KR20060084039A - Semiconductor memory device - Google Patents

Abstract

The present invention discloses a semiconductor memory device. The device includes a memory cell array disposed in a memory cell array region, first and second peripheral circuit regions disposed in first and second peripheral circuit regions disposed opposite to both sides of the memory cell array region, and the memory cell array region. Main word lines arranged in an upper layer, column select signal lines arranged in a direction orthogonal to the main word lines in a layer different from a layer in which the main word lines on the memory cell array region are arranged; The memory cell may include peripheral circuit signal lines arranged on a different layer from a layer on which the main word lines and the column select signal lines are disposed on a memory cell array area, and which connect the first and second peripheral circuits. And disposed across the array area. Therefore, the load of the peripheral circuit signal line is reduced to improve the operation performance, and the layout area of the peripheral circuit region is reduced.

Description

Semiconductor memory device

1A and 1B are diagrams showing an example of arrangement of peripheral circuit signal lines of a conventional semiconductor memory device.

2A and 2B are diagrams showing the arrangement of the peripheral circuit signal lines of the semiconductor memory device of the first embodiment of the present invention.

3A and 3B are diagrams showing the arrangement of the peripheral circuit signal lines of the semiconductor memory device of the second embodiment of the present invention.

4A and 4B are diagrams showing the arrangement of the peripheral circuit signal lines of the semiconductor memory device of the third embodiment of the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device which solves a signal delay problem caused by arranging signal lines transferring signals between memory peripheral circuit areas around a cell array and reduces layout area.

In the conventional semiconductor memory device, when a signal is transmitted between peripheral circuit regions, a signal is arranged by arranging lines with a peripheral circuit region other than the memory cell region as a path.

1A and 1B illustrate an arrangement structure of peripheral circuit signal lines of a conventional semiconductor memory device, where 10 is a memory cell array region, PXi is a word select signal line, NWL is a main word line, and LIO is a local input / output. Line, CSL is the column select signal line, GIO is the global I / O line, PCL is the peripheral circuit signal line, 20 is the row decoder area, 30 is the column decoder area, 40 is the peripheral circuit upper area, 42 is the peripheral circuit lower area, 44 is divided into a peripheral circuit left region and 46 is a peripheral circuit right region.

The block functions and signal line arrangement shown in FIGS. 1A and 1B will be described below.

The memory cell array area 10 includes a plurality of memory cells (not shown), and the plurality of memory cells (not shown) are a combination of transmission signals of a word select signal line PXi and a main word line NWL. Is selected.

The word select signal line PXi is connected to the row decoder 20, is selected by decoding the row address of the least two bits among the row addresses, and is disposed on the first metal layer.

The main word line NWL is connected to the row decoder 20 and is selected by decoding the row address of the remaining bits except the lowest two bits among the row addresses, and is disposed on the top / bottom of the memory cell array 10. It arrange | positions to a 1st metal layer in a downward direction.

The local input / output line (LIO) is connected to the global input / output lines (GIO) and transmits data to / from the global input / output line (GIO), and the upper / lower direction above the memory cell array 10 is provided. 1 is disposed in the metal layer.

The column select signal line CSL is connected to the column decoder 30 and is activated by receiving a signal from the column decoder 30 and transmits signals to and from a bit line (not shown) and a local input / output line (LIO). The second metal layer is disposed on the memory cell array 10 in the left and right directions.

The row decoder 20 is connected to the word select signal line PXi and the main word line NWL, receives the externally input data address signal, decodes the main word line NWL, and selects the memory cell array. It is arrange | positioned under (10).

The column decoder 30 is connected to a column select signal line CSL, receives a data address signal input from an external source, decodes the column select signal line CSL, and selects a column select signal line CSL on the right side of the memory cell array 10. To place.

Peripheral circuit regions 40, 42, 44, and 46 are disposed on the outside in a shape surrounding the memory cell array 10, the row decoder 20, and the column decoder 30. The peripheral circuit lower region 42 is disposed to face each other, and the peripheral circuit left region 44 and the peripheral circuit right region 46 are disposed to face each other.

In this case, in the conventional semiconductor memory device, as shown in FIG. 1A, the peripheral circuit upper region 40 or the peripheral circuit lower side in order to transmit a signal from the left region 44 of the peripheral circuit to the circuit of the right region 46 of the peripheral circuit. The peripheral circuit signal line PCL was disposed via the region 42.                         

In addition, as shown in FIG. 1B, in order to transmit a circuit of the peripheral circuit upper region 40 to the circuit of the peripheral circuit lower region 42 via the peripheral circuit left region 42 or the peripheral circuit right region 44. Peripheral signal lines (PCLs) were placed.

Therefore, the peripheral circuit signal lines PCL are disposed in the peripheral circuit areas 40, 42, 44, and 46, and thus the layout area is widened. As the directivity of the semiconductor memory device increases, the layout of the layout for the peripheral circuits is increased. It became more and more difficult to secure.

In addition, as the length of the peripheral circuit signal line PCL increases, the loading of the signal line increases, thereby deteriorating the operating performance of the semiconductor memory device.

In order to solve the above-described problems, a method of arranging the peripheral circuit signal line PCL on the metal layer on which the word select signal line PXi and the main word line NWL or the column select signal line CSL are arranged may be considered. In the semiconductor memory device having high directivity and reduced layout area, the arrangement of the peripheral circuit signal line PCL between the word select signal line PXi and the column select signal line CSL is realized due to the coupling effect between the signal lines. There is a difficulty.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device in which peripheral circuit signal lines are disposed on a memory cell array region, thereby minimizing an area occupied by a region of peripheral circuits, and minimizing loading by shortening peripheral circuit signal lines. There is.

The semiconductor memory device of the present invention for achieving the above object is, the memory cell array disposed in the memory cell array region, the first and second peripheral circuit regions disposed facing both sides of the memory cell array region, First and second peripheral circuits, main word lines arranged in a layer above the memory cell array region, and perpendicular to the main word lines in a different layer than the layer in which the main word lines above the memory cell array region are arranged; Column select signal lines arranged in a direction different from the layer in which the main word lines and the column select signal lines on the memory cell array area are disposed, and the first peripheral circuit and the second peripheral circuit Peripheral circuit signal lines connecting the circuits may be disposed across the memory cell array region.

Hereinafter, a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

2A and 2B are diagrams for explaining an arrangement structure of a peripheral circuit signal line of a semiconductor memory device according to a first embodiment of the present invention. The same blocks and the same signal lines shown in FIGS. 1A and 1B are denoted by the same symbols. 1A and 1B are the same except that a clock input pad 50, an internal clock generator 52, a data output buffer 54, and an output pad 56 are added to illustrate one example. . In addition, since the functions of the respective blocks and signal lines other than the added circuits are the same, a description thereof will be omitted.

For example, an internal clock generator 52 that receives a signal from an external clock input pad 50 and generates a clock signal ICLK, and a data output that receives the clock signal ICLK and transmits the clock signal ICLK to an output pad 46. When arranging the peripheral circuit signal line PCL for connecting the buffer 54, as shown in FIG. 2A, the internal clock generator 52 is provided in the peripheral circuit right region 44, and outputs the data. When the buffer 54 is provided in the left area 46 of the peripheral circuit, the peripheral circuit signal line PCL may be formed in the peripheral circuit area other than the area of the signal lines disposed in the first metal layer and the second metal layer on the memory cell array. The peripheral circuit signal line PCL is disposed in the third metal layer on the memory cell array 10, unlike the peripheral circuit signal line PCL via 40 and 42.

As shown in FIG. 2B, the internal clock generator 52 is provided in the upper region 40 of the peripheral circuit, and the data output buffer 54 is provided in the lower region 42 of the peripheral circuit. The signal line PCL is disposed through the peripheral circuit areas 44 and 46 other than the areas of the signal lines disposed in the first metal layer and the second metal layer on the memory cell array. Alternatively, the peripheral circuit signal line PCL is disposed on the third metal layer on the memory cell array 10.

The arrangement of the peripheral circuit signal lines of the semiconductor memory device shown in FIGS. 2A and 2B is as follows.

The word select signal line PXi, the main word line NWL, and the local input / output line LIO are disposed in the first metal layer on the memory cell array 10 in the direction of the row decoder 20.

The column select signal line CSL and the global input / output line GIO are disposed on the second metal layer on the memory cell array 10 in the direction of the column decoder 30.

The peripheral circuit signal line PCL is disposed in the third metal layer on the memory cell array 10 in the direction of the column decoder 30.

Therefore, since the peripheral circuit signal line PCL is disposed on a different layer from the column select signal line CSL and the global input / output line GIO, coupling of the column select signal line CSL and the global input / output line GIO is performed. It is not affected.

In addition, the peripheral circuit signal lines PCL are disposed by crossing the memory cell array 10 without passing through the peripheral circuit upper and lower regions 40 and 42 and the peripheral circuit left and right regions 44 and 46. By reducing the allocated space, the layout area can be reduced, and the loading can be reduced, thereby increasing the efficiency of the semiconductor memory device.

3A and 3B are diagrams illustrating an arrangement structure of peripheral circuit signal lines of a semiconductor memory device in accordance with a second embodiment of the present invention, in which the same blocks and the same signal lines are denoted by the same reference numerals. 2A and 2B are identical except that the circuit signal line PCL is disposed on the second metal layer, and the column select signal line CSL and the global input / output line GIO are disposed on the third metal layer. In addition, since the functions of the respective blocks and signal lines of FIGS. 3A and 3B are the same as those of FIGS. 2A and 2B, description thereof will be omitted.

The arrangement of the peripheral circuit signal lines of the semiconductor memory device shown in FIGS. 3A and 3B is as follows.

The word select signal line PXi, the main word line NWL, and the local input / output line LIO are disposed on the first metal layer on the memory cell array 10 in the row decoder direction 20.

The peripheral circuit signal line PCL is disposed on the second metal layer on the memory cell array region 10 in the direction of the column decoder 30.

The column select signal line CSL and the global input / output line GIO are disposed on the third metal layer on the memory cell array 10 in the column decoder direction 30.

4A and 4B are diagrams illustrating an arrangement structure of signal circuits of a peripheral circuit of a semiconductor memory device according to a third exemplary embodiment of the present invention, in which the same blocks and the same signal lines are denoted by the same reference numerals, and FIGS. 4A and 4B are peripherals. The circuit signal line PCL is disposed on the first metal layer, the word select signal line PXi, the main word line NWL, and the local input / output line LIO are disposed on the second metal layer, and the column select signal line CSL is disposed. 3A and 3B except that the global input / output line GIO is disposed on the third metal layer. In addition, since the functions of the blocks and signal lines of FIGS. 4A and 4B are the same as those of FIGS. 3A and 3B, description thereof will be omitted.

The arrangement of the peripheral circuit signal lines of the semiconductor memory device shown in FIGS. 4A and 4B is as follows.

The peripheral circuit signal line PCL is disposed on the first metal layer on the memory cell array region 10 in the direction of the column decoder 30.

The word select signal line PXi, the main word line NWL, and the local input / output line LIO are disposed on the second metal layer on the memory cell array 10 in the row decoder direction 20.

The column select signal line CSL and the global input / output line GIO are disposed on the third metal layer on the memory cell array 10 in the column decoder direction 30.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Therefore, the arrangement of the signal lines between the peripheral circuit regions of the semiconductor memory device is arranged over the memory cell array region in the other metal layer of the word line selection signal line and the column selection signal line. Accordingly, the loading of the peripheral circuit signal line is reduced to improve performance, and the layout area of the peripheral circuit region is reduced.

Claims (4)

A memory cell array disposed in the memory cell array area; First and second peripheral circuits disposed in first and second peripheral circuit regions facing each other on both sides of the memory cell array region; Main word lines disposed in a layer above the memory cell array area; Column select signal lines arranged in a direction orthogonal to the main word lines on a layer different from the layer on which the main word lines are disposed on the memory cell array area; The memory circuit may include peripheral circuit signal lines disposed on a layer different from a layer in which the main word lines and the column select signal lines are disposed on the memory cell array area, and connect the first and second peripheral circuits. And disposed across the cell array region. According to claim 1, And the main word lines, column select signal lines, and the peripheral circuit signal lines are made of metal. The method of claim 1, wherein the peripheral circuit signal lines And a semiconductor memory device arranged in the same direction as the main word lines. The method of claim 1, wherein the peripheral circuit signal line And the column selection signal lines in the same direction.

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