KR101598829B1 - Semiconductor package of stacked chips having an improved data bus structure semiconductor memory module and semiconductor memory system having the same - Google Patents

Abstract

A semiconductor package comprising a plurality of stacked chips having an improved data bus structure is disclosed. According to one embodiment of the semiconductor package, at least one master chip is in communication with an external memory controller, and at least one master chip, which is stacked on the at least one master chip, Wherein the plurality of chips includes a plurality of memory banks, and the at least one first memory bank and the at least one first memory bank are communicated with the same master chip and classified into different ranks, Two memory banks are provided.

Description

[0001] The present invention relates to a semiconductor package, a semiconductor memory module, and a semiconductor memory system having a stacked structure having an improved data bus structure,

The present invention relates to a stacked semiconductor package, and more particularly, to a stacked semiconductor package having an improved data bus structure for efficient data transfer.

In recent years, the capacity and speed of a semiconductor memory used as a memory device in most electronic systems have been increasing. Various attempts have been made to implement a memory of a larger capacity in a narrower area and to efficiently drive the memory.

2. Description of the Related Art [0002] In recent years, in order to improve integration of a semiconductor memory, a three-dimensional structure (3D) arrangement technique in which a plurality of memory chips are stacked in a conventional plane arrangement (2D) system has begun to be applied. There may be a demand for a structure that increases the capacity by using the 3D arrangement structure of the memory chip while simultaneously reducing the semiconductor chip size and improving the integration degree in accordance with the trend of high integration and high memory requirement.

Meanwhile, in order to efficiently drive the semiconductor memories, the concept of a bank on a semiconductor chip and the concept of a rank on a module structure may be introduced. The concept of the DRAM device will be described as follows .

Typically, a memory core in a DRAM chip may have a plurality of memory banks. A memory bank can be defined as a set of memory cells that simultaneously activate a memory to be accessed, and is typically divided by a bank address (BA). Typically, a read / write command between a bank and a bank defines a parameter called a column to column delay (tCCD) in order to ensure the operation cycle of one memory bank, As shown in Fig.

On the other hand, on a memory module including one or more DRAM chips, a rank may be defined as a set of DRAM chips receiving the same command, bank address, and address (C / BA / A) at the same time. Generally, a rank is divided using a chip select signal CS provided to a memory module, and interleaving operations between ranks are mainly used for efficient use of data and command buses.

In order to efficiently access data from the memory, the above-described bank and rank concepts can be appropriately used. However, since a collision may occur between signal lines for communication between the memory module and the memory controller and signals transmitted and received on the signal transmission path in the memory chip of the memory module, a bank and a rank structure may be applied Proper placement of the signal bus along with time is required. Particularly, in a semiconductor package having a 3D arrangement structure for improving the integration degree of a memory package, it is necessary to increase the efficiency of data access other than the improvement of the integration degree. Accordingly, the signal line bus to be applied to the semiconductor package of the 3D arrangement structure is optimized It is necessary to implement it.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor package, a semiconductor memory module, and a semiconductor memory module each having an optimal data bus structure while applying the concept of a bank, a bank group, and a rank, It is an object of the present invention to provide a semiconductor memory system.

In order to achieve the above object, a semiconductor package according to an embodiment of the present invention includes at least one master chip having a plurality of stacked chips and communicating with an external memory controller, At least one slave chip stacked on a master chip and communicating with the master chip via one or more conductive means, the plurality of chips including a plurality of memory banks, communicating with the same master chip, And at least one first memory bank and at least one second memory bank that are separated by different ranks.

Advantageously, the at least one master chip and the at least one slave chip are each divided into different ranks.

Also preferably, the at least one master chip has a master area which operates in response to a global control signal and which interfaces with the memory controller, wherein the at least one slave chip is operable in response to a local control signal, And a slave area for performing an interface with the master chip.

Preferably, the at least one master chip includes a first decoder for receiving and decoding a first command related to the master area control, a second decoder for receiving and decoding a second command related to the slave area control, And a computing unit for receiving a chip selection signal provided to each of the master chip and the slave chip and performing a logic operation and providing the computation result to the first decoder and a command decoder unit including a first decoder and a second decoder, For generating the global control signal based on a combination of the output of the first decoder and the address or a combination of the output of the first decoder and the address, And an address decoder for generating a control signal.

Each of the at least one master chip has a master area for transmitting / receiving data to / from the memory controller, and a unidirectional data bus is disposed in the master area.

The at least one conductive means is a via formed in the at least one master chip and / or the at least one slave chip.

The at least one master chip may comprise a master chip, and the at least one slave chip may comprise a plurality of slave chips communicating with the one master chip.

On the other hand, a plurality of bank groups are defined, and each bank group includes one or more memory banks of the plurality of memory banks included in the plurality of chips, and a data bus for transmitting and receiving data is connected to each of the bank groups And are arranged so as to correspond to each other.

Preferably, at least two memory banks arranged on different chips of the plurality of memory banks and arranged vertically to each other are set as one bank group.

At least two memory banks, which are provided in different chips and are arranged vertically to each other, are defined as one rank among the plurality of memory banks.

According to another aspect of the present invention, there is provided a semiconductor package including at least one master chip including a master area communicating with an external memory controller, And at least one slave chip including a slave area communicating with the master chip, wherein, for a plurality of memory banks provided in the master chip and / or the at least one slave chip, Wherein each bank group includes at least one memory bank and a data bus for transmitting and receiving data is arranged to correspond to each of the bank groups.

According to another aspect of the present invention, there is provided a semiconductor package comprising: a master chip including an input circuit and an output circuit for communicating with an external memory controller; Wherein a data transmission / reception distance of data between the master chip and the slave chip is controlled by a memory bank and a via in the slave chip when the master chip and the slave chip are communicating with each other via the slave chip, And a second path between the via and the input circuit or output circuit in the master chip, wherein the first path has a relatively short distance relative to the second path .

According to another aspect of the present invention, there is provided a semiconductor package including a plurality of stacked chips and a master area for transmitting and receiving data to and from a memory controller through an external data bus, At least one first semiconductor chip in which a first data bus is disposed and at least one second semiconductor chip stacked in the at least one first semiconductor chip and including a slave region for transmitting and receiving data through the master region and the second data bus At least one of a rank and a bank-group defined in the semiconductor package has a plurality of numbers, and the structure of the first data bus and / or the second data bus The number of rank and the number of bank-groups of the external data bus, Characterized in that the crystal.

According to another aspect of the present invention, there is provided a semiconductor memory module, comprising: at least one semiconductor memory package having a plurality of stacked chips; a semiconductor memory package mounted on one surface of the semiconductor memory package; Wherein the semiconductor memory package comprises: at least one master chip in communication with the memory controller; and at least one master chip, stacked on the at least one master chip, And at least one second memory bank and at least one second memory bank having at least one slave chip communicating with each other and communicating with the same master chip and being divided into different ranks

According to another aspect of the present invention, there is provided a semiconductor memory system including: a semiconductor memory module having at least one semiconductor memory package attached thereto, each semiconductor memory package having a plurality of stacked chips; And a memory controller for controlling a memory read / write operation of the semiconductor memory module, wherein the semiconductor memory package is stacked on at least one master chip and at least one master chip in communication with the memory controller, And at least one first memory bank having at least one slave chip communicating with the master chip through one or more conductive means and communicating with the same master chip and being divided into different ranks, Two memory banks are provided.

According to the semiconductor package, the semiconductor memory module and the semiconductor memory system of the present invention as described above, it is possible to improve the degree of integration of the memory, and at the same time, it is possible to improve the integration ratio of the memory, The data bus structure of FIG.

In order to fully understand the present invention, operational advantages of the present invention, and objects achieved by the practice of the present invention, reference should be made to the accompanying drawings and the accompanying drawings which illustrate preferred embodiments of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

1A and 1B are block diagrams showing a semiconductor memory module according to an embodiment of the present invention. A memory controller 20 for sending and receiving data to and from the semiconductor memory module 10 and for providing commands and addresses for controlling the semiconductor memory module 10 is also shown for convenience of explanation.

As shown in FIG. 1A, the semiconductor memory module 10 may include one or more semiconductor packages, for example, the semiconductor memory module 10 may include a plurality of semiconductor packages attached to one side thereof. Each semiconductor package may also include one or more semiconductor chips. In one embodiment of the present invention, a plurality of semiconductor chips 11 to 14 in which respective semiconductor packages are stacked are provided. The first semiconductor chip 11 stacked at the bottom may be a master chip, and the first semiconductor chip 11 may include a master area (not shown) for interfacing with the outside of the semiconductor package. The first semiconductor chip 11 may further include a slave area (not shown) for interfacing with the master area to perform a read / write operation of a memory in the chip, and the slave area may be electrically connected to the master area And transmits and receives various control signals and data to and from the master area according to the connection.

Meanwhile, the second to fourth semiconductor chips 12 to 14 stacked on the first semiconductor chip 11 may be a slave chip including a slave region. The second to fourth semiconductor chips 12 to 14 are electrically connected to the master region of the first semiconductor chip 11. For this purpose, a conductive means for connecting the chips to each other may be provided in the semiconductor package . Since the semiconductor package includes a plurality of stacked semiconductor chips, a through silicon via (TSV) may be preferably used as the conductive means. To use the TSV as a conductive means between the semiconductor chips, one or more semiconductor chips in the semiconductor package may have one or more vias formed therethrough vertically.

In FIG. 1A, four semiconductor chips are stacked in one semiconductor package as one embodiment of the present invention. The four semiconductor chips include one master chip 11 disposed on the lowest layer and three slave chips (12 to 14), but the present invention is not necessarily limited to this. As an example, fewer or more semiconductor chips may be stacked vertically in each semiconductor package, and more than one master chip may be placed in each semiconductor package.

The memory controller 20 transmits and receives the chip select signal CS, the command and the address C / A, and the data DQ to and from the semiconductor memory module 10 via the respective buses BUS. As a signal transfer characteristic between the semiconductor memory module 10 and the memory controller 20, the chip select signal CS is provided to a plurality of semiconductor packages through a common bus CS BUS. The command and address (C / A) are also provided in a plurality of semiconductor packages via a common bus (C / A BUS). On the other hand, in order to transmit and receive the input data and the output data DQ between the semiconductor memory module 10 and the memory controller 20, the data bus DQ BUS is arranged to be divided for each semiconductor package. 1A shows an example in which the semiconductor memory module 10 and the memory controller 20 transmit and receive input data and output data via a bidirectional data bus on the same bus.

FIG. 1B shows one semiconductor package attached to the semiconductor memory module 10 and including the first to fourth semiconductor chips 11 to 14. Chip select signal lines for providing a chip select signal CS [3: 0] to the semiconductor package are commonly connected to a plurality of semiconductor packages, and the data bus DQ BUS shown in FIG. Directional data bus for transferring data between the memory controller 20 and the memory controller 20. The first semiconductor chip 11 interfaces with the memory controller 20 via a master area provided in the first semiconductor chip 11. The command / address and data provided to the master area are transmitted to the second semiconductor chip 11 as one or more slave chips 4 semiconductor chips 12 to 14, respectively.

2A and 2B are block diagrams showing a semiconductor memory module according to another embodiment of the present invention. 2A and 2B, a memory controller 40 for transmitting / receiving a command / address and data to / from the semiconductor memory module 30 is also shown for convenience of explanation. Particularly, the semiconductor memory module 30 and the memory controller 40 shown in FIGS. 2A and 2B transmit and receive data through the unidirectional data bus, and accordingly receive the write data from the memory controller 40 to the semiconductor memory module 30 and the read data provided from the semiconductor memory module 30 to the memory controller 40 have different signal transmission paths.

The semiconductor package attached to the semiconductor memory module 30 may include a plurality of vertically stacked chips. The first semiconductor chip 31 stacked at the bottom may be a master chip, The two semiconductor chips to the fourth semiconductor chips 32 to 34 may be provided as slave chips. As described above, the first semiconductor chip 31 may further include a slave area for interfacing with the master area and for reading / writing the memory in the chip, in addition to a master area for interfacing with the memory controller 40 have.

Each of the semiconductor packages attached to the semiconductor memory module 30 includes a bus (C / A / WD BUS) for receiving command / address and write data from the memory controller 40, To the memory controller 40 via a bus (RD BUS) for providing read data to the memory controller 40. The semiconductor memory module 30 receives the command C, the address A and the write data WD including the chip selection signal on a frame basis and outputs the received command C, address A, Or writes the data RD to the memory controller 40 in response to the received command C and the address A in response to the command WD.

FIG. 2B shows one semiconductor package attached to the semiconductor memory module 30 and including the first to fourth semiconductor chips 31 to 34. As shown, the semiconductor package transmits and receives data to and from the memory controller 40 through a unidirectional data bus. As an example, the semiconductor package receives data from the memory controller 40 via a write data bus WD when writing data. When data is read, the semiconductor package provides the read data to the memory controller 40 via the write data bus RD.

As described above, the semiconductor package according to an embodiment of the present invention may include a plurality of semiconductor chips in a stacked structure, and each semiconductor chip may include one or more memory banks. Particularly, a semiconductor package according to an embodiment of the present invention including a stacked semiconductor chip includes at least one first memory bank and at least one second memory bank, which communicate with the same master chip and are divided into different ranks, A memory bank may be provided. For example, the first to fourth semiconductor chips provided in the semiconductor package may be divided into first to fourth ranks, respectively. Alternatively, a plurality of memory banks distributed in a plurality of chips may be divided into a rank, and a plurality of other memory banks distributed in the plurality of chips may be divided into another rank.

In addition, the concept of a bank group may be applied to the semiconductor package according to an embodiment of the present invention. A bank group is defined as one group of one or more banks and is usually divided by a bank address or a bank group address. The above concept is used as a method for improving data transmission through an interleaving operation between bank groups. That is, in the interleaving operation between the bank and the bank, a data transfer amount is limited by a column-to-column delay time (tCDD) having a large value, but a plurality of bank groups are defined And performs the interleaving operation between the bank groups by a small value of the column-to-column delay time (tCDD) to improve the data transfer amount.

According to an embodiment of the present invention, a bank group may be defined similarly to the manner of defining the rank. That is, the memory banks included in one semiconductor chip may be defined as one bank group, and the memory banks included in another semiconductor chip may be defined as another bank group. Or a plurality of memory banks included in a plurality of semiconductor chips are defined as one bank group and a plurality of other memory banks included in the plurality of semiconductor chips are defined as another bank group . The manner of defining a rank and a bank group according to the embodiment of the present invention will be described in detail later.

In a structure of a semiconductor package including a semiconductor chip of a stacked structure in which at least one bus is shared by a plurality of chips, a signal is transmitted between signals transmitted and received by performing interleaving of rank and / or interleaving of a bank group Conflicts can occur. Accordingly, the structure of the command / address bus and the data bus must be appropriately changed depending on the characteristics of the rank and the bank group defined in the semiconductor package. Particularly, interleaving may cause collision of data when data is transmitted / received between different ranks or when data is transmitted / received between different bank groups. Therefore, a data bus for transmitting / receiving data in a semiconductor package A change in structure is required. As described above, since the semiconductor memory module can transmit and receive data through an external memory controller and a bidirectional data bus or a unidirectional data bus, the data bus structure in the semiconductor package can be used as a data bus structure between the semiconductor memory module and the memory controller It is also desirable to be considered.

3A and 3B are waveform diagrams showing an example of a data collision when a plurality of ranks or a plurality of bank groups are applied to one semiconductor package.

3A shows a case where a plurality of ranks are defined in a semiconductor package and a master area of the master chip has a bidirectional data bus. It is assumed that a read operation is performed on a memory bank corresponding to rank 0 and a write operation is performed on a memory bank corresponding to rank 1 (rank 1).

An internal command / address is generated in response to a command / address provided from an external memory controller, and data RD [3: 0] is read from a memory bank of rank 0 after a predetermined address decoding time. The read data RD [3: 0] is transferred to the master chip through a data bus provided in the master area through a predetermined propagation delay time. The read data RD [3: 0] transferred to the master chip is converted into serial data and supplied to an external memory controller.

By a rank interleaving operation, a write command for a memory bank of rank 1 is input after a predetermined time after a read command for rank 0 (rank 0). Write data (WD [3: 0]) converted into parallel data after a predetermined time is transferred to the data bus of the master area after an external command / address and data are input, And write data WD [3: 0] is transferred to the data bus of the slave area.

As shown in the figure, during the above-mentioned rank interleaving operation, the read data RD [3: 0] for rank 0 and the write data for rank 1 (rank 1) on the bidirectional data bus provided in the master area (WD [3: 0]) occurs. That is, according to this, when a plurality of ranks are defined in one semiconductor package, the master area needs to be applied with a unidirectional data bus for data transmission and reception.

FIG. 3B shows a data collision during the interleaving operation between the bank groups. As an example, a plurality of bank groups are defined in one rank and operations in a structure in which different bank groups share a data bus are shown.

FIG. 3B shows the interleaving operation between the bank group 0 (BG0) and the bank group 1 (BG1) related to the read operation. As shown, a command / address for bank group 0 (BG0) and a command / address for bank group 1 (BG1) are sequentially provided. The read data RD [3: 0] _BG0 from the bank group 0 (BG0) is transferred to the data bus of the slave area with the address decoding time as an interval after the provision of the command / The read data RD [3: 0] _BG1 from the master device is transferred to the data bus of the slave area.

The read data RD [3: 0] _BG0 of the bank group 0 (BG0) and the read data RD [3: 0] _BG1 of the bank group 1 (BG1) transferred to the data buses of the respective slave areas are transferred to the master Area data bus. In this case, a collision occurs between the read data RD [3: 0] _BG0 of the bank group 0 (BG0) and the read data RD [3: 0] _BG1 of the bank group 1 (BG1) Occurs.

3B shows the interleaving operation between the bank group 0 (BG0) and the bank group 1 (BG1) related to the write operation. As shown, a command / address and data for bank group 0 (BG0) and a command / address and data for bank group 1 (BG1) are sequentially provided.

The externally supplied data is supplied to the data bus of the master area as write data through a parallelization process. In this case, the write data WD [3: 0] _BG0 for the bank group 0 (BG0) and the write data WD [3: 0] _BG1 for the bank group 1 (BG1) . Accordingly, when a plurality of bank groups are defined in one rank, the data buses need to be independently arranged corresponding to the respective bank groups.

4A and 4B are block diagrams showing a structure of a semiconductor chip applied to a semiconductor package according to an embodiment of the present invention. 4A shows an example of a master chip in which a semiconductor package transmits and receives data via an external memory controller (not shown) and a bidirectional data bus, and FIG. 4B shows an example in which a semiconductor package is connected to an external memory controller and a unidirectional data bus Fig. 2 is a block diagram of a master chip according to the present invention; Fig. Particularly, FIGS. 4A and 4B show an embodiment in which a plurality of bank groups are defined in a semiconductor package. In the structures shown in FIGS. 4A and 4B, slave regions (memory banks, A column address decoder, and the like) may be understood as a structure provided in a slave chip.

The semiconductor chip 50 (for example, a master chip) of FIG. 4A may have a plurality of memory banks, and some of the memory banks and some of the other memory banks may be defined as different bank groups. As shown, the semiconductor chip 50 may include memory banks defined as a first bank group 0 and memory banks defined as a second bank group 1.

The semiconductor chip 50 includes various circuit blocks for controlling the read / write operation of the memory banks. For example, in order to control the operation of the memory banks 51 of the first bank group (bank group 0), the row address decoder 52, the column address decoder 53, the bank control section 54 and the input / (55). The semiconductor chip 50 is also provided with a control logic 56 including a mode register set (MRS, 56_1) and a command decoder 56_2, an address register 57 for temporarily storing an address, a bank for controlling a bank group A data input unit 59_1 and a data output unit 59_2 for controlling data input / output with the group control unit 58 and the external memory controller (not shown). Although not shown, the semiconductor chip 50 is provided with circuit blocks (e.g., a bank group (not shown) for controlling memory banks defined as a second bank group and other bank groups 1), a bank control unit, and an input / output control unit).

As shown in the figure, a plurality of memory banks 51, which are defined as a first bank group (bank group 0), correspond to decoding results of the row address decoder 52 and the column address decoder 513 and the decoding results of the bank control unit 54, Output driver section 55 or outputs the read data to the input / output driver section 115 under the control of the input / The control logic 56 receives a command CMD received from the outside based on the setting of the mode register set 56_1 and performs a decoding operation. The address register 57 temporarily stores the received address ADDR and provides an address related to the bank group control to the bank group control unit 58 and supplies the row and column addresses to the row address decoder 52 and the column address decoder 52, (53). Data is written to any one of the banks of the plurality of memory banks 51 using the received command CMD and address ADDR and the write data received through the data input unit 59_1, And outputs the data read out from any one of the banks of the plurality of memory banks 51 to the outside through the data output unit 59_2 in response to the address CMD and the address ADDR.

The semiconductor chip 60 shown in FIG. 4B has a plurality of bank groups (for example, a first bank group 0, 210, a second bank group 1, 220) And circuit blocks for transmitting and receiving data in an unidirectional manner with an external controller. The semiconductor chip 60 includes a memory bank 61 defined by a bank group and a row address decoder 62 and a column address decoder 63 associated with the operation of the memory bank 61, A bank control unit 64, an input / output driver unit 65, and the like. The semiconductor chip 60 is also provided with control logic (not shown) including a frame logic decoder 66, a mode register set 67_1 and a command decoder 67_2 to control a plurality of bank groups included in the semiconductor chip 60 67, an address register 68 for temporarily storing an address, a bank group control unit 69 for controlling a bank group, and a data output unit 70 for outputting data to the outside. The frame logic decoder 66 decodes the signal received on a frame basis to generate the command CMD, the address ADDR and the input data DIN respectively and supplies them to the control logic 67, the address register 68, And supplies them to the driver section 65, respectively. On the other hand, the data read from the predetermined memory block in response to the command CMD and the address ADDR is supplied to the outside via the data output unit 70. [

5 is a circuit diagram schematically illustrating a data path between semiconductor chips included in a semiconductor package according to an embodiment of the present invention. As shown in FIG. 5, the semiconductor package 110 may include a plurality of stacked chips, and the first semiconductor chip 111 is a master chip including a master area, and interfaces with an external memory controller, Address and data to / from a slave area of another chip stacked on the chip and / or a slave area of other chips stacked thereon. The second semiconductor chip 112 stacked on the first semiconductor chip 111 is a slave chip including a memory bank therein and a slave region for an interface between the memory bank and the master region.

According to an embodiment of the present invention, a plurality of semiconductor chips in the semiconductor package 110 are provided with a plurality of memory banks controlled by the same master chip (for example, the first semiconductor chip 111) The first memory bank of the first memory bank and the second memory bank of the at least one second memory bank are classified into different ranks. 4, the memory banks provided in the first semiconductor chip 111 are defined as a first rank (rank 0), and the memory banks provided in the second semiconductor chip 112 The banks are defined as the second rank (rank 1). When more chips are stacked in the semiconductor package 110, the memory banks included in the added chips may be defined as a third rank (rank 2), a fourth rank (rank 3), and the like.

As described above, when a plurality of ranks are defined in the semiconductor package 110, data collision occurs when the data bus of the master area is arranged as a bidirectional data bus. Accordingly, the master area 111a included in the first semiconductor chip 111 is provided with a unidirectional data bus. As an example, a plurality of ranks may be defined in the semiconductor package 110, regardless of whether the semiconductor package 110 and an external memory controller (not shown) transmit or receive data to either the bidirectional data bus or the unidirectional data bus The master area 111a is provided with a unidirectional data bus. The through silicon via (TSV) connected to the master region 111a to transfer data to the plurality of semiconductor chips allows the vias for the path of the read data and the vias for the path of the write data to be formed separately.

Since data corresponding to a plurality of ranks occurs on the data bus of the master region 111a, the slave region 111b or the second semiconductor chip 112 The bidirectional data bus may be applied to the data bus of the slave region 112a.

6A and 6B are block diagrams illustrating interfaces between a master area and a slave area. FIG. 6A shows a case where a master area and a slave area transmit / receive data through a bidirectional data bus, and FIG. 6B shows a case where a master area and a slave area transmit / receive data through a unidirectional data bus.

The master area 121 in the semiconductor package 120 is provided in the master chip and includes logic circuits such as an input buffer and an output buffer for transmitting and receiving data to and from an external memory controller (not shown). The data bus provided in the master area 121 is commonly used for the master chip and one or more slave chips stacked on the master chip. The master area 121 shown in FIG. 6 transmits and receives data through an external memory controller and a bidirectional data bus, and is connected to a through silicon via 121a for transferring data in both directions to transmit and receive slave areas and data in both directions .

The through silicon via 121a shown in the figure is formed on the master chip and the data transferred to the data bus of the master region 61 through the through silicon via 121a is transferred to the slave region provided in the slave chips . The slave area is connected to the corresponding memory bank 123, the sense amplifier and the driver 124 and receives data related to the read operation and the write operation from the memory bank 123 or provides the data to the memory bank 123. In addition, although the through silicon vias 121a are shown as one line, it is obvious that a plurality of vias for transmitting a plurality of data in parallel can be formed.

6B shows a case where the master area 131 in the semiconductor package 130 transmits / receives data to / from an external memory controller through a separate input / output pad in a unidirectional manner. Correspondingly, the master area 131 also has a unidirectional data bus therein. When the slave region 132 is formed in the second semiconductor chip stacked adjacent to the first semiconductor chip including the master region 131, the slave region 132 is formed in the via-silicon via 131a. The slave region 132 provides the data received through the through silicon via 131a to the memory bank 133 and the sense amplifier and driver 134 or to the memory bank 133 and the sense amplifier and driver 134 from the memory bank 133, And provides the data to the master region 131 through the through silicon via 131a. Since the master region 131 transmits and receives data to and from the slave region 132 via the unidirectional data bus, the via silicon via 131a can be formed by dividing the via connected to the read data bus and the via connected to the write data bus have.

7A and 7B are block diagrams of a control signal generator for generating control signals for controlling the master area and the slave area. A master area provided in the master chip is commonly used for a plurality of chips, and is controlled to operate in response to a global control signal. On the other hand, the slave area included in the master chip and / or the slave chip is used independently for the chip, and the operation is controlled in response to the local control signal.

7A shows a case where a plurality of ranks are defined in the semiconductor package. The control signal generator 210 is provided in the master area and receives a chip selection signal CS [n: 0] from an external memory controller (not shown) ), Commands and addresses ADDR [m: 0] of RAS, CA, WE, and the like. The control signal generation unit 210 may include a command decoder unit 211 and an address decoder unit 212. The command decoder unit 211 further includes an operation unit 211_1 for receiving the chip select signal CS [n: 0] and performing a logical operation on the chip select signal CS [n: 0], a first decoder for decoding the first command related to the global control signal And a second decoder 211_3 for decoding the first command related to the local control signal. The address decoder unit 212 also includes a buffer 212_1 for receiving the address ADDR [m: 0] and temporarily storing the address ADDR [m: 0] And a third decoder 212_2 for generating a global control signal GCS and a local control signal LCS using the outputs of the decoder 211_2 and the second decoder 211_3.

The operation unit 211_1 receives at least one chip selection signal CS [n: 0] and performs a logical operation (for example, a logical sum (OR) operation) . Also, the at least one chip selection signal CS [n: 0] is provided to the second decoder 211_3. That is, when two or more chip selection signals CS [n: 0] are activated to control a plurality of chips (for example, a plurality of ranks), the first decoder 211_2 outputs RAS, CA, WE, and the like, and generates a decoding result CMD_M accordingly. On the other hand, when any one of the at least one chip selection signal CS [n: 0] is activated to control a specific semiconductor chip (for example, any one rank), the second decoder 211_3 Performs a decoding operation on commands, such as RAS, CA, and WE, and generates a decoding result (CMD_S) accordingly.

The third decoder 212_2 of the address decoder unit 212 generates a global control signal GCS for controlling the master area in response to the decoding result of the address ADDR [m: 0] and the output of the first decoder 211_2, Or generates a local control signal LCS for controlling the slave area in response to the decoding result of the address ADDR [m: 0] and the output of the second decoder 211_3.

On the other hand, FIG. 7B shows an example of a control signal generating unit in a case where a plurality of bank groups are defined in one rank. The first decoder 221 receives a chip selection signal CS and commands such as RAS, CA, and WE as a command decoder and performs a decoding operation and provides the decoding result to the address decoder unit 222.

The address decoder unit 222 includes an operation unit 222_1 that receives the bank group address BG [n: 0] and performs a predetermined logical operation (for example, a logical sum (OR) operation) A first buffer 222_2 for temporarily storing a bank address BG [n: 0], a second buffer 222_3 for temporarily storing an address ADDR [m: 0] And a second decoder 222_4 that performs a decoding operation on the address ADDR [m: 0] and generates a global control signal GCS and a local control signal LCS. When any one of the plurality of bank group addresses BG [n: 0] is activated to control any one of the bank groups, the second decoder 222_4 outputs the decoded command, the bank group address BG [n: 0] And a local control signal LCS for controlling the slave area in response to the address ADDR [m: 0]. When two or more bank group addresses BG [n: 0] are activated, the operation unit 222_1 provides the corresponding signals to the second decoder 222_4, and the second decoder 222_4 provides the corresponding signals to the operation unit 222_1. And a global control signal GCS related to control of a plurality of bank groups in response to the decoded command, the bank group address BG [n: 0] and the address ADDR [m: 0]

Various embodiments of the data bus of the semiconductor package according to an embodiment of the present invention, which can be configured as described above, will be described below. Particularly, in disposing the data bus in the semiconductor package, the data bus structure between the semiconductor package and the external memory controller, the number of ranks defined in the semiconductor package, and the number of bank- group, the data bus in the semiconductor package has a variety of structures.

8A and 8B illustrate a data bus structure in a case where one rank and a plurality of bank groups are defined in a semiconductor package. In addition, the master chip in the semiconductor package transmits and receives data through an external memory controller and a bidirectional data bus.

As shown in FIG. 8A, memory banks arranged on different chips and arranged vertically to each other are defined as one bank group. For example, memory banks A to D vertically arranged through a plurality of semiconductor chips are defined as one bank group. Also, the memory banks included in all the semiconductor chips in the semiconductor package are defined as one rank.

The master area shown in FIG. 8A is provided in the master chip to interface with the memory controller, and provides the received command / address and data to the memory banks. Each of the memory banks A to D may be a memory bank included in a slave chip. In this case, the master chip in the semiconductor package may have only a master area. As another example, one or more of the memory banks (e.g., memory bank A) may be a memory bank that is included in the master chip, and the memory bank A to the memory bank B of the slave chip D can be defined as one bank group. In the following drawings, the memory bank A is defined as being a memory bank included in the master chip. For the sake of convenience, the memory bank A and the master area are vertically divided. However, May be provided in the same master chip.

8B shows an example of arranging the data bus in the structure as shown in FIG. 8A. The semiconductor package 310 includes a master chip 311 including a master area and a slave chip 312 stacked on the master chip 311 and including a slave area. Although a greater number of semiconductor chips may be provided in the semiconductor package 310, detailed illustration is omitted for the sake of explanation.

8B, only one rank is defined in the semiconductor package 310, so that the data bus in the master area can follow the data bus structure between the semiconductor package 310 and the memory controller. As shown, the master chip 311 transmits and receives data through the bidirectional data bus with the memory controller, and thus places a bi-directional data bus bi for transferring data in the master area.

On the other hand, since a plurality of bank groups are defined in one rank, a separate data bus is arranged for each bank group. The master area of the master chip 311 and the slave area of the slave chip 312 transmit and receive data bidirectionally through the bidirectional data bus of the master area and the through silicon via (TSV) connected thereto. In general, the through silicon via (TSV) is connected in common to four memory banks per chip on its structure, so that the data from the four memory banks of each chip or from the four memory banks . As shown, a through silicon via (TSV) for transferring data to bank groups includes a through silicon via TSV_BG0 for transferring data corresponding to the first bank group BG0 and a through silicon via TSV_BG0 for transferring data corresponding to the first bank group BG0, (TSV_BG1) for transferring data corresponding to the bit line (BG1).

9A and 9B show a data bus structure in which a plurality of ranks and one bank group are defined in a semiconductor package. As an example, each semiconductor chip is provided with memory banks A to D, and the memory banks A to D of each semiconductor chip are divided into different ranks with memory banks of other chips. Then, the memory banks included in the entire semiconductor chip are defined as one bank group. In addition, the master chip in the semiconductor package transmits and receives data through an external memory controller and a bidirectional data bus.

FIG. 9B shows an example of arranging the data bus in the structure as shown in FIG. 9A. The semiconductor package 320 includes a master chip 321 including a master region and a slave chip 322 stacked on the slave region and including a slave region and the master chip 321 is defined as a first rank Rnk 0 And the slave chip 322 is defined as a second rank Rnk 1.

In Fig. 9B, since a plurality of ranks are defined in the semiconductor package 320, the unidirectional data bus uni is arranged in the data bus in the master area. As shown in Fig. 9B, input data (for example, write data) and output data (for example, read data) in the master area have different transmission paths. On the other hand, a through silicon via (TSV) for connection between the master area and the slave area carries data on memory banks corresponding to a plurality of ranks. Accordingly, the through silicon via (TSV) also needs to transmit data unidirectionally. As shown in the figure, the through silicon via (TSV_RD) for lead data and the through silicon via (TSV_WD) for write data can be formed. The slave area transmits and receives data to and from the master area via a through silicon via (TSV), and a bidirectional data bus may be disposed in the slave area.

10A and 10B illustrate a data bus structure in which a plurality of ranks and a plurality of bank groups are defined in a semiconductor package and a master chip transmits and receives data through an external memory controller and a bidirectional data bus . For example, memory banks arranged on different chips and vertically arranged are defined as a first bank group BG0, and memory banks arranged adjacent to and vertically arranged are defined as a second bank group BG1. Also, the memory banks of one first bank group BG0 and one second bank group BG1 are defined as one rank. A first rank Rnk 0 and a second rank Rnk 1 are shown that each include one first bank group BG0 and one second bank group BG1.

FIG. 10B shows an example of arranging the data bus in the structure as shown in FIG. 10A. Although not shown in the cross-sectional view of FIG. 10A, four memory banks connectable to one through silicon via (TSV) are defined as one rank, two memory banks are defined as a first bank group BG0 , And the other two memory banks are defined as the second bank group BG1.

First, since the data bus in the master area of the semiconductor package 330 is for transmitting and receiving data related to a plurality of ranks, the data bus in the master area uses a unidirectional data bus uni as shown in the figure. On the other hand, since the memory banks included in the first bank group BG0 and the second bank group BG1 are defined by the same rank (for example, the first rank Rnk 0), the connection between the master area and the slave area Through-silicon vias (TSVs) formed for the same rank deliver data corresponding to the same rank. As a result, the through silicon via (TSV) is formed in a structure that transmits data in both directions.

Also, as described above, it is preferable that different data buses are arranged corresponding to different bank groups. Accordingly, in forming the through silicon via (TSV), the through silicon via (TSV_BG0) for transmitting and receiving data corresponding to the first bank group BG0 and the data corresponding to the second bank group BG1 And the through silicon vias TSV_BG1 for transmission and reception are separated from each other. Thus, the first bank group BG0 and the second bank group BG1 transmit and receive data to and from the master region via different through silicon vias TSV, and each of the different through silicon vias TSV Transmits in both directions.

10A and 10B, a plurality of ranks and a plurality of bank groups are defined in the semiconductor package, and the master chip transmits data through an external memory controller and a bidirectional data bus The data bus structure in the case of transmitting and receiving is shown. However, even when a plurality of ranks and a plurality of bank groups are defined in the semiconductor package and the master chip transmits and receives data in one direction with the external memory controller, May have the same structure as shown in Fig. That is, when the master chip transmits and receives data in one direction with the external memory controller, it is preferable that the unidirectional data bus is disposed in the data bus in the master chip. However, regardless of the structure of the external data bus, rank is defined, a unidirectional data bus is used in the master chip. Thus, even when a plurality of ranks and a plurality of bank groups are defined in the semiconductor package and the master chip transmits and receives data in one direction with an external memory controller, And may have the same data bus structure as shown.

11A and 11B show a case where a rank and a plurality of bank groups are defined in a semiconductor package and a master chip has a data bus structure for transmitting and receiving data through an external memory controller and a unidirectional data bus . Also, as shown in FIG. 11A, memory banks arranged in a plurality of semiconductor chips and vertically aligned with each other are defined as one bank group. As an example, a first bank group BG0 and a second bank group BG1 are shown. Also, all semiconductor chips in a semiconductor package are defined with the same rank.

11B shows an example of arranging the data bus in the structure as shown in FIG. 11A. As shown, only one rank is defined in the semiconductor package, so that the data bus in the master region may follow the data bus structure between the semiconductor package 340 and the memory controller. Since the master chip and the memory controller transmit and receive data through the unidirectional data bus, the data bus in the master area can use the unidirectional data bus (uni).

On the other hand, since only one rank is defined in the semiconductor package, a through silicon via (TSV) for connecting the master area and the slave area is formed to transmit data in both directions. A data bus is separately arranged for each of a plurality of bank groups. For example, data buses for transferring data for the first bank group BG0 and data for the second bank group BG1 So that the data buses to be transmitted are distinguished. Since the memory banks connectable to the respective through silicon vias TSV are included in the same bank group, the bidirectional through silicon via TSV_BG0 corresponding to the first bank group BG0 and the second bank group BG1 Directional through silicon vias TSV_BG1 corresponding to the via holes TSV_BG1 can be formed.

12A and 12B show another example of the data bus structure when one rank and a plurality of bank groups are defined in the semiconductor package. The above conditions are the same as those in FIGS. 8A and 8B, but the bank grouping method in FIGS. 12A and 12B and the bank grouping method in FIGS. 8A and 8B are different from each other.

As shown in FIG. 12A, on the vertical section of the semiconductor package, memory banks included in a plurality of semiconductor chips to be stacked are defined as the same bank group. However, as shown in semiconductor package 410 of FIG. 12B, any two of the four memory banks, which are connectable to the through silicon vias (TSV), and the other two memory banks are in different bank groups, . As an example, a case where two upper memory banks of the four memory banks are defined as a first bank group BG0 and two lower memory banks are defined as a second bank group BG1.

According to the above structure, the through silicon vias TSV_BG0 for transferring the data corresponding to the first bank group BG0 and the through silicon vias TSV_BG1 for transferring the data corresponding to the second bank group BG1, Should be formed separately from each other.

As described above, in the above-described structure, since only one rank is defined in the semiconductor package 410, the data bus disposed in the master region uses the bi-directional data bus bi. Also, as only one rank is defined, each through silicon via (TSV) is formed to transmit data in both directions.

According to the structure of the data bus shown in FIG. 12B, it can be seen that a larger number of through silicon vias (TSV) and a data bus are required than the structure of the data bus shown in FIG. 8B. That is, the bank grouping scheme according to the scheme shown in FIG. 8B is more efficient than the bank grouping scheme shown in FIG. 12B. Accordingly, it is possible to more effectively arrange the data bus in the semiconductor package by defining memory banks having a structure that can be connected to any one of the through silicon vias (TSV) as one bank group. Similarly, when memory banks arranged perpendicularly to each other along the direction of the through silicon vias (TSV) are defined with the same rank, a bi-directional data bus structure instead of a uni-directional (uni) , It is preferable to define a rank and a bank group as described above.

13A and 13B show another example of the data bus structure when a plurality of ranks and one bank group are defined in the semiconductor package. The above conditions are the same as those in Figs. 9A and 9B, but the rank defining method in Figs. 13A and 13B and the rank defining method in Figs. 9A and 9B are different.

 In FIGS. 9A and 9B, unlike the case where the semiconductor chips are defined at different ranks, the memory banks arranged in a plurality of semiconductor chips and arranged perpendicularly to each other are defined as one rank in FIG. 13A. That is, in defining a plurality of ranks in the semiconductor package, memory banks arranged in a plurality of semiconductor chips and arranged perpendicularly to each other can be defined as one rank. Memory banks (e.g., four memory banks) vertically disposed and connectable to a single through silicon via (TSV) may be defined with the same rank.

As shown in FIG. 13B, the semiconductor package 420 uses a unidirectional data bus (uni) as a data bus in the master area as a plurality of ranks are defined. Also, since the memory banks connectable to the through silicon vias (TSV) are defined by the same bank group, the through silicon vias (TSV) can be shared by four memory banks. Also, since the four memory banks connected to the through silicon vias (TSV) are defined with the same rank as each other, the through silicon vias (TSV) are formed to transfer data in both directions.

Accordingly, even though a plurality of ranks are defined in one semiconductor package 420, the through silicon vias TSV can be arranged to transfer data in both directions. That is, it is the same as in FIGS. 9A and 9B that a plurality of ranks are defined in one semiconductor package 420, but the semiconductor package 420 in FIGS. 13A and 13B has a through silicon via (TSV) is used, which further reduces the use of through silicon vias (TSV) compared to the case of Figures 9A, B, indicating that the data bus structure in the semiconductor package 420 can be made more efficient.

As described above, a semiconductor package having a plurality of stacked chips according to an embodiment of the present invention includes memory banks that are controlled by one master chip and are defined with different ranks. Also, a plurality of bank groups may be defined in any one of the ranks. In defining the rank and bank groups, it is possible to define more various types of rank and bank groups. 8 to 13 show only a partial implementation of the present invention. The semiconductor package of the present invention can be implemented in various ways based on the unidirectional / bidirectional data bus and the data bus separation for each bank group disclosed in the present invention have.

14 is a block diagram showing a data transfer path of a semiconductor package according to an embodiment of the present invention. In general, a semiconductor chip is provided with at least one first pad for transmitting and receiving data to both sides of the semiconductor chip, and at least one second pad for receiving a command inside the first pads is disposed according to the position of the pad An ODIC (Outer Data Inner Command) type semiconductor chip, at least one first pad for transmitting and receiving data on one side of the semiconductor chip, and one or more second pads for receiving a command on the other side are disposed. Command) type semiconductor chips.

According to an embodiment of the present invention, when a master chip including a master area in a semiconductor package transmits and receives data to and from a plurality of slave chips, the influence of PVT changes for each semiconductor chip is reduced. That is, when data is transferred to each of the slave chips via the master area of the master chip, or when data read from each slave chip is supplied to the master chip, data transmission Time and so on.

As shown in FIG. 14A, it is preferable that a slave chip included in the semiconductor package 510 according to an embodiment of the present invention is applied with a semiconductor chip of ODIC (Outer Data Inner Command) type. Accordingly, the pads for transmitting data are disposed on both sides of the semiconductor chip, and the transmission distance between the memory bank and the pads is shortened. The data read from the memory bank is transferred to the master area of the master chip via the data pad and through silicon via (TSV). In this case, the transfer path of the read data includes the transfer path (a) in the slave chip and the transfer path (b) in the master chip.

Preferably, the transmission path a in the slave chip has a relatively shorter distance than the transmission path b in the master chip. To this end, at least one slave chip is formed with a through silicon via (TSV) close to where the data pad is located. Accordingly, when the data read from each slave chip is transferred to the master chip, the data path through each slave chip is shorter than the data path in the master chip, The effect can be reduced. The semiconductor package 520 shown in FIG. 14 (b) is a semiconductor package in which a data pad is disposed on one side of a semiconductor chip and corresponding thru silicon vias (TSV) are formed, So that the length of the path through it becomes longer. Accordingly, when data is transferred from each slave chip to the master chip, the difference in PVT characteristics of each slave chip greatly affects the data.

This is also applied to the case of recording data in the slave chip. The write data supplied from the external memory controller (not shown) to the master chip is provided to each slave chip via a predetermined data transfer path. In this case, the data is transferred by a relatively long path through the data bus in the master chip, and the data transferred in the master chip is provided to the slave chip through the through silicon via (TSV) and the data pad of the slave chip . The data provided to each slave chip is transferred to the memory bank through a path having a relatively short length.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

1A and 1B are block diagrams showing a semiconductor memory module according to an embodiment of the present invention.

2A and 2B are block diagrams showing a semiconductor memory module according to another embodiment of the present invention.

3A and 3B are waveform diagrams showing an example of data collision when a plurality of ranks or a plurality of bank groups are applied.

4A and 4B are block diagrams showing a configuration of a semiconductor chip included in a semiconductor package according to an embodiment of the present invention.

5 is a circuit diagram schematically illustrating a data path between semiconductor chips included in a semiconductor package according to an embodiment of the present invention.

6A and 6B are block diagrams illustrating interfaces between a master area and a slave area.

7A and 7B are block diagrams of a control signal generator for generating control signals for controlling the master area and the slave area.

Figures 8a, b, 13a, and b illustrate various embodiments of a data bus structure formed in a semiconductor package in accordance with an embodiment of the present invention.

14 is a block diagram showing a data transfer path of a semiconductor package according to an embodiment of the present invention.

Claims (28)

A semiconductor package comprising a plurality of stacked chips, At least one master chip communicating with an external memory controller; And At least one slave chip stacked on the at least one master chip and communicating with the master chip through one or more conductive means, The plurality of stacked chips includes a plurality of memory banks, wherein the plurality of memory banks communicate with the same master chip and include one or more first memory banks and one or more second memory banks, which are divided into different ranks And the semiconductor package. The method according to claim 1, Wherein the at least one master chip and the at least one slave chip are divided into different ranks. The method according to claim 1, Wherein the at least one master chip has a master area that operates in response to a global control signal and interfaces with the memory controller, Wherein the at least one slave chip comprises a slave region operating in response to a local control signal and performing an interface with the master chip. 4. The method of claim 3, wherein the at least one master chip comprises: A first decoder for receiving a first command related to the master area control and decoding the first command, a second decoder for receiving and decoding a second command related to the slave area control, and a second decoder A command decoder for receiving a selection signal and performing a logical operation and providing the operation result to the first decoder; And Receiving an output from the first and second decoders and an externally provided address and generating a global control signal provided to the master region based on a combination of the output of the first decoder and the address, And an address decoder for generating a local control signal provided to the slave area based on a combination of the output of the decoder and the address. The method according to claim 1, Wherein each of the at least one master chip has a master area for transmitting and receiving data to and from the memory controller, and a unidirectional data bus is disposed in the master area. The apparatus of claim 1, wherein the at least one conductive means comprises: Wherein said at least one master chip and / or said at least one slave chip is a via. delete delete delete The method according to claim 1, Wherein at least two memory banks provided in different chips of the plurality of memory banks and arranged vertically to each other are defined as one rank. At least one master chip including a master area for communicating with an external memory controller; And At least one slave chip stacked on the master chip and including a slave region communicating with the master chip through one or more conductive means, Two or more bank groups are defined for the master chip and / or a plurality of memory banks provided in the at least one slave chip, each bank group includes at least one memory bank, and data for transmitting and receiving data And the bus is arranged to be divided corresponding to each of the bank groups. 12. The method of claim 11, When the master chip transmits and receives data to and from the memory controller via a bidirectional data bus, Wherein all of the chips in the semiconductor package are defined as one rank, the master area has bidirectional data buses for bidirectionally transferring data therein, Wherein when the chips in the semiconductor package are defined as a plurality of ranks, the master region has a unidirectional data bus for unidirectionally transmitting data therein. delete A master chip including an input circuit and an output circuit for communicating with an external memory controller; And At least one slave chip stacked on the master chip and communicating with the master chip via a via, Wherein a data transmission / reception distance during data transmission / reception between the master chip and the slave chip is determined by a first path between a memory bank and a via in the slave chip and between the via in the master chip and the input circuit, Or output circuit, wherein the first path has a relatively short distance relative to the second path. delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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