KR102017314B1 - Semiconductor memory device and method of driving the same - Google Patents

Abstract

A semiconductor memory device having a stacked structure, comprising: a semiconductor memory device in which a plurality of semiconductor chips are stacked, comprising: a first pad group electrically connected to an external device to input and output first data, and electrically connected to the external device; A first semiconductor chip having a second pad group for inputting and outputting second data; And a second semiconductor chip electrically connected to the first semiconductor chip and vertically penetrated with at least one chip through via for interfacing the first and second data, wherein the second semiconductor chip stores the first data. And a first bank group having at least one first and second bank for providing; A second bank group having at least one third and fourth banks for storing and providing second data; And a data path selector for electrically connecting the chip through via to any one of the first to fourth banks in response to the data width option signal, the address signal, and the bank address signal.

Description

Semiconductor memory device and driving method thereof {SEMICONDUCTOR MEMORY DEVICE AND METHOD OF DRIVING THE SAME}

The present invention relates to a semiconductor design technology, and more particularly, to a semiconductor memory device having a laminated structure and a driving method thereof.

In general, packaging technology has been continually evolved to meet the demand for miniaturization and mounting reliability. Recently, as the miniaturization of electric / electronic products and high performance are required, various technologies for stack packages have been developed.

In the semiconductor industry, "stacking" refers to stacking at least two or more semiconductor chips or packages vertically. According to the stacked package, for example, in the case of a semiconductor memory device such as DRAM (DRAM), a semiconductor integration process It is possible to implement products with more than twice the memory capacity that can be implemented in. In addition, since the stack package has advantages in terms of increasing memory capacity and efficiency of mounting density and footprint area, research and development of the stack package is accelerated.

Stacked packages can be manufactured by stacking individual semiconductor chips, and then stacking stacked semiconductor chips at once, and stacking the packaged individual semiconductor chips. The individual semiconductor chips of the stacked package are made of metal wires or through-chips. Electrically connected through the back. In particular, a stack package using chip through vias is a structure in which chip through vias are formed in a semiconductor chip so that physical and electrical connections are made between semiconductor chips vertically by the chip through vias.

Meanwhile, a semiconductor chip connected to an external device to exchange various signals, power, and data among the semiconductor chips included in the stack package is called a master chip, and a semiconductor chip that stores and provides data under the control of the master chip is called a slave chip. do. In particular, in order to minimize the area of the slave chip, a technology has been developed to include only the core area.

1 shows an internal configuration diagram of a slave chip.

Referring to FIG. 1, a slave chip is configured to input and output data between a plurality of banks BANK0 to BANK7 for storing and providing data, and a plurality of banks BANK0 to BANK7 and a master chip (not shown). It includes a plurality of first and second global input and output lines (GIO1, GIO2).

Here, the plurality of banks BANK0 to BANK7 are divided corresponding to the first and second data pad groups UDQ and LDQ, respectively, and some of the banks BANK0, BANK1, BANK4, and BANK5 are divided into a plurality of first globals. The input / output line GIO1 is shared and some banks BANK2, BANK3, BANK6, and BANK7 share a plurality of second global input / output lines GIO2.

For example, if the slave chip has a capacity of 1 G Bit and 8 banks are provided, a capacity of 128 M Bits per bank-64 M Bits corresponding to the first and second data pad groups UDQ and LDQ per half bank Since the memory cell corresponds to 128M bits per bank, 128 global input / output lines GIO1 and GIO2 are provided to correspond to the memory cells.

Meanwhile, in the related art, a technique of reducing the number of global input / output lines in order to reduce the area of the slave chip illustrated in FIG. 1 has been disclosed.

2 illustrates an internal configuration of a slave chip with a minimized area.

Referring to FIG. 2, it can be seen that a slave chip having a minimized area is divided into half banks corresponding to the first and second data pad groups UDQ and LDQ, respectively. For example, the first to eighth half banks BANK0 to BANK7 corresponding to the first data pad group UDQ form one bank group, and the first to eighth half corresponding to the second data pad group LDQ. The banks BANK0 'through BANK7' form another bank group. In this configuration, 64 global input / output lines GIO11 and GIO12 may be provided in correspondence with the bank groups BANK0 to BANK7 and BANK0 'to BANK7', respectively. The advantage is that you save as much as half the line.

On the other hand, although not shown in the drawing, 128 chip through vias (for example, through silicon vias (TSVs)) are provided corresponding to a total of 128 global input / output lines GIO11 and GIO12. The chip through via vertically penetrates the slave chip, and is electrically connected to the master chip forming a stacked structure together with the slave chip, and is a medium for interfacing data between the master chip and the global input / output lines GIO11 and GIO12.

However, the slave chip having the above configuration has a limitation in reducing the area, and also has a structure in which the global input / output lines GIO11 and GIO12 are shared per bank group BANK0 to BANK7 and BANK0 'to BANK7'. Therefore, there is a problem in that the line loading of the global input / output lines GIO11 and GIO12 is increased.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having a reduced area by reducing the number of chip through vias and a driving method thereof.

In addition, another object of the present invention is to provide a semiconductor memory device and a method of driving the same, which reduces the number of chip through vias and minimizes line loading of global input / output lines.

According to an aspect of the present invention, the present invention provides a semiconductor memory device in which first and second semiconductor chips are stacked, comprising: a first pad group electrically connected to an external device to input and output first data, and the external device; The first semiconductor chip electrically connected to the device and having a second pad group for inputting and outputting second data; And the second semiconductor chip electrically connected to the first semiconductor chip and vertically penetrating at least one chip through via for interfacing the first and second data, wherein the second semiconductor chip comprises: A first bank group having at least one first and second bank for storing and providing first data; A first input / output line connected between the first bank and the chip through via; A second input / output line connected between the second bank and the chip through via; A second bank group having at least one third and fourth banks for storing and providing the second data; A third input / output line connected between the third bank and the chip through via; A fourth input / output line connected between the fourth bank and the chip through via; And electrically connecting the first and third input and output lines and the chip through via in response to a bank address signal, and electrically separating the second and fourth input and output lines and the chip through via. Electrically connecting an input / output line and the chip through via, electrically separating the first and third input / output lines from the chip through via, and in response to a data width option signal and an address signal. Electrically connects any one of the chip through vias and electrically separates the other of the first and third input / output lines from the chip through via, or connects any of the second and fourth input / output lines with the chip through via. A data path selector for electrically connecting and electrically separating the remaining of the second and fourth input / output lines from the chip through via. It may include

According to another aspect of the present invention, the present invention includes the steps of entering a specific data width option mode in which data is input and output through only one of the first and second pad groups; The first and third banks and the chip through via are electrically connected to each other according to the bank address signal, and the second and fourth banks and the chip through via are electrically separated from each other. Electrically connecting one of a third banks to the chip through vias and electrically separating the other of the first and third banks from the chip through vias; And transmitting data between any one of the first and third banks and the chip through via.

Since the number of chip through vias for electrical connection with other stacked semiconductor chips can be reduced, the area can be minimized and the process time and cost can be saved.

In addition, by selectively connecting the global I / O lines shared per bank group corresponding to the activated bank it is possible to minimize the line loading of the global I / O lines. Therefore, the transition time of the data can be reduced, thereby contributing to the performance improvement of the semiconductor memory device.

1 is a diagram illustrating an internal configuration of a slave chip included in a semiconductor memory device according to an exemplary embodiment.
2 is a diagram illustrating an internal configuration of a slave chip included in a semiconductor memory device according to another example.
3 is a side view conceptually illustrating a semiconductor memory device in accordance with an embodiment of the present invention.
FIG. 4 is a diagram illustrating an internal configuration of the slave chip shown in FIG. 3.
FIG. 5 is a diagram illustrating an internal configuration of the slave chip illustrated in FIG. 4 in more detail.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

3 is a side view of a semiconductor memory device according to an exemplary embodiment of the present invention, FIG. 4 is a diagram illustrating an internal configuration of the first slave chip illustrated in FIG. 3, and FIG. 5 is illustrated in FIG. 4. 1 is an internal configuration diagram illustrating the slave chip in more detail.

Referring to FIG. 3, the semiconductor memory device 100 is sequentially stacked on the master chip 110 and the master chip 110 to exchange various signals, power, data, and the like with an external device (not shown). First to fourth slave chips 120A, 120B, 120C and 120D and first to fourth slave chips 120A, 120B, 120C and 120D for storing and providing data under the control of the master chip 110. A plurality of first through fourth chip through vias 130A, 130B, and 130C for vertically penetrating the data and interfacing data between the master chip 110 and the first through fourth slave chips 120A, 120B, 120C, and 120D. 130D).

Here, the master chip 110 includes a plurality of data pads (not shown) for exchanging data with an external device. Hereinafter, a description will be made of 16 data pads as an example. First to eighth data pads are referred to as a first pad group UDQ, and ninth to sixteenth data pads are referred to as a second pad group LDQ.

In addition, the first to fourth slave chips 120A, 120B, 120C, and 120D have only a minimum configuration capable of storing and providing data under the control of the master chip 110. Here, since all of the first to fourth slave chips 120A, 120B, 120C, and 120D have the same configuration, only the first slave chip 120A will be described below. Referring to FIG. 4, the first slave chip 120A may include first and second half bank groups BANK0 to BANK3 to store and provide first data input and output through the first pad group UDQ. Third and fourth half bank groups BANK0 'to BANK3' for storing and providing the first bank groups 121A and 123A having the BANK7 and the second data input / output through the second pad group LDQ. First to fourth banks in response to the second bank group 125A and 127A having BANK4 'to BANK7', the data width option signal X8, the address signal A14, and the bank address signal BA2. Data path selection for electrically connecting any one of the half bank groups BANK0 to BANK3 (BANK4 to BANK7) (BANK0 'to BANK3') (BANK4 'to BANK7') and the plurality of first chip through vias 130A. A plurality of first global I / Os for actually connecting the portion 122A, the first and second half bank groups BANK0 to BANK7, and the plurality of first chip through vias 130A. A plurality of second global input / output lines GIO22 for actually connecting the GIO21, the third and fourth half bank groups BANK0 'to BANK7', and the plurality of first chip through vias 130A. .

Here, the data path selection unit 122A will be described in more detail with reference to FIG. 5. 5 illustrates a data path selector 122A corresponding to one chip through via 130A and one first and second global input / output lines GIO21 and GIO22 for convenience of description. For example, the data path selector 122A corresponding to 64 chip through vias 130A and 64 first and second global I / O lines GIO21 and GIO22 corresponding to the density of each bank, which is 64M Bit, is used. ) Should be provided.

Referring to FIG. 5, the data path selector 129A may include first and third half bank groups 121A and 125A in response to a data width option signal X8, an address signal A14, and a bank address signal BA2. A second multiplexer 129A_1 for electrically connecting any one of the chip through vias 130A, the second in response to a data width option signal X8, an address signal A14, and a bank address signal BA2. And a second multiplexer 129A_3 for electrically connecting any one of the fourth half bank groups 123A and 127A to the chip through via 130A.

The first multiplexer 129A_1 includes a first bank path selector 129A_11 and a data width option for selectively connecting the first connection node CN1 and the chip through via 130A in response to the bank address BA2. A first group path selector 129A_13 and a data width option signal for selectively connecting the first connection node CN1 and the first half bank group 121A in response to the signal X8 and the address signal A14; A second group path selection for selectively connecting the first connection node CN1 and the third half bank group 125A in response to an address signal inverted with X8, which is an inverted signal of the address signal A14; Section 129A_15.

The second multiplexer 129A_3 may include a second bank path selector 129A_31 and a data width option for selectively connecting the second connection node CN2 and the chip through via 130A in response to the bank address BA2. A third group path selector 129A_31 for selectively connecting the second connection node CN2 and the second half bank group 123A in response to the signal X8 and the address signal A14, and a data width option signal A fourth group path selection for selectively connecting the second connection node CN2 and the fourth half bank group 127A in response to the address signal inverted with X8, which is an inverted signal of the address signal A14; Section 129A_35.

Meanwhile, the plurality of chip through vias 130A include through silicon vias (TSVs).

Hereinafter, a driving method of the semiconductor memory device 100 according to the embodiment of the present invention having the above configuration will be described. However, in the embodiment of the present invention, a write operation according to the X8 mode-input / output data through eight data pads (first pad group UDQ or second pad group LDQ) is described as an example. Only the first slave chip 120A during the write operation will be described.

When data is input through the first pad group UDQ (not shown) provided in the master chip, the master chip transfers data to the first slave chip 120A through the plurality of chip through vias 130A.

In this case, only one of the first and second multiplexers 129A_1 and 129A_3 is enabled in the first slave chip 120A, and the data transmitted through the chip through via 130A may be the first multiplexer 129A_1 or the like. The first multiplexer 129A_3 is transferred to any one of the first to fourth half bank groups 121A, 123A, 125A, and 127A through the second multiplexer 129A_3. In other words, in the X8 mode, the data path connected to the chip through via 130A is determined to which bank group 121A, 123A, 125A, 127A is connected according to a specific address signal A14, and the bank address signal BA2. Which half bank groups 121A, 123A, 125A, and 127A are connected to are determined according to this. For example, when data is input through the first pad group UDQ and any one of the banks BANK0, BANK1, BANK2, and BANK3 belonging to the first half bank group 121A is activated, a bank low-level bank address signal. The first multiplexer 129A_1 is enabled according to BA2 and the first global input / output line GIO21 and the chip through via 130A through the first multiplexer 129A_1 according to the logic high level address signal A14. ) Is connected, and the data transmitted through the chip through via 130A is finally transferred to the first half bank group 121A. At this time, the first global input / output line GIO21 connected to the second half bank group 123A is electrically separated by the disabled second multiplexer 129A_3.

According to the exemplary embodiment of the present invention, data transmitted to different bank groups can be transmitted through one chip through via, so that the number of chip through vias can be reduced while other data is transferred to a specific half bank group. By electrically separating the paths, there is an advantage in reducing the line loading of the global I / O lines.

Although the technical spirit of the present invention has been described in detail with reference to the above embodiments, it should be noted that the above-described embodiments are for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible with various substitutions, modifications, and changes within the scope of the technical idea of the present invention.

100: semiconductor memory device 110: master chip
120A ~ 120D: Slave Chip 121A and 123A: First Bank Group
121A: First Half Bank Group 123A: Second Half Bank Group
125A and 127A: second bank group 125A: third half bank group
127A: First half bank group 129A: Data path selector
129A_1: first multiplexer 129A_11: first bank path selector
129A_13: first group path selector 129A_15: second group path selector
129A_3: second multiplexer 129A_31: second bank path selector
129A_33: third group path selector 129A_35: fourth group path selector

Claims (9)

A semiconductor memory device in which first and second semiconductor chips are stacked,
The first semiconductor chip having a first pad group electrically connected to an external device to input and output first data, and a second pad group electrically connected to the external device to input and output second data; And
The second semiconductor chip electrically connected to the first semiconductor chip and vertically penetrated with at least one chip through via for interfacing the first and second data,
The second semiconductor chip,
A first bank group having at least one first and second bank for storing and providing the first data;
A first input / output line connected between the first bank and the chip through via;
A second input / output line connected between the second bank and the chip through via;
A second bank group having at least one third and fourth banks for storing and providing the second data;
A third input / output line connected between the third bank and the chip through via;
A fourth input / output line connected between the fourth bank and the chip through via; And
The first and third input and output lines and the chip through via are electrically connected in response to a bank address signal, and the second and fourth input and output lines and the chip through via are electrically separated from each other or the second and fourth input and output vias are electrically connected. An electrical connection between a line and the chip through via, electrically disconnecting the first and third input / output lines and the chip through via, and either of the first and third input / output lines in response to a data width option signal and an address signal. Electrically connect one and the chip through via to electrically isolate the other of the first and third input / output lines from the chip through via, or electrically connect either one of the second and fourth input / output lines to the chip through via. And a data path selector for electrically separating the remaining of the second and fourth input and output lines and the chip through A semiconductor memory device comprising.
Claim 2 has been abandoned upon payment of a set-up fee. The method of claim 1,
The data path selection unit,
In response to the data width option signal, the address signal, and the bank address signal, one of the first and third input / output lines and the chip through via are electrically connected to each other, and the other of the first and third input / output lines and the A first multiplexing unit for electrically separating chip through vias; And
In response to the data width option signal, the address signal, and the bank address signal, one of the second and fourth input / output lines and the chip through via are electrically connected to each other, and the other of the second and fourth input / output lines and the And a second multiplexing unit for electrically separating chip through vias.
Claim 3 has been abandoned upon payment of a set-up fee. The method of claim 2,
The first multiplexer,
A first bank path selector for selectively connecting a first connection node and the chip through via in response to the bank address;
A first group path selector for selectively connecting the first connection node and the first input / output line in response to the data width option signal and the address signal; And
And a second group path selector for selectively connecting the first connection node and the third input / output line in response to the data width option signal and an inverted address signal, the inverted signal of the address signal. Device.
Claim 4 has been abandoned upon payment of a setup registration fee. The method of claim 2,
The second multiplexer,
A second bank path selector for selectively connecting a second connection node and the chip through via in response to the bank address;
A third group path selector for selectively connecting the second connection node and the second input / output line in response to the data width option signal and the address signal; And
And a fourth group path selector for selectively connecting the second connection node and the fourth input / output line in response to the data width option signal and an inverted address signal, the inverted signal of the address signal. Device.
Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1,
And the first to fourth input / output lines each include a global input / output line.
Claim 6 has been abandoned upon payment of a setup registration fee. The method of claim 1,
The first to fourth input / output lines may be provided to correspond to the densities of the first to fourth banks, respectively.
Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1,
The chip through via includes a through silicon via (TSV).
A method of driving a semiconductor memory device according to any one of claims 1 to 7,
Entering a specific data width option mode in which data is inputted and outputted through only one of the first and second pad groups according to the data width option signal;
The first and third banks and the chip through via are electrically connected to each other according to the bank address signal, and the second and fourth banks and the chip through via are electrically separated from each other. Electrically connecting one of a third banks to the chip through vias and electrically separating the other of the first and third banks from the chip through vias; And
Transferring data between any one of the first and third banks and the chip through via
Method of driving a semiconductor memory device comprising a.
Claim 9 was abandoned upon payment of a set-up fee. The method of claim 8,
The first and third banks and the chip through via are electrically separated according to the bank address signal, and the second and fourth banks and the chip through via are electrically connected to each other. Any one of a fourth bank and the chip through via is electrically connected, and the other of the second and fourth banks is electrically separated from the chip through via; And
And transmitting data between any one of the second and fourth banks and the chip through via.

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