KR20180100088A - Semiconductor memory device and method of driving the same - Google Patents

Abstract

The present invention relates to a semiconductor memory device having a stacked structure. The semiconductor memory device, in which a plurality of semiconductor chips are stacked, comprises a first semiconductor chip including a first pad group electrically connected to an external device to input and output first data and a second pad group electrically connected to an external device to input and output second data; and a second semiconductor chip electrically connected to the first semiconductor chip and having at least one chip through via vertically bored to interface the first and second data. The second semiconductor chip comprises a first bank group including at least one first bank and at least one second bank for storing and providing first data; a second bank group including at least one third bank and at least one fourth bank for storing and providing second data; and a data path selection unit for electrically connecting one of the first to fourth banks and the chip through via in response to a data width option signal, an address signal, and a bank address signal. By reducing the number of chip through vias, an area is minimized. Also, line loading of a global input and output line is minimized.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor design technology, and more particularly, to a semiconductor memory device having a stacked structure and a driving method thereof.

In general, packaging techniques have been continually developed to meet the demands for miniaturization and mounting reliability. In recent years, various technologies for a stack package have been developed as demand for miniaturization of electric / electronic products and high performance are required.

In the semiconductor industry, "lamination" means stacking at least two or more semiconductor chips or packages vertically. According to such a lamination package, in the case of a semiconductor memory device such as DRAM (Dynamic Random Access Memory) It is possible to implement a product having a memory capacity twice as much as a memory capacity that can be implemented in the memory. In addition, since the stacked package has advantages in terms of the mounting density and the efficiency of use of the mounting area as well as the memory capacity, the research and development of the stacked package is accelerated.

The stacked package can be manufactured by a method of stacking individual semiconductor chips and then stacking the stacked semiconductor chips at once, and a method of stacking individual semiconductor chips packaged, and the individual semiconductor chips of the stacked package may be formed by metal wires or chip- And the like. Particularly, a laminate package using chip through vias is a structure in which chip through vias are formed in a semiconductor chip so that physical and electrical connections are made between semiconductor chips vertically by chip through vias.

On the other hand, among the semiconductor chips included in the stacked package, a semiconductor chip connected to an external device to exchange various signals, power, and data is called a master chip, and a semiconductor chip storing and providing data under the control of the master chip is called a slave chip do. In particular, in order to minimize the area of the slave chip, a technique for including only the core region is being developed.

1 shows an internal configuration of a slave chip.

1, a slave chip includes a plurality of banks BANK0 to BANK7 for storing and providing data and a plurality of banks BANK0 to BANK7 for inputting / outputting data between the banks BANK0 to BANK7 and a master chip And a plurality of first and second global input / output lines (GIO1, GIO2).

Here, the plurality of banks BANK0 to BANK7 are divided into the first and second data pad groups UDQ and LDQ, respectively, and some of the banks BANK0, BANK1, BANK4, and BANK5 are divided into a plurality of first global Output lines GIO1 and some of the banks BANK2, BANK3, BANK6, and BANK7 share a plurality of second global input / output lines GIO2.

For example, if the density of the slave chip is 1 Gbit and eight banks are provided, a capacity of 64 Mbits corresponding to the first and second data pad groups UDQ and LDQ per capacity-half bank of 128 Mbits per bank The memory cell corresponding to 128 Mbits per bank is provided and 128 global input / output lines (GIO1, GIO2) are provided corresponding to the memory cell.

Meanwhile, in the related art, a technique of reducing the number of global input / output lines in order to reduce the area of the slave chip shown in FIG. 1 has been disclosed.

FIG. 2 shows an internal structure of a slave chip having an area minimized.

Referring to FIG. 2, it can be seen that the slave chip having the minimum area is divided into half banks corresponding to the first and second data pad groups UDQ and LDQ, respectively, as compared with FIG. For example, the first through eighth half banks BANK0 through BANK7 corresponding to the first data pad group UDQ form one bank group, and the first through eighth half banks BANK0 through BANK7 corresponding to the second data pad group LDQ, The banks BANK0 'to BANK7' form another bank group. With this configuration, 64 global input / output lines (GIO11, GIO12) can be provided corresponding to the bank groups (BANK0 to BANK7) (BANK0 'to BANK7'), There is an advantage of saving as much as half the area of the line.

Although not shown in the drawing, 128 chip through vias (for example, through silicon vias (TSV)) are provided corresponding to a total of 128 global input / output lines GIO11 and GIO12. The chip through vias are provided to vertically penetrate the slave chip, and are a medium for interfacing data between the master chip and the global input / output lines (GIO11, GIO12) by being electrically connected to the master chip forming the stacked structure together with the slave chip.

However, the structure of the slave chip having the above configuration has a limitation in reducing the area and shares the global input / output line (GIO11) (GIO12) per bank group (BANK0 ~ BANK7) Therefore, there is a problem that line loading of the global input / output lines (GIO11, GIO12) becomes large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor memory device and a method of driving the semiconductor memory device in which the number of chip through vias is reduced to minimize the area.

It is another object of the present invention to provide a semiconductor memory device and a method of driving the semiconductor memory device in which the number of chip through vias is reduced to minimize the area and the line loading of the global input / output lines is minimized.

According to an aspect of the present invention, there is provided a semiconductor memory device in which first and second semiconductor chips are stacked, comprising: a first pad group electrically connected to an external device for inputting / outputting first data; A first semiconductor chip electrically connected to the device and having a second pad group for inputting / outputting second data; And a second semiconductor chip electrically connected to the first semiconductor chip and vertically penetrating at least one chip through via for interfacing the first and second data, A first bank group having at least one first and second banks for storing and providing one data; A first input / output line connected between the first bank and the chip through vias; A second input / output line connected between the second bank and the chip through vias; A second bank group having at least one third and fourth banks for storing and providing the second data; A third input / output line connected between the third bank and the chip through vias; A fourth input / output line connected between the fourth bank and the chip through vias; And electrically connecting the first and second input / output lines and the chip through via in response to a data width option signal and an address signal, electrically separating the third and fourth input / output lines from the chip through via, Output lines and the chip-through vias, electrically isolating the first and second input / output lines and the chip-through vias from each other, and electrically connecting the first and second input / output lines in response to the bank address signal, One of the third and fourth input / output lines and one of the chip-through vias is electrically connected to the other of the first and second input / output lines, And a data path selection unit for electrically connecting the remaining of the third and fourth input / output lines and the chip through via electrically, . ≪ / RTI >

According to another aspect of the present invention, there is provided a method of controlling a semiconductor memory device, comprising: entering a specific data width option mode in accordance with a data width option signal, wherein data is input / output through only one of the first and second pad groups; The first and second banks and the chip through vias are electrically connected and the third and fourth banks and the chip through vias are electrically disconnected in accordance with the address signal so that the first and second banks One of the first and second banks is electrically connected to the chip through via, and the remaining of the first and second banks and the chip through via are electrically separated; And transmitting data between any one of the first and second banks and the chip through vias.

The number of chip through vias for electrical connection with other stacked semiconductor chips can be reduced, thereby minimizing the area and saving the processing time and process cost.

In addition, by selectively connecting global input / output lines shared for each bank group corresponding to activated banks, it is possible to minimize line loading of global input / output lines. Therefore, it is possible to reduce the transition time of the data, thereby contributing to the improvement of the performance of the semiconductor memory device.

FIG. 1 is an internal configuration diagram of a slave chip included in a conventional semiconductor memory device.
FIG. 2 is an internal configuration diagram of a slave chip included in a semiconductor memory device according to another example of the related art.
3 is a side view for conceptually illustrating a semiconductor memory device according to an embodiment of the present invention.
4 is an internal configuration diagram of the slave chip shown in FIG.
5 is an internal configuration diagram for explaining the slave chip shown in FIG. 4 in more detail.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, so that those skilled in the art can easily carry out the technical idea of the present invention.

3 shows a side view of a semiconductor memory device according to an embodiment of the present invention. FIG. 4 shows an internal structure of the first slave chip shown in FIG. 3, and FIG. 1 shows an internal configuration diagram for explaining one slave chip in more detail.

3, the semiconductor memory device 100 includes a master chip 110 for exchanging various signals, power, data, and the like with an external device (not shown) The first to fourth slave chips 120A, 120B, 120C and 120D and the first to fourth slave chips 120A, 120B, 120C and 120D for storing and providing data under the control of the master chip 110, And a plurality of first through fourth chip through vias 130A, 130B, 130C for vertically penetrating each of the first through fourth slave chips 120A, 120B, 120C, 120D and interfacing data between the master chip 110 and the first through fourth slave chips 120A, , 130D.

Here, the master chip 110 has a plurality of data pads (not shown) for exchanging data with an external device. The first to eighth data pads will be referred to as a first pad group UDQ and the ninth to sixteenth data pads will be referred to as a second pad group LDQ.

Also, the first to fourth slave chips 120A, 120B, 120C and 120D have only a minimum configuration capable of storing and providing data under the control of the master chip 110. [ Here, since the first to fourth slave chips 120A, 120B, 120C and 120D all have the same configuration, only the first slave chip 120A will be exemplarily described below. Referring to FIG. 4, the first slave chip 120A includes first and second half bank groups BANK0 to BANK3 (BANK4 to BANK4) for storing and providing first data input / output through the first pad group UDQ, Bank groups BANK0 'to BANK3' for storing and providing second data input / output through the second pad group LDQ, and first and second half bank groups BANK0 'to BANK3' In response to the data width option signal X8, the address signal A14 and the bank address signal BA2, the second bank group 125A, 127A having the first to fourth banks BANK4 'to BANK7' The data path selection for electrically connecting any one of the half bank groups BANK0 to BANK3 (BANK4 to BANK7) (BANK0 'to BANK3') and BANK4 'to BANK7' to the plurality of first chip through vias 130A A plurality of first global input / output units 122A for actually connecting the first and second half bank groups BANK0 to BANK7 and a plurality of first chip through vias 130A, And a plurality of second global input / output lines GIO22 for actually connecting the third and fourth half bank groups BANK0 'to BANK7' and the plurality of first chip through vias 130A, .

Here, the data path selector 122A will be described in more detail with reference to FIG. 5, a data path selector 122A corresponding to one chip through via 130A and one global input / output line (GIO21, GIO22) is shown for convenience of explanation, Corresponding to the 64 chip through vias 130A and the 64 first and second global input / output lines GIO21 and GIO22 corresponding to the capacity of 64 Mbit - ) Shall be provided.

5, the data path selector 129A selects one of the first and third half bank groups 121A and 125A in response to the data width option signal X8, the address signal A14, and the bank address signal BA2. In response to the data width option signal X8, the address signal A14, and the bank address signal BA2, a first multiplexing section 129A_1 for electrically connecting any one of the chip- And a second multiplexing unit 129A_3 for electrically connecting any one of the fourth half bank groups 123A and 127A to the chip through vias 130A.

The first multiplexing unit 129A_1 includes a first bank path selection unit 129A_11 for selectively connecting the first connection node CN1 and the chip through via 130A in response to the bank address BA2, A first group path selection unit 129A_13 for selectively connecting the first connection node CN1 and the first half bank group 121A in response to the signal X8 and the address signal A14, In order to selectively connect the first connection node CN1 and the third half bank group 125A in response to the inverted signal of the inverted address signal-address signal A14 and the inverted address signal-address signal A14, Part 129A_15.

The second multiplexing unit 129A_3 includes a second bank path selection unit 129A_31 for selectively connecting the second connection node CN2 and the chip through via 130A in response to the bank address BA2, A third group path selector 129A_31 for selectively connecting the second connection node CN2 and the second half bank group 123A in response to the signal X8 and the address signal A14, (4) for selectively connecting the second connection node (CN2) and the fourth half bank group (127A) in response to the inverted address signal - address signal (A14) Part 129A_35.

Meanwhile, the plurality of chip through vias 130A include a through silicon via (TSV).

Hereinafter, a method of driving the semiconductor memory device 100 according to the embodiment of the present invention will be described. However, in the embodiment of the present invention, the write operation according to input / output of data through the eight data pads (first pad group (UDQ) or second pad group (LDQ)) in the X8 mode will be described as an example, Only the first slave chip 120A will be described.

When data is input through a first pad group (UDQ; not shown) provided in the master chip, the master chip transmits data to the first slave chip 120A through the plurality of chip through vias 130A.

At this time, only the first and second multiplexers 129A_1 and 129A_3 are enabled in the first slave chip 120A, and the data transmitted through the chip through vias 130A are transmitted to the first multiplexer 129A_1 or Are transmitted to any one of the first through fourth half bank groups 121A, 123A, 125A, and 127A through the second multiplexing unit 129A_3. In other words, the data path connected to the chip through via 130A in the X8 mode is determined according to the specific address signal A14 to which bank group 121A, 123A (125A, 127A) is to be connected and the bank address signal BA2 It is determined according to which half bank group 121A, 123A, 125A, and 127A to be connected. For example, when data is input through the first pad group UDQ and one of the banks BANK0, BANK1, BANK2, and BANK3 belonging to the first half bank group 121A is activated, the logic low level bank address signal The first multiplexer 129A_1 is enabled in accordance with the first multiplexer 129A_1 and the first global input / output line GIO21 and the chip through vias 130A through the first multiplexer 129A_1 in accordance with the address signal A14 of logic high level, And the data transmitted through the chip through vias 130A are finally transferred to the first half bank group 121A. At this time, the first global input / output line (GIO21) connected to the second half bank group 123A is electrically disconnected by the disabled second multiplexer 129A_3.

According to the embodiment of the present invention, data transferred to different bank groups can be transmitted through one chip through via, thereby reducing the number of chip through vias. In addition, when data is transferred to a specific half bank group, There is an advantage that the line loading of global input / output lines can be reduced by electrically separating paths.

The technical idea of the present invention has been specifically described according to the above embodiments, but it should be noted that the embodiments described above are for explanation purposes only and not for the purpose of limitation. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.

100: semiconductor memory device 110: master chip
120A to 120D: Slave chips 121A and 123A: first bank group
121A: first half bank group 123A: second half bank group
125A and 127A: second bank group 125A: third half bank group
127A: Half bank group 129A: Data path selection unit
129A_1: first multiplexing unit 129A_11: first bank path selection unit
129A_13: first group path selection unit 129A_15: second group path selection unit
129A_3: second multiplexer 129A_31: second bank path selector
129A_33: third group path selection unit 129A_35: fourth group path selection unit

Claims (9)

In a semiconductor memory device in which first and second semiconductor chips are stacked,
A first pad group electrically connected to an external device for inputting and outputting first data and a second pad group electrically connected to the external device for inputting and outputting second data; And
The second semiconductor chip electrically connected to the first semiconductor chip and vertically penetrating at least one chip-through via for interfacing the first and second data,
Wherein the second semiconductor chip comprises:
A first bank group having at least a first bank and a second bank for storing and providing the first data;
A first input / output line connected between the first bank and the chip through vias;
A second input / output line connected between the second bank and the chip through vias;
A second bank group having at least one third and fourth banks for storing and providing the second data;
A third input / output line connected between the third bank and the chip through vias;
A fourth input / output line connected between the fourth bank and the chip through vias; And
Output lines and the chip-through vias electrically in response to a data width option signal and an address signal, electrically isolating the third and fourth input / output lines from the chip-through vias, or electrically connecting the third and fourth input / And the fourth input / output line and the chip via via are electrically connected to electrically isolate the first and second input / output lines and the chip through via from each other, and in response to the bank address signal, One of the first and second input / output lines and the other of the first and second input / output lines is electrically connected to the other of the first and second input / And a data path selector for electrically isolating the remaining of the third and fourth input / output lines from the chip through via The semiconductor memory device.
The method according to claim 1,
Wherein the data path selector comprises:
Output lines and the chip-through vias in response to the data width option signal, the address signal, and the bank address signal, and electrically connecting the rest of the first and third input / A first multiplexer for electrically isolating the chip through vias; And
Output lines in response to the data width option signal, the address signal, and the bank address signal, electrically connecting any one of the second and fourth input / output lines to the chip- And a second multiplexer for electrically separating the chip through vias.
3. The method of claim 2,
Wherein the first multiplexer comprises:
A first bank path selection unit for selectively connecting the first connection node and the chip through via in response to the bank address;
A first group path selection unit for selectively connecting the first connection node and the first input / output line in response to the data width option signal and the address signal; And
And a second group path selector for selectively connecting the first connection node and the third input / output line in response to the data width option signal and an inverted address signal, which is an inverted signal of the address signal, Device.
3. The method of claim 2,
Wherein the second multiplexer comprises:
A second bank path selection unit for selectively connecting the second connection node and the chip through via in response to the bank address;
A third group path selector for selectively connecting the second connection node and the second input / output line in response to the data width option signal and the address signal; And
And a fourth group path selector for selectively connecting the second connection node and the fourth input / output line in response to the data width option signal and the inverted address signal - the inverted signal of the address signal - Device.
The method according to claim 1,
And the first to fourth input / output lines each include a global input / output line.
The method according to claim 1,
And the first to fourth input / output lines are provided corresponding to the capacities of the first to fourth banks, respectively.
The method according to claim 1,
Wherein the chip through vias include a through silicon via (TSV).
A method of driving a semiconductor memory device according to any one of claims 1 to 7,
Entering a specific data width option mode according to the data width option signal, wherein data is input / output through only one of the first and second pad groups;
The first and second banks and the chip through vias are electrically connected and the third and fourth banks and the chip through vias are electrically disconnected in accordance with the address signal, And electrically connecting the chip through vias to one of the first banks and the second banks, and electrically isolating the remaining ones of the first and second banks from the chip through vias; And
Wherein data is transferred between any one of the first and second banks and the chip through vias
And a driving method of the semiconductor memory device.
9. The method of claim 8,
Wherein the first and second banks and the chip through vias are electrically disconnected in accordance with the address signal and the third and fourth banks and the chip through vias are electrically connected, One of the fourth banks is electrically connected to the chip through via and the remaining of the third and fourth banks and the chip through via are electrically separated; And
And transferring data between any one of the third and fourth banks and the chip through vias.

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