KR20130072044A - Integrated circuit system and memory system - Google Patents
Integrated circuit system and memory system Download PDFInfo
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- KR20130072044A KR20130072044A KR1020110139589A KR20110139589A KR20130072044A KR 20130072044 A KR20130072044 A KR 20130072044A KR 1020110139589 A KR1020110139589 A KR 1020110139589A KR 20110139589 A KR20110139589 A KR 20110139589A KR 20130072044 A KR20130072044 A KR 20130072044A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
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Abstract
A memory system according to the present invention includes: a first memory chip including an input / output unit; A second memory chip including a first bank group including one or more banks and a second bank group including one or more banks; At least one first transmission line for transferring data input to the input / output unit to the first bank group or the second bank group; And at least one second transmission line for transferring data output from the first bank group or the second bank group to the input / output unit.
Description
The present invention relates to a memory system.
BACKGROUND OF THE INVENTION In the field of integrated circuit systems, the packaging technology of semiconductor devices has been continuously developed according to the demand for miniaturization and high capacity. In recent years, various technologies have been developed for multilayer semiconductor packages that can satisfy mounting efficiency along with miniaturization and high capacity.
The stacked semiconductor package may be manufactured by stacking individual semiconductor chips and then packaging the stacked chips at a time and stacking the packaged individual semiconductor packages. The individual semiconductor chips of the stacked semiconductor package may be formed of metal wires or through silicon. It is electrically connected through a through silicon via (TSV).
However, the conventional laminated semiconductor package using the metal wire is slow because the electrical signal exchange is made through the metal wire, a large number of wires are used to cause electrical characteristics deterioration. In addition, an additional area is required in the substrate to form a metal wire, thereby increasing the size of the package, and a height of the package is increased because a cap for wire bonding between semiconductor chips is required.
Thus, recently, a multilayer semiconductor package using a through silicon via (TSV) has been proposed. In general, a stacked semiconductor package forms a via hole penetrating a semiconductor chip in a semiconductor chip, and fills a conductive material in the penetrated via hole to form a through electrode called a through silicon via. The lower semiconductor chip is electrically connected to each other.
On the other hand, in the memory system, the master chip is usually located at the bottom of the stacked semiconductor package, and receives a command, address, data, etc. from the memory controller and transfers the data to the slave chip or the interface chip for transferring the output data of the slave chip to the memory controller. Say Many slave chips store or output data using commands and addresses delivered through the master chip. Here, the master chip and each of the plurality of slave chips are connected through through silicon vias, and signals (eg, commands, addresses, data, etc.) are transmitted between the master chip and the plurality of slave chips through the through silicon vias.
The memory system includes one or more ranks. Here, the rank refers to a unit memory chip having an independent function controlled by one chip select signal. The rank includes a plurality of banks. The data is divided into one or more bank groups to control the data access operation. At this time, the more bank groups, the longer the tCCD (CAS to CAS Delay, the minimum separation time at which a column access command is made in a bank and the next column access command) can be secured. An increase in the number of silicon vias reduces the yield of the memory system. Therefore, there is a need to develop a memory system optimized for tCCD and yield.
The present invention provides a memory system having a high yield by controlling the number of bank groups to reduce the number of transmission lines for transferring data between memory chips while securing a minimum tCCD.
A memory system according to the present invention includes a first memory chip including an input and output unit; A second memory chip including a first bank group including one or more banks and a second bank group including one or more banks; At least one first transmission line for transferring data input to the input / output unit to the first bank group or the second bank group; And at least one second transmission line transferring data output from the first bank group or the second bank group to the input / output unit.
In addition, the memory system according to the present invention includes a first bank group including one or more banks, a second bank group including one or more banks, and a first memory chip including an input / output unit; A second memory chip including a third bank group including one or more banks and a fourth bank group including one or more banks; At least one first transmission line transferring data inputted to the input / output unit to the third bank group or the fourth bank group; And at least one second transmission line transferring data output from the third bank group or the fourth bank group to the input / output unit.
The memory system according to the present invention can guarantee a tCCD by dividing and controlling a plurality of banks into a number of bank groups capable of securing a minimum tCCD, while increasing the yield by reducing the number of transmission lines for transferring data between memory chips.
1 is a configuration diagram of a memory system according to an embodiment of the present invention;
2 is a block diagram of a memory system according to another embodiment of the present invention.
Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.
1 is a block diagram of a memory system according to an embodiment of the present invention. The memory system of FIG. 1 includes a configuration in which the first memory chip (master chip) and the second memory chip (slave chip) are different from each other, and thus the first memory chip does not include a configuration for storing data. Include only configuration for.
As shown in FIG. 1, the memo system includes a first memory chip C1 including an input / output unit IO, a bank group including one or more banks B0 to B3, and B0 hereinafter. To a second memory chip (C2) and an input / output unit (IO) including a second bank group (hereinafter, referred to as B4 to B7) and a second bank group including one or more banks. One or more first transmission lines GIO1 <0: 127> and the first bank group B0 to B3 transferring the input data to the first bank group B0 to B3 or the second bank group B4 to B7. Or one or more second transmission lines GIO2 <0: 127> for transferring data output from the second bank groups B4 to B7 to the input / output unit IO.
The first memory chip C1 transfers the data transferred to one or more first transmission lines GIO1 <0: 127> to a bank included in the first bank groups B0 to B3 or to the first bank group B0 to B1. One or more first local transmission lines LIO1 <0: 127> for transferring data output from the bank included in B3) to one or more second transmission lines GIO2 <0: 127>. Data transmitted from the GIO1 <0: 127>) to the banks included in the second bank groups B4 to B7, or data output from the banks included in the second bank groups B4 to B7. Receive one or more data from one or more second local transmission lines (LIO2 <0: 127>) and one or more first transmission lines (GIO1 <0: 127>) to transmit to the transmission lines (GIO2 <0: 127>). One or more second transmission lines GIO2 <0: 127> that are transmitted to the first local transmission line LIO1 <0: 127> or receive data from one or more first local transmission lines LIO1 <0: 127>. Sent by Receives data from one transmission / reception circuit TR1 and one or more first transmission lines GIO1 <0: 127> and transmits the data to one or more second local transmission lines LIO2 <0: 127> or one or more second local transmissions. The second transmission / reception circuit TR2 receives the data of the lines LIO2 <0: 127> and transmits the data to one or more second transmission lines GIO2 <0: 127>.
Here, at least one first transmission line GIO1 <0: 127> is a transmission line used when writing data, and at least one second transmission line GIO2 <0: 127> is a transmission line used when reading data. At least one first local transmission line (LIO1 <0: 127>) and at least one second local transmission line (LIO2 <0: 127>) are transmission lines used for writing and reading data.
Hereinafter, an operation of the memory system will be described with reference to FIG. 1.
Each bank group includes four banks, each of one or more first transmission lines GIO1 <0: 127> and one or more second transmission lines GIO2 <0: 127>, each of which is 128, and one or more first The case of 128 local transmission lines LIO1 <0: 127> and one or more second local transmission lines LIO2 <0: 127> will be described.
During the write operation, data to be written to the first bank group B0 to B3 or the second bank group B4 to B7 is inputted to the input / output unit IO of the first chip C1 to provide at least one first transmission line GIO1. <0: 127>). The at least one first transmission line GIO1 <0: 127> is a transmission line for transmitting data to be written, and may each include a first through silicon via TSV1 <0: 127>.
The first receiving circuit Rx included in the first transmitting and receiving circuit TR1 receives data of one or more first transmission lines GIO1 <0: 127> and receives a first local transmission line LIO1 <0: 127>. The second receiving circuit Rx included in the second transmitting / receiving circuit TR2 receives data from one or more first transmission lines GIO1 <0: 127>, and the second local transmission line LIO2 <0. : 127>). Data of one or more first local transmission lines LIO1 <0: 127> is addressed by an address among banks included in the first bank group B0 to B3 via a 'SA & DRV' block for sensing, amplifying and driving data. Passed to the specified bank. Data of one or more second local transmission lines LIO2 <0: 127> is addressed by an address among banks included in the second bank groups B4 to B7 via a 'SA & DRV' block for sensing, amplifying and driving data. Passed to the specified bank.
In the read operation, data output from the banks included in the first bank groups B0 to B3 is transferred to one or more first local transmission lines LIO1 <0: 127> through the 'SA & DRV' block and the second data. Data output from the banks included in the bank groups B4 to B7 is transferred to one or more second local transmission lines LIO2 <0: 127> through the 'SA & DRV' blocks.
The first transmission circuit Tx included in the first transmission and reception circuit TR1 receives data from one or more first local transmission lines LIO1 <0: 127> and receives one or more second transmission lines GIO2 <0: 127. And the second transmission circuit Tx included in the second transmission / reception circuit TR2 receives data from one or more second local transmission lines LIO2 <0: 127>. GIO2 <0: 127>). Data of one or more second transmission lines GIO2 <0: 127> is transferred to the input / output unit IO and output to the outside of the memory system through the input / output unit IO. The at least one second transmission line GIO2 <0: 127> is a transmission line for transferring read data and may include a second through silicon via TSV2 <0: 127>.
2 is a configuration diagram of a memory system according to another embodiment of the present invention. The memory system of FIG. 1 includes a configuration in which a first memory chip stores data and an interface for data interface, including a configuration in which a first memory chip (master chip) and a second memory chip (slave chip) are the same. do.
As shown in FIG. 2, the memory includes a first bank group including one or more banks (bank group including B0 to B3, hereinafter referred to as B0 to B3), and a second bank group including one or more banks (B4). A bank group including B7 to B7, hereinafter referred to as B4 to B7, a first memory chip C1 including an input / output unit IO, and a third bank group including one or more banks B8 to B11 A second memory chip C2 including an group, hereinafter referred to as B8 to B11) and a fourth bank group including one or more banks (hereinafter, referred to as a bank group including B11 to B15, hereinafter referred to as B11 to B15), an input / output unit One or more first transmission lines GIO1 <0: 127> and a third bank group that transfer the data inputted to (C2) to the third bank group B7 to B11 or the fourth bank group B12 to B15. One or more second transmission lines GIO2 <0: 127> for transferring data output from the B7 to B11 or the fourth bank groups B12 to B15 to the input / output unit IO.
The first memory chip C1 transfers the data transferred to one or more first transmission lines GIO1 <0: 127> to a bank included in the first bank groups B0 to B3 or to the first bank group B0 to B1. One or more first local transmission lines (LIO1 <0: 127>) and one or more first transmission lines for transferring data output from the bank included in B3) to one or more second transmission lines GIO2 <0: 127>. Data transmitted to (GIO1 <0: 127>) is transferred to the banks included in the second bank groups B4 to B7, or data output from the banks included in the second bank groups B3 to B7 is stored. Receives data from one or more second local transmission lines (LIO2 <0: 127>) and one or more first transmission lines (GIO1 <0: 127>) to be transmitted to two transmission lines (GIO2 <0: 127>). One or more second transmission lines GIO2 <0: 127> may be transmitted to the first local transmission lines LIO1 <0: 127> or receive data from one or more first local transmission lines LIO1 <0: 127>. Sent with) Receives data from the first transmission / reception circuit TR1 and one or more first transmission lines GIO1 <0: 127> and transmits the data to one or more second local transmission lines LIO2 <0: 127> or one or more second locals. The second transmission / reception circuit TR2 receives the data of the transmission line LIO2 <0: 127> and transmits the data to one or more second transmission lines GIO2 <0: 127>.
The second memory chip C2 transfers the data transferred to the one or more first transmission lines GIO1 <0: 127> to the banks included in the third bank groups B8 to B11 or the third bank group B8 to One or more third local transmission lines (LIO3 <0: 127>) and one or more first transmission lines for transferring data output from the bank included in B11) to one or more second transmission lines GIO2 <0: 127>. Data transmitted to (GIO1 <0: 127>) is transferred to the banks included in the fourth bank groups B12 to B15, or data output from the banks included in the fourth bank groups B12 to B15 is stored. Receives data from one or more fourth local transmission lines (LIO4 <0: 127>) and one or more first transmission lines (GIO1 <0: 127>) to be transmitted to two transmission lines (GIO2 <0: 127>). One or more second transmission lines GIO2 <0: 127 are transmitted to the third local transmission lines LIO3 <0: 127> or receive data from the one or more third local transmission lines LIO3 <0: 127>. >) Receives data from the third transmitting and receiving circuit TR3 and one or more first transmission lines GIO1 <0: 127> and transmits the data to one or more fourth local transmission lines LIO4 <0: 127> or one or more agents. The fourth transmission and reception circuit TR4 receives the data of the four local transmission lines LIO4 <0: 127> and transmits the data to one or more second transmission lines GIO2 <0: 127>.
Here, at least one first transmission line GIO1 <0: 127> is a transmission line used when writing data, and at least one second transmission line GIO2 <0: 127> is a transmission line used when reading data. One or more first local transmission lines to fourth local transmission lines LIO1 <0: 127> to LIO4 <0: 127> are transmission lines used for writing and reading data.
Hereinafter, an operation of the memory system will be described with reference to FIG. 2.
Each bank group includes four banks, each of one or more first transmission lines GIO1 <0: 127> and one or more second transmission lines GIO2 <0: 127>, each of which is 128, and one or more first The case where there are 128 local transmission lines to fourth local transmission lines LIO1 <0: 127> to LIO4 <0: 127> will be described.
During the write operation, data to be written to the first bank group B0 to B3 or the second bank group B4 to B7 is inputted to the input / output unit IO of the first chip C1 to provide at least one first transmission line GIO1. <0: 127> and data to be written to the third bank group B7 to B11 or the fourth bank group B12 to B15 are inputted to the input / output unit IO of the first chip C1. It is transmitted through one or more first transmission lines GIO1 <0: 127>. The at least one first transmission line GIO1 <0: 127> is a transmission line for transmitting data to be written, and may each include a first through silicon via TSV1 <0: 127>. In this case, data to be written to the third bank group B7 to B11 or the fourth bank group B12 to B15 passes through the first through silicon via TSV1 <0: 127>, and the first bank group B0 to B3. Alternatively, data to be written to the second bank groups B4 to B7 does not pass through the first through silicon via TSV1 <0: 127>.
The first receiving circuit Rx included in the first transmitting and receiving circuit TR1 receives data of one or more first transmission lines GIO1 <0: 127> and receives a first local transmission line LIO1 <0: 127>. The second receiving circuit Rx included in the second transmitting / receiving circuit TR2 receives data from one or more first transmission lines GIO1 <0: 127>, and the second local transmission line LIO2 <0. : 127>). The third receiving circuit Rx included in the third transmitting and receiving circuit TR3 receives data of one or more first transmission lines GIO1 <0: 127> and receives a third local transmission line LIO3 <0: 127>. The fourth receiving circuit Rx included in the fourth transmitting and receiving circuit TR4 receives the data of one or more first transmission lines GIO1 <0: 127> and transmits the fourth local transmission line LIO4 <0. : 127>).
Data of one or more first local transmission lines LIO1 <0: 127> is addressed by an address among banks included in the first bank group B0 to B3 via a 'SA & DRV' block for sensing, amplifying and driving data. The data of the second local transmission line LIO2 <0: 127> is transferred to the designated bank and included in the second bank group B4 to B7 through the 'SA & DRV' block for sensing, amplifying, and driving the data. The bank is transferred to the bank designated by the address. Data of one or more third local transmission lines LIO3 <0: 127> is addressed by an address among banks included in the third bank group B8 to B11 via a 'SA & DRV' block for sensing, amplifying and driving data. The data of the fourth local transmission line LIO4 <0: 127> is transferred to the designated bank and included in the fourth bank group B12 to B15 through the 'SA & DRV' block that senses, amplifies, and drives the data. The bank is transferred to the bank designated by the address.
In the read operation, data output from the banks included in the first bank groups B0 to B3 is transferred to one or more first local transmission lines LIO1 <0: 127> through the 'SA & DRV' block and the second data. Data output from the banks included in the bank groups B4 to B7 is transferred to one or more second local transmission lines LIO2 <0: 127> through the 'SA & DRV' blocks. In addition, data output from the banks included in the third bank groups B8 to B11 is transferred to one or more third local transmission lines LIO3 <0: 127> through the 'SA & DRV' block, and the fourth bank group. Data output from the banks included in (B12 to B15) is transferred to one or more fourth local transmission lines (LIO4 <0: 127>) via the 'SA & DRV' block.
The first transmission circuit Tx included in the first transmission and reception circuit TR1 receives data from one or more first local transmission lines LIO1 <0: 127> and receives one or more second transmission lines GIO2 <0: 127. And the second transmission circuit Tx included in the second transmission / reception circuit TR2 receives data from one or more second local transmission lines LIO2 <0: 127>. GIO2 <0: 127>). The third transmission circuit Tx included in the third transmission and reception circuit TR3 receives data from one or more third local transmission lines LIO3 <0: 127> and receives one or more second transmission lines GIO2 <0: 127. >), And the fourth transmission circuit Tx included in the fourth transmission / reception circuit TR4 receives data from one or more fourth local transmission lines LIO4 <0: 127>, and transmits one or more second transmission lines (Tx). GIO2 <0: 127>). Data of one or more second transmission lines GIO2 <0: 127> is transferred to the input / output unit IO and output to the outside of the memory system through the input / output unit IO. The at least one second transmission line GIO2 <0: 127> is a transmission line for transferring read data and may include a second through silicon via TSV2 <0: 127>.
1 and 2 illustrate a memory system including two memory chips, but the present invention may be applied to a memory system including two or more memory chips. As the number of banks included in the rank is divided into more groups, more tCCDs can be secured, but since the through silicon vias must be provided for each group, the number of through silicon vias required increases, resulting in a lower yield. Dividing a plurality of banks into smaller groups reduces the number of through-silicon vias, resulting in higher yields, but it is difficult to secure tCCD. The present invention can increase the yield by reducing the number of through silicon vias while securing a minimum tCCD by dividing and controlling a plurality of banks included in the ranks into two groups.
While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit and scope of the invention.
Claims (5)
A second memory chip including a first bank group including one or more banks and a second bank group including one or more banks;
At least one first transmission line for transferring data input to the input / output unit to the first bank group or the second bank group; And
At least one second transmission line transferring data output from the first bank group or the second bank group to the input / output unit;
≪ / RTI >
The first memory chip
One or more transfer data transferred to the one or more first transmission lines to a bank included in the first bank group or transfer data output from a bank included in the first bank group to the one or more second transmission lines. A first local transmission line;
One or more transfer data transferred to the one or more first transmission lines to a bank included in the second bank group or transfer data output from a bank included in the second bank group to the one or more second transmission lines. A second local transmission line;
A first transmission / reception circuit that receives data of the one or more first transmission lines and transmits the data to the one or more first local transmission lines or receives and transmits data of the one or more first local transmission lines to the one or more second transmission lines. ; And
A second transmission / reception circuit that receives data of the one or more first transmission lines and transmits the data to the one or more second local transmission lines or receives and transmits data of the one or more second local transmission lines to the one or more second transmission lines.
≪ / RTI >
A second memory chip including a third bank group including one or more banks and a fourth bank group including one or more banks;
At least one first transmission line transferring data inputted to the input / output unit to the third bank group or the fourth bank group; And
At least one second transmission line transferring data output from the third bank group or the fourth bank group to the input / output unit;
≪ / RTI >
The first memory chip
One or more transfer data transferred to the one or more first transmission lines to a bank included in the first bank group or transfer data output from a bank included in the first bank group to the one or more second transmission lines. A first local transmission line;
One or more transfer data transferred to the one or more first transmission lines to a bank included in the second bank group or transfer data output from a bank included in the second bank group to the one or more second transmission lines. A second local transmission line;
A first transmission / reception circuit that receives data of the one or more first transmission lines and transmits the data to the one or more first local transmission lines or receives and transmits data of the one or more first local transmission lines to the one or more second transmission lines. ; And
A second transmission / reception circuit that receives data of the one or more first transmission lines and transmits the data to the one or more second local transmission lines or receives and transmits data of the one or more second local transmission lines to the one or more second transmission lines. More,
The second memory chip
One or more transfer data transferred to the one or more first transmission lines to a bank included in the third bank group or transfer data output from a bank included in the third bank group to the one or more second transmission lines. A third local transmission line;
One or more transfer data transferred to the one or more first transmission lines to a bank included in the fourth bank group or transfer data output from a bank included in the fourth bank group to the one or more second transmission lines. A fourth local transmission line;
A third transmission and reception circuit which receives the data of the one or more first transmission lines and transmits the data to the one or more third local transmission lines or receives and transmits the data of the one or more third local transmission lines to the one or more second transmission lines. ; And
A fourth transmission and reception circuit which receives the data of the one or more first transmission lines and transmits the data to the one or more fourth local transmission lines or receives and transmits the data of the one or more fourth local transmission lines to the one or more second transmission lines. Memory system further comprising.
And the one or more first transmission lines and the one or more second transmission lines comprise through silicon vias.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020110139589A KR20130072044A (en) | 2011-12-21 | 2011-12-21 | Integrated circuit system and memory system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020110139589A KR20130072044A (en) | 2011-12-21 | 2011-12-21 | Integrated circuit system and memory system |
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| KR20130072044A true KR20130072044A (en) | 2013-07-01 |
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| KR1020110139589A KR20130072044A (en) | 2011-12-21 | 2011-12-21 | Integrated circuit system and memory system |
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| KR (1) | KR20130072044A (en) |
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2011
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