KR20060083746A - Substrate for display panel and testing method by using the same - Google Patents

Abstract

Disclosed are a display panel substrate and an inspection method using the same. The gate driving circuit unit is electrically connected to one side of the plurality of gate lines, and outputs a plurality of gate signals, respectively. The gate auxiliary circuit part is electrically connected to the other sides of the gate lines, thereby pulling down the gate signal applied to the gate line. The first inspection unit applies a test signal to an input terminal of the gate driving circuit unit. The second test unit applies a test signal to an input terminal of the gate auxiliary circuit unit. The switching unit is electrically connected to the final stage of the gate auxiliary circuit unit to control the operation of the gate auxiliary circuit unit. This can facilitate the 2G array inspection process.

Gate Drive Circuit, Gate Auxiliary Circuit, 2G Array Inspection

Description

Substrate for display panel and inspection method using same {SUBSTRATE FOR DISPLAY PANEL AND TESTING METHOD BY USING THE SAME}

1 is a schematic plan view of a substrate for a display panel according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed block diagram of a display panel substrate shown in FIG. 1 according to a first exemplary embodiment.

3 is a detailed block diagram of a display panel substrate shown in FIG. 1 according to a second exemplary embodiment.

<Description of the symbols for the main parts of the drawings>

130: gate driving circuit 140: gate auxiliary circuit

150: gate inspection unit 152: first inspection pad

154: second test pad 156: third test pad

TRc: control transistor

The present invention relates to a display panel substrate and an inspection method thereof, and more particularly, to a display panel substrate and an inspection method using the same.

In general, a liquid crystal display includes a liquid crystal display panel having a plurality of gate lines and a plurality of data lines, a gate driving circuit for outputting a gate signal to the plurality of gate lines, and a data driving circuit for outputting a data signal to the plurality of data lines. It is made of furnace. The gate driving circuit and the data driving circuit are mounted on the liquid crystal display panel in a chip form.

In order to increase productivity while reducing the overall size of the liquid crystal display, a structure for integrating a gate driving circuit into a liquid crystal display panel has been developed.

When the gate lines and the data lines are formed on the array substrate during the manufacturing process of the liquid crystal display panel, an inspection process for inspecting an electrical operation state of each of the lines is performed. The inspection process uses a 1G method of applying the test signal by binding the gate lines together.

When a test operation is performed by applying a gate pulse to the gate driving circuit in the 1G method, defects of adjacent pixels may be detected during a high level period of the gate signal due to driving characteristics of the gate driving circuit.

However, since the gate signal sensed by the gate wiring in the period in which the gate signal is substantially low level is floated to a high level, there is a problem in that failure detection is not practical.

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display panel substrate for facilitating a 2G array inspection process.

Another object of the present invention is to provide an inspection method using the display panel substrate.

A display panel substrate according to an exemplary embodiment of the present invention includes a gate driving circuit part, a gate auxiliary circuit part, a first test part, a second test part, and a switching part. The gate driving circuit unit is electrically connected to one side of the plurality of gate lines, and outputs a plurality of gate signals, respectively. The gate auxiliary circuit part is electrically connected to the other side of the gate wires to pull down the gate signal applied to the gate wire. The first inspection unit applies a test signal to an input terminal of the gate driving circuit unit. The second test unit applies the test signal to an input terminal of the gate auxiliary circuit unit. The switching unit is electrically connected to a final end of the gate auxiliary circuit unit to control the operation of the gate auxiliary circuit unit.

 The gate auxiliary circuit part includes a plurality of pull-down transistors electrically connected to the other sides of the gate lines, wherein the switching part is diode-connected with a gate electrode and a drain electrode, and a source electrode is the last pull-down of the pull-down transistors. It is connected to the gate electrode of the transistor.

Preferably, the second test unit applies a test signal to the first test pad unit for applying a test signal to pull-down transistors connected to the odd-numbered gate lines and the pull-down transistors connected to the even-numbered gate lines. And a second test pad portion to be applied.

More preferably, the gate electrode of the control switching device is electrically connected to any one of the first test pad unit and the second test pad unit.

A first test signal is applied to the first test unit and the first and first test pads to activate the display area, and a second test signal is applied to the first test unit and the first test pad to display the display area. The display areas corresponding to the even-numbered gate lines are activated.

The display area is activated by applying a first test signal to the first test part and the first and first test pads, and applying a second test signal to the first test part and the second test pad. The display areas corresponding to the odd-numbered gate lines are activated.

According to another aspect of the present invention, there is provided a method of inspecting a substrate for a display panel, the method including: applying a gate-on voltage to all of the gate lines to activate the entire display area; Applying a gate-off voltage to odd-numbered gate lines to activate the display area corresponding to the even-numbered line, maintaining the gate-on voltage at even-numbered gate lines, and totally activating the entire display area. Applying a gate-on voltage to gate lines of the gate line and applying a gate-off voltage to even-numbered gate lines to activate a display area corresponding to an odd-numbered line of the display area, and applying the gate-off voltage to odd-numbered gate lines. Maintaining a gate on voltage.

According to the display panel substrate and the inspection method using the same, the 2G array inspection process can be facilitated with respect to the substrate including the gate driving circuit integrated in the display panel substrate.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a schematic plan view of a substrate for a display panel according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the display panel substrate 100 includes a display area DA in which an image is displayed and a peripheral area PA surrounding the display area DA. The display area DA includes a plurality of pixel areas defined by a plurality of data lines DL and a plurality of gate lines GL. In the pixel region, a switching element TFT, a pixel electrode connected to the switching element TFT, and a storage capacitor CST are formed. The pixel electrode defines a first electrode of the liquid crystal capacitor CLC.

The peripheral region may include a first peripheral region PA1 positioned at one end of the plurality of gate lines GL, a second peripheral region PA2 positioned at the other end of the plurality of gate lines GL, and a plurality of The third peripheral area PA3 is positioned at one end of the data lines DL.

A gate driving circuit 130 for outputting gate signals to gate lines is integrated in the first peripheral area PA1, and gate signals output from the gate driving circuit 130 are output to the second peripheral area PA2. The gate auxiliary circuit 140 for determining the low level VSS is integrated.

A data driving circuit for outputting data signals to data lines is mounted or integrated in the third peripheral area PA3. In addition, a gate inspection unit 150 for applying a test signal to the gate driving circuit 130 and the gate auxiliary circuit 140 is formed in the third peripheral area PA3. The gate inspecting unit 150 includes a first test pad 152 for applying a test signal to the gate driving circuit 130 and a second test pad 154 and a third test for applying a test signal to the gate auxiliary circuit 140. Pad 156 is formed.

FIG. 2 is a detailed block diagram of a display panel substrate shown in FIG. 1 according to a first exemplary embodiment.

Referring to FIG. 2, the gate driving circuit 130 includes n stages SRC1, SRC2,..., SRCn and a dummy stage SRCd, and a plurality of stages are cascaded.

Each of the stages is formed by integrating a plurality of thin film transistors, and has an input terminal and an output terminal. The input terminals include an input terminal IN through which a vertical start signal STV or a previous stage output signal is input, and a control terminal CL through which an output signal of a next stage or a dummy stage SRCd is input. And a clock terminal CK to which the first clock signal CKV or the second clock signal CKVB is input, and a voltage terminal VSS to which the off voltage VSS is applied.

The output terminal is connected to the corresponding gate lines to output gate signals G1, G2, .. Gn. The first clock signal CKV is provided to odd-numbered stages, and the second clock signal CKVB is provided to even-numbered stages. The first clock signal CKV and the second clock signal CKVB have phases opposite to each other.

In the operation of the gate driving circuit 130, the first stage SRC1 is driven by the vertical start signal STV, the first clock signal CKV or the second clock signal CKVB, and the off voltage VSS. At the start, the remaining stages are inputted with the output signal of the previous stage to the input terminal IN, and the output signal of the next stage is input to the control terminal CL to sequentially receive the gate signals G1, G2, ..Gn. Output

The gate auxiliary circuit 140 may include pull-down transistors TR1, TR2,... TRn that pull-down output signals of the plurality of stages to a low level based on an off voltage VSS. And a control transistor TRc for turning on the down transistors TR1, TR2, ..., TRn.

The odd-numbered pull-down transistors TR1, TR3,..., TRn-1 and the control transistor TRc of the pull-down transistors TR1, TR2,..., TRn are connected to each other by a first wiring. The first input terminal 141 of the gate auxiliary circuit 140 is formed at an end of the first wiring.

Drain electrodes of even-numbered pull-down transistors (TR2, TR4, .., TRn) of the pull-down transistors TR1, TR2,..., TRn are connected to a second wiring, The second input terminal 141 of the gate auxiliary circuit 140 is formed at an end thereof.

The gate electrode of each pull-down transistor TR1 is applied with the output signal G2 of the next stage, the source electrode is applied with the output signal G1 of the current stage, and the drain electrode has an off voltage VSS. Is approved. As a result, when the output signal G2 is applied to the gate electrode from the next stage, the output signal G1 of the current stage is pulled down to the low level VSS.

The control transistor TRc is formed for a 2G array inspection process, and a gate electrode and a drain electrode are diode-connected to be electrically connected to the first wiring (or the first input terminal 141), and the source electrode is the last pull. It is connected to the gate electrode of the -down transistor TRn.

In detail, during the 2G array inspection process, the control transistor TRc electrically connected to the first wiring is turned on by the first test signal VON applied to the first input terminal 141. When the control transistor TRc is turned on, the last pull-down transistor TRn connected to the control transistor TRc is turned on. The cascaded pull-down transistors TR1, TR2,..., TRn are turned on.

Accordingly, during the 2G array inspection process, the pull-down transistors TR1, TR2,..., And TRn adjust the level of the gate signals output from the stages SRC1, .. SRCn to the first input terminal 141. Is maintained at the level of the first test signal (VON) applied from.

A test signal is applied to the gate lines GL formed on the substrate through the gate driving circuit 130 and the gate auxiliary circuit 140 to inspect the gate lines in a 2G manner.

3 is a detailed block diagram of a display panel substrate shown in FIG. 1 according to a second exemplary embodiment. The same components as those in the first embodiment shown in FIG. 2 will be described with the same reference numerals.

Referring to FIG. 3, the gate driving circuit 130 is composed of n stages SRC1, SRC2,..., SRCn and a dummy stage SRCd, and a plurality of stages are cascaded.

The gate auxiliary circuit 140 may include pull-down transistors TR1, TR2,... TRn that pull-down output signals of the plurality of stages to a low level based on an off voltage VSS. A control transistor TRc that controls the operation of the down transistors TR1, TR2, ..., TRn.

Specifically, the odd-numbered pull-down transistors TR1, TR3,..., TRn-1 are connected to the first input terminal 141 of the gate auxiliary circuit 140 through a first wiring. The even-numbered pull-down transistors TR2, TR4,..., TRn and the control transistor TRc are connected to the second input terminal 142 of the gate auxiliary circuit 140 through a second wiring.

The control transistor TRc is formed for a 2G array inspection process, and a gate electrode and a drain electrode are diode-connected to be electrically connected to the second wiring (or the second input terminal 142), and the source electrode is the last pull. It is connected to the gate electrode of the -down transistor TRn.

That is, the control transistor TRc is a switching device that turns on the pull-down transistors TR2, TR4,..., TRn. As a result, when the first test signal VON is applied from the second input terminal 142, the control transistor TRc is turned on, whereby the pull-down transistors TR2, TR4, ..., TRn) is turned on.

Therefore, during the 2G array inspection process, the pull-down transistors TR1, TR2,..., And TRn adjust the level of the gate signals output from the stages SRC1, .. SRCn to the second input terminal 142. Is maintained at the level of the first test signal (VON) applied from.

The 2G array inspection method by the gate inspection unit 150 is as follows.

Referring to FIGS. 1 and 2, the gate inspecting unit 150 may include a first inspection pad 152 and a gate auxiliary circuit 140 configured to apply a test signal to the input terminals 131, 132, 133, and 134 of the gate driving circuit 130. And a second test pad 154 and a third test pad 156 for applying a test signal to the first input terminal 141 and the second input terminal 142.

The first test pad 152 includes a first clock terminal 131, a second clock terminal 132, a start signal input terminal 133, and an off voltage input terminal of the gate driving circuit 130. 134 is formed at an end of the wiring which is bundled together. The second test pad 154 is formed at an end extending from the first input terminal 141 of the gate auxiliary circuit 140, and the third test pad 156 is formed of the gate auxiliary circuit 140. 2 is formed at the input terminal 142 and the extended end.

First, a process of inspecting an electrical operation state of even-numbered gate lines is as follows.

In a first step, the first test signal VON is applied to the first test pad 152, the second test pad 154, and the third test pad 156. Of course, when the test signal is applied to the gate checker 150, it is natural that the test data voltage is also applied to the data lines.

As the first test signal VON is applied to the first test pad 152, the plurality of stages SRC1 and SRCn are driven to generate a gate-on voltage having a predetermined level. The generated gate on voltages are output to the corresponding gate lines GL1, GL2,..., GLn. As a result, a gate-on voltage corresponding to the first test signal is applied to the gate lines GL1, GL2,..., GLn.

As the first test signal VON is applied to the second test pad 154, the control transistor TRc is turned on, and the pull-down transistors TR1, TR2,..., TRn are turned on. do. The pull-down transistors TR1, TR2,... TRn are applied to the gate lines GL1, GL2,... By the first test voltage VON applied to the second and third test pads 154, 156. The gate-on voltage applied to .GLn is maintained at the level of the first test signal VON.

Accordingly, the switching elements formed in the plurality of pixel regions are turned on to apply the test data voltage to the pixel electrode.

In a second step, in a state in which the first test signal VON is applied to the third test pad 156, the first test pad 152 and the second test pad 154 have a second test signal ( VOFF). The switching elements TFT connected to the odd-numbered gate lines GL1, GL3,..., GLn-1 electrically connected to the second test pad 154 by the second test signal are turned off. As the switching elements are turned off, the test data voltage applied to the pixel electrode connected to the odd-numbered gate lines GL1, GL3,..., GLn-1 is discharged.

Meanwhile, the first test signal VON is maintained in the third test pad 156. Therefore, the test data voltage applied to the pixel electrodes connected to the even-numbered gate lines GL2, GL4,... It is not discharged. As a result, the test data voltage is maintained only at the pixel electrode connected to the even-numbered gate lines GL2, GL4,... GLn.

In this state, an error of a pixel corresponding to the even-numbered gate lines is checked.

Next, the process of checking the electrical operation state of the odd-numbered gate wirings is as follows.

In a third step, the first test signal VON is applied to the first test pad 152, the second test pad 154, and the third test pad 156. Of course, when a test signal is applied to the gate checker 150, it is natural that a test data voltage is also applied to the data lines.

As the first test signal VON is applied to the first test pad 152, the plurality of stages SRC1 and .. SRCn are driven to generate a gate-on voltage having a predetermined level to generate the gate lines GL1, Output to GL2, .., GLn). As a result, a gate-on voltage corresponding to the first test signal is applied to the gate lines GL1, GL2,..., GLn.

As the first test signal VON is applied to the second test pad 154, the control transistor TRc is turned on, and the pull-down transistors TR1, TR2,..., TRn are turned on. do. The pull-down transistors TR1, TR2,... TRn are applied to the gate lines GL1, GL2,... By the first test voltage VON applied to the second and third test pads 154, 156. The gate-on voltage applied to .GLn is maintained at the level of the first test signal VON.

Accordingly, the switching elements formed in the plurality of pixel regions are turned on to apply the test data voltage to the pixel electrode.

In a fourth step, in a state in which the first test signal VON is applied to the second test pad 154, the first test pad 152 and the third test pad 156 have a second test signal ( VOFF). The switching elements TFT connected to the even-numbered gate lines GL2, GL4,... GLn electrically connected to the third test pad 156 are turned off by the second test signal VOFF. . As the switching elements are turned off, the test data voltage applied to the pixel electrode connected to the even-numbered gate lines GL2, GL4,..., GLn is discharged.

Meanwhile, a first test signal VON is maintained on the second test pad 154. Therefore, test data applied to pixel electrodes connected to the odd-numbered gate lines GL1, GL3,..., GLn-1. The voltage is not discharged. As a result, the test data voltage is maintained only at the pixel electrode connected to the odd-numbered gate lines GL1, GL3, ... GLn-1.

In this state, an error of a pixel corresponding to the odd-numbered gate lines is checked.

A summary of the 2G array inspection process described above is shown in Table 1 below.

order 1st test pad 2nd test pad 3rd test pad Odd numbered GL Even GL One VON VON VON ACTIVE ACTIVE 2 VOFF VOFF VON INACTIVE ACTIVE 3 VON VON VON ACTIVE ACTIVE 4 VOFF VON VOFF ACTIVE INACTIVE

In this manner, the 2G array inspection process is performed on the gate lines connected to the gate driving circuit unit integrated on the display panel substrate.

As described above, according to the present invention, a 2G array inspection process may be facilitated with respect to a substrate including a gate driving circuit integrated on a display panel substrate.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (7)

A gate driving circuit unit electrically connected to one side of the plurality of gate lines to output a plurality of gate signals; A gate auxiliary circuit part electrically connected to the other sides of the gate lines to pull down the gate signal applied to the gate line; A first inspection unit applying a test signal to an input terminal of the gate driving circuit unit; A second inspection unit applying the test signal to an input terminal of the gate auxiliary circuit unit; And And a switching unit electrically connected to a final end of the gate auxiliary circuit unit to control an operation of the gate auxiliary circuit unit. The gate auxiliary circuit of claim 1, further comprising a plurality of pull-down transistors connected to the other side of the gate lines. And wherein the switching unit is diode-connected with a gate electrode and a drain electrode, and a source electrode is connected with a gate electrode of the last pull-down transistor among the pull-down transistors. The method of claim 2, wherein the second inspection unit, A first test pad unit applying the test signal to pull-down transistors connected to odd-numbered gate lines; And And a second test pad unit configured to apply the test signal to pull-down transistors connected to even-numbered gate lines. The display panel substrate of claim 2, wherein the gate electrode of the switching unit is electrically connected to any one of the first test pad unit and the second test pad unit. The method of claim 2, Activate the display area by applying a first test signal to the first inspection unit and the first and first inspection pads; And applying a second test signal to the first test unit and the first test pad to activate a display area corresponding to even-numbered gate lines of the display area. The method of claim 2, Activate the display area by applying a first test signal to the first inspection unit and the first and first inspection pads; And applying a second test signal to the first test unit and the second test pad to activate a display area corresponding to odd-numbered gate lines of the display area. Applying a gate on voltage to the entire gate lines to activate the entire display area; Applying a gate-off voltage to odd-numbered gate lines to activate a display area corresponding to an even-numbered line among the display areas, and maintaining the gate-on voltage at even-numbered gate lines; Applying a gate on voltage to the entire gate lines to activate the entire display area; And Applying a gate-off voltage to even-numbered gate lines to activate a display area corresponding to an odd-numbered line among the display areas, and maintaining the gate-on voltage at odd-numbered gate lines. The inspection method of the board | substrate for display panels.

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