KR20060083012A - Method for providing selective access to plural devices and apparatus thereof - Google Patents

Abstract

The present invention discloses a method and apparatus for providing selective access to a plurality of devices.

According to the present invention, a method of transferring a plurality of devices to each device when the processor selectively accesses them, storing physical addresses of accessible internal registers of the devices as first access information, and storing the internal devices. The registers store the logical address accessed by the processor as the second access information. The registers associate the logical address with the physical address for each device based on the stored first and second access information. If the value coincides with any one of the second access information, the device corresponding to the first access information is notified that the processor has access, and from the processor's point of view, each vendor-specific channel whose address can be changed or added during development. Change the corresponding address separately for IC and preamp IC According to the present invention, it is possible to connect to an actual address so that necessary information can be written or read by designating only a logical address determined for each IC without having to execute a necessary command while developing a HDD, which must be developed by using devices having the same function at the same time. In this field, the overall development period can be shortened, and intangible benefits are difficult to calculate.

Description

Method for providing selective access to plural devices and apparatus

FIG. 1 illustrates an example of a path for accessing a channel IC and a pre-amplifier used in the HDD development stage.

2 illustrates a flow of a method for providing selective access to a plurality of devices in accordance with the present invention.

3 is a block diagram illustrating a configuration of an apparatus and an operating environment for providing selective access to a plurality of devices according to the present invention.

4 is a view for comparing the result of using the access providing apparatus according to the present invention with the conventional case of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data storage device, and to a method and apparatus for providing selective access to a plurality of devices in a data storage device such as a hard disk drive.

For the operation of a hard disk drive (HDD), a pre-amp IC and a channel IC are used as one of components for processing a signal read from a media in which data is recorded. The detailed operation of these components allows all of them to operate under the control of firmware embedded in the HDD.

For each preamplifier or channel IC to be developed at the same time or at different time intervals, so as to minimize the risk in HDD development or to reduce the cost and to use the preamplifier and channel ICs manufactured by multiple vendors. It is common to develop.

However, because the specifications of the components of the preamplifier and channel IC provided by each vendor are not the same, the firmware of the HDD is prepared to process the code inside the firmware for each device so that it works properly even if the vendor of the device is changed. Should be. In other words, the firmware code must be written according to the specifications that are different for each manufacturer in order to ensure correct operation even when the manufacturer of the internal component devices used are different.

The firmware code may be complicated by the code structure of the firmware. Especially in the development stage, this complexity of firmware code can cause various side effects. The same task must be modified in small increments, repeating as many as the number of suppliers, and multiple trials and errors and bugs in the program are examples of side effects.

FIG. 1 illustrates an example of a path for accessing a channel IC and a pre-amplifier used in the HDD development stage. Reference numeral 100 is an example of instructions generated by a processor executing firmware, and reference numeral 110 is a resource that is accessed while executing such an instruction. The reference numeral 110 is registers of channel ICs and preamplifier ICs of vendors A, B, and C.

As can be seen from the figure, the processor executing the firmware needs to consider all cases of accessing the IC of each vendor in each instruction block when it is necessary to access a channel and a preamplifier for each instruction. As a result, the firmware code becomes complicated, a relatively high probability of bugs, and a problem of increasing trial and error in development.

The technical problem to be achieved by the present invention is to solve the above problems, even if there is a difference in the operating specifications of the component parts having the same function that can be accessed from the processor running the firmware, the same access can always be The present invention provides a method and apparatus for providing selective access to a plurality of devices.

According to the present invention for solving the above technical problem, a method for providing a selective access to a plurality of devices, in the method of delivering it to each device when the processor selectively access (access) a plurality of devices, ( a) storing the physical address of the accessible internal registers of the devices as first access information; (b) storing, as second access information, a logical address to which internal registers of the elements are accessed by the processor; (c) associating a logical address and a physical address for each device based on the first and second access information stored in steps (a) and (b); And (d) if the value of the address output by the processor for access matches any one of the second access information stored in step (b), access of the processor to an element corresponding to the first access information associated therewith is performed. Notifying that there is; characterized in that it comprises a.

In this case, it is preferable that the physical address of the register corresponding to the address value output from the processor is notified together while notifying the corresponding device in step (d).

According to another aspect of the present invention, there is provided an apparatus for providing selective access to a plurality of devices, the apparatus for delivering the same to each device when the processor selectively accesses a plurality of devices. A first storage unit which stores physical addresses of accessible internal registers of the devices as first access information; A second storage unit which stores, as second access information, a logical address to which internal registers of the elements are accessed by the processor; An information association unit for associating a logical address and a physical address for each device based on the stored first and second access information; And an element corresponding to the first access information associated with the processor when the address value obtained by decoding the address output by the processor for access in real time matches any one of the second access information stored in the second storage unit. And an address decoder that notifies that there is access.

At this time, it is preferable that the address decoder transmits the physical address value of the register corresponding to the address value output from the processor while notifying that the processor has access.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 illustrates a flow of a method for providing selective access to a plurality of devices in accordance with the present invention.

When a processor selectively accesses a plurality of devices, this method of transferring them to each device stores the physical address of the accessible internal registers of the devices as first access information (step 200), and the internal registers of the devices. They store the logical address accessed by the processor as the second access information (step 210), and associate the logical address and the physical address for each device based on the stored first and second access information (step 220). When the value of the address output by the processor for access matches any one of the second access information stored in step 210, the device corresponding to the first access information associated therewith is notified that the processor has access (step 230). .

In this case, it is preferable to notify the corresponding device in step 230 while also notifying the physical address of the register corresponding to the address value output from the processor.

3 is a block diagram illustrating a configuration of an apparatus and an operating environment for providing selective access to a plurality of devices according to the present invention.

When the processor selectively accesses a plurality of devices, the device, which delivers them to each device, may include a first storage unit configured to store physical addresses of accessible internal registers 340 of the devices as first access information. 300, a second storage unit 310 for storing internal addresses of the devices accessed by the processor as second access information, and each device based on the stored first and second access information. The information associated with the logical address and the physical address 320 and the address value obtained by decoding the address output by the processor 350 for access in real time to the second access information stored in the second storage 310 If it matches with any one of the elements corresponding to the first access information associated with the address decoder 330 for notifying that the access of the processor 350 is included.

As in the above method, it is preferable that the address decoder 330 notifies that the processor 350 has access and simultaneously transfers the physical address value of the register corresponding to the address value output from the processor 350.

Hereinafter, specific contents of the process of FIG. 2 with the configuration of FIG. 3 will be described.

The present invention operates in an environment in which the processor selectively accesses multiple devices having the same functionality as shown in FIG.

Elements accessible by the processor 350 are resources available to the processor. In order to access each device, the processor outputs the addresses given to the devices, or more specifically, the registers embedded in the devices, and writes the necessary values into the area corresponding to the address or reads the data recorded in the area. .

As described above, the first storage unit 300 stores the physical addresses of the internal registers of the respective devices that can be accessed by an external processor or a device having a master function. It is common for a device to have several registers, each of which is identified by its address value.

To control the device, the processor writes a specific value by addressing the corresponding register. Alternatively, the processor designates the address of the register corresponding to the state of the device and the result of the control, and reads the value recorded in the area designated by the address. This value is interpreted according to the specifications of the device to obtain the required result.

The first storage unit 300 stores physical addresses of accessible internal registers of such devices. This stored information is referred to as first access information to distinguish it.

Generally, as above, the processor directly accesses the physical address assigned to the registers of the elements. Then, as shown in FIG. 1, the code for driving the processor is changed whenever the target to which the processor needs to access or when the target address changes, so that the present invention provides a logical address to the target in order to improve this. When a channel IC of an A vendor is accessed, the physical address assigned to the IC is not accessed, but the logical address assigned to the IC is accessed.

As a specific example, a register that controls over shoot control (OSC) in a hard disk drive is taken as an example.

An example of a register map of each vendor-specific device for controlling the OSC is as follows.

<51XXD> Size 5bit, 02h, 0ch divided into two registers.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

R02h: 2 1 0

R0Ch: 4 3

<For TI18XX> Size 4bit and mapped to one register at 09h.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

R09h: 3 2 1 0

<In case of PA75XX> Size 5bit and mapped to 2 registers, 09h and 12h.

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

R09h: 3 2 1 0

R12h: 4

If each vendor-specific device is mapped as above, the conventional method performs option processing for a number of routines that need to control the OSC, and at the same time every additional vendor or register map changes, You should check the routine and make corrections.

Conventionally, a method of controlling devices having the same function as the OSC may be generated by the following code.

IdlePowerSave ()

{

.

.

#if PREAMP_CHIP == AG7550

d = (chnRdMv (0x09) & 0x0F) | ((chnRdMv (0x12) & 0x40) >> 2);

#elif PREAMP_CHIP == TI1860

d = (chnWrMv (PA_R09) &0x0F);

#else // PREAMP_CHIP == MV5114

d = ((chnWrMv (PA_R02) & 0xe0) >> 5) | ((chnWrMv (PA_R0C) & 0x30) >> 1);

#endif

.

.

}

In the same way as above, all relevant parts that need to process OSC should be processed by vendor.

Examples of cases improved according to the invention are as follows.

Assign logical address to each register as follows.

.EQU ZH_WC 0x21B

.EQU ZH_OSC 0x21C

.EQU ZH_RWOFFS 0x21D

Then, create a separate routine that manages logical addresses. The following is an example of a separate routine that manages logical addresses.

WORD RdLogReg (WORD r)

{

WORD * p;

WORD d;

. .

switch (r)

    {

case ZH_RC:

        d = ((chnRdMv (PA_R01) & 0xf8) >> 2) | ((chnRdMv (PA_R09) & 0x40) >> 6);

        break;

.

.

case ZH_OSC

#if PREAMP_CHIP == AG7550

            d = (chnRdMv (0x09) & 0x0F) | ((chnRdMv (0x12) & 0x40) >> 2);

#elif PREAMP_CHIP == TI1860

            d = (chnWrMv (PA_R09) &0x0F);

#else // PREAMP_CHIP == MV5114

d = ((chnWrMv (PA_R02) & 0xe0) >> 5) | ((chnWrMv (PA_R0C) & 0x30) >> 1);

#endif

        break;

return d;

}

Through the above configuration, even if there is a change in the device to be controlled for each vendor or a vendor of a device having the same function is added, only the routine of the logical address processing part as in the above example is corrected or supplemented. Many other routines that call this routine can be used without modification. This also reduces the overall code size that you control.

The following is an example of calling an improved processing routine according to the present invention.

IdlePowerSave ()

{

.

.

           d = RdLogReg (ZH_OSC);

.

}

The above examples are examples of implementing the present invention through a programmatic software method. In addition, this can be done by hardware configuration using means such as PLD or FPGA.

The second storage unit 310 stores the logical address assigned to each of these elements and accessed by the processor as the second access information (step 210).

The information association unit 320 associates the logical address and the physical address for each device based on the stored first and second access information as described above, for each register embedded in each device (step 220).

In order for the processor 350 to access an external resource, a signal of access start (or transmission start), a signal of whether this access is read or write, and a target address line signal must be driven at least.

The address decoder 330 monitors a signal output from such a processor in real time. At the same time, it decodes the address signals output by the processor and monitors whether the register 340 for each device is accessed. When a logical address value corresponding to each device register is detected, this is a value related to information stored in the second storage unit 310.

The address decoder 330 identifies the first access information associated with the second access information, which is the logical address, by referring to the result of the information association unit 320, and transmits the first access information to the device corresponding to the first access information from the processor. Notify that there is access (step 230) so that a response is passed from the device to the processor.

In more detail, the start access signal and the read or write signal to the corresponding device are transferred from the processor 350 to the corresponding device directly or through a buffer or through the address decoder unit 330 according to the implementation. The signal indicating that the register is selected is transmitted to another device or address decoder 330, which is not shown in the figure, by decoding the address signal of the processor 350 to the device, and the address decoder unit 330 is physically separated from the logical address of the processor. Create an address and pass it to the appropriate device. By the combination of signals transmitted through the above process, the corresponding device knows that it is selected by the processor.

In the above example, if the operation of the processor is a write operation, after outputting the address signal, the data value will be transferred to the device at the same time as the address or after a predetermined time. The value is transferred to the processor 350 through the data line. In this case, signals and data values for data transmission output from the corresponding device may vary depending on the implementation, but will be directly transmitted to the processor 350 directly or through a functional unit such as a buffer.

Through the above process, the device according to the present invention operates between the processor 350 and the registers 340 for each device so that the processor can selectively access the devices that perform the same operation.

4 is a view for comparing the result of using the access providing apparatus according to the present invention with the conventional case of FIG.

Reference numeral 100 in FIG. 4 is an example of instructions generated by a processor executing firmware, and reference numeral 110 is a resource that is accessed while executing such an instruction. The registers are the same as in FIG.

However, in FIG. 4, the processor providing the access 400 according to the present invention in the middle and executing the instructions 100, the channel IC and the preamp IC for each vendor whose address may be changed or added during the development process. Without having to execute the necessary commands while changing the respective addresses separately, and by specifying only logical addresses determined for each IC, the access providing apparatus 400 according to the present invention can connect to the corresponding actual addresses to write or read necessary information. do.

The result is that you don't have to change the processor's executable code, especially during development, which simplifies the code's content and reduces bugs caused by subsequent changes.

Those skilled in the art will appreciate that the present invention can be implemented in a modified form without departing from the essential features of the present invention. Therefore, the disclosed embodiments should be considered in descriptive sense only and not for purposes of limitation. Examples included in the above description are introduced for the understanding of the present invention, and these examples do not limit the spirit and scope of the present invention. It will be apparent to those skilled in the art that various embodiments in accordance with the present invention in addition to the above examples are possible. The scope of the present invention is shown not in the above description but in the claims, and all differences within the scope will be construed as being included in the present invention.

In addition, it can be easily understood by those skilled in the art that each of the above steps according to the present invention can be variously implemented in software or hardware using a general programming technique.

And some steps of the invention may also be embodied as computer readable code on a computer readable recording medium. The computer-readable recording medium includes all kinds of recording devices in which data that can be read by a computer system is stored.

 According to the present invention, a method of transferring a plurality of devices to each device when the processor selectively accesses them, storing physical addresses of accessible internal registers of the devices as first access information, and storing the internal devices. The registers store the logical address accessed by the processor as the second access information. The registers associate the logical address with the physical address for each device based on the stored first and second access information. If the value coincides with any one of the second access information, the device corresponding to the first access information is notified that the processor has access, and from the processor's point of view, each vendor-specific channel whose address can be changed or added during development. Change the corresponding address separately for IC and preamp IC By specifying only a logical address determined for each IC without having to execute necessary instructions, it is possible to write or read necessary information by connecting to an actual address according to the present invention, and in particular, there is no need to change the execution code of the processor during development. As a result, the contents of the code can be simplified, and as a result, the occurrence of bugs due to continuous changes can be reduced, so that the entire development period can be shortened in fields such as HDD development, which must be developed using the same device at the same time. You can see intangible benefits.

Claims (4)

In a method for transferring a plurality of devices to each device when the processor selectively access (access), (a) storing the physical address of the accessible internal registers of the devices as first access information; (b) storing, as second access information, a logical address to which internal registers of the elements are accessed by the processor; (c) associating a logical address and a physical address for each device based on the first and second access information stored in steps (a) and (b); And (d) If the value of the address output by the processor for access matches any one of the second access information stored in step (b), there is an access of the processor as an element corresponding to the first access information associated therewith. Notifying; providing selective access to the plurality of devices. The method of claim 1, And (d) notifying the corresponding device while notifying the corresponding device, the physical address of the register corresponding to the address value output from the processor. In the device for passing a plurality of devices to each device when the processor (access) selectively (access), A first storage unit which stores physical addresses of accessible internal registers of the devices as first access information; A second storage unit which stores, as second access information, a logical address to which internal registers of the elements are accessed by the processor; An information association unit for associating a logical address and a physical address for each device based on the stored first and second access information; And When the address value obtained by decoding the address output by the processor for access in real time coincides with any one of the second access information stored in the second storage unit, the processor accesses the device corresponding to the first access information associated with the processor. And an address decoder unit for notifying of the presence of a device. The method of claim 3, And the address decoder unit notifies that the processor has access and simultaneously transfers a physical address value of a register corresponding to the address value output from the processor.

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