EP0446250A1 - Control for a rotating media storage system - Google Patents
Control for a rotating media storage systemInfo
- Publication number
- EP0446250A1 EP0446250A1 EP89913194A EP89913194A EP0446250A1 EP 0446250 A1 EP0446250 A1 EP 0446250A1 EP 89913194 A EP89913194 A EP 89913194A EP 89913194 A EP89913194 A EP 89913194A EP 0446250 A1 EP0446250 A1 EP 0446250A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- control
- control means
- program
- memory
- control program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
Definitions
- This invention relates to the field of disk drives and to a method of providing onboard control to a disk drive system.
- Many computer systems utilize rotating media storage devices as a means of providing mass storage for data and other information.
- These storage devices may employ magnetic, optical, magneto-optical or other types of media for information storage.
- the storage device typically communicates with the host computer system through an interface, such as a small computer system interface (SCSI), ST-506 (J.D. check number) or ESDI.
- SCSI small computer system interface
- ST-506 J.D. check number
- ESDI ESDI
- control or storage device functions and communications were handled by the host computer. This placed additional burden on the host computer system and limited performance of the storage devices.
- One method of improving a performance of the storage device is to make it a "smart" device.
- processing means were provided on the storage device itself to handle certain control functions and communication with the host computer system.
- prior art storage devices may include a processor on a control board for controlling certain functions of the operation of the storage device. This processor is controlled by a program (firmware) typically stored in read only memory, such as a ROM, EPROM or EEPROM.
- a disk type storage device such as a Winchester type hard disk drive which utilizes such onboard control
- a control program be prepared and debugged to govern operations of the processor.
- An EPROM is then manufactured to store the control program on the control board or provide the programming to the processor when the storage device is active. This control program is burned into the EPROM and the EPROM is then soldered onto a control board in the storage device.
- One disadvantage of this prior art method of manufacturing disk drives is the fact that the EPROM must be removed from the board to correct any errors or mistakes in the control program. Additionally, when running emulators (testers) on the storage device, it is necessary to replace the control program with an emulation program, again requiring the opening of the storage device.
- storage devices are original equipment manufactured devices (OEM) which are tailored to each purchaser's particular package, therefore, for different purchasers , different control programs must be prepared, debugged and embedded in an EPROM before inserting onto a control board in a disk drive.
- OEM original equipment manufactured devices
- One method of reducing the physical size of the storage device is to reduce the size of the control board within the storage device. This may offer a lower profile storage device, or permit additional area to be dedicated to storage.
- One method of reducing the size of the control board is to pack individual components on the control board more tightly, or to condense functions and combine functions into a single component.
- there are methods of mounting components on a control board which reduce the height of the control board and thereby provide space advantages. For example, by using a "surface mount" technology, a lower profile control board may be achieved.
- probes are coupled to the processor on the storage device and coupled to emulation hardware so that single step, break point and disassemble instructions can be utilized. Because probes cannot be attached to surface mount technology, it has not been possible in these prior art storage devices to utilize surface mounting.
- One approach to the use of surface mount technology is to provide an onboard emulator hardwired to the processor to single step and disassemble instructions. However, this takes up valuable board real estate and adds to the expense and complexity of the storage device.
- Interface control includes communication with the host computer through the particular type of communication interface used in the computer system. For example, if a SCSI interface is used, the processor monitor the SCSI bus and looks for communication from the host computer system.
- Device operations entails management of the storage device itself such as rotation speed for rotating media, system, and read/ write head position, etc.
- the present invention is directed to a control system for a rotating media storage device.
- the rotating media storage device includes a control board having a ROM to store a basic power up control program, one or more processing means for control of the storage device and communication between the storage device and the host computer and a read/write memory means such as a RAM.
- the basic code in ROM initializes the control system, activates the rotating storage media, and accesses a control code stored on the storage media.
- the control code is transferred to the onboard RAM through a suitable interface, such as a SCSI connection.
- the control program of the storage device then executes from the RAM based control program. This eliminates the need for a "firm ware" based control program realized in an onboard EPROM. This permits changing and updating of the control program simply by writing to disk and transferring the new program into the RAM for execution, h addition, it is not necessary to power down the drive in order to change the control program.
- the control system of the present invention includes a dual processor architecture for distributed control of storage device operations.
- a master processor controls and monitor communication with a host computer system through a communications interface.
- the interface comprises a SCSI bus.
- a second "slave" processor controls device operations such as rotation speed, read/ write head position, and seek operations.
- the dual processor scheme of the present invention utilizes commercial processing units. Communication between the processors is accomplished on a microwire utilizing a novel communications protocol which permits high speed processing of individual distributed functions and high speed communication between the processors.
- the present invention provides a serial port coupled to the processors and used to implement a test environment with a host computer.
- Emulation code can be downloaded to the storage device to the serial port and stored in the RAM memory. This provides the ability to single step through programs and set break points, and disassemble instructions of the microprocessor while it is running out of the RAM memory. Because the microprocessor is running out of the RAM there is no need for external hardware to provide these break points and disassemble instructions.
- the use of a serial port and novel testing protocol permits the "daisy chaining" of a plurality of storage devices for testing and emulation with a single host computer.
- Figure 1 is a block diagram of a prior art storage device.
- FIG. 2 is a block diagram of the present invention.
- Figure 3 is a block diagram of the system memory map of the present invention.
- FIG. 4 is a block diagram of the master and slave processor of the present invention.
- Figure 5 is a timing diagram illustrating a normal command sequence of the present invention.
- Figure 6 is a timing diagram illustrating command with status return of the present invention.
- Figure 7 is a timing diagram illustrating an error handler of the present invention.
- Figure 8 is a block diagram illustrating a test configuration of the preferred embodiment of the present invention. DETAILED DESCRIPTION OF THE PRESENT INVENTION
- the present invention is directed to a control system having method and apparatus for controlling the operation of a storage device, communication between the storage device and a host computer system, provision of control programming, and distribution of control functions.
- the following description of the present invention is made in connection with a Winchester type hard disk drive storage device.
- the disk drive includes one or more rotating storage disks, a read/write head for reading and writing information on storage tracks On a disk surface, a control board which includes architecture for controlling operation of the disk drive, and an interface for communication between the disk drive and a host computer.
- the present invention is described in connection with a hard disk drive system, it would be apparent, to one skilled in the art, that the present invention has equal application to any type of mass storage device which requires communication to a host system and control of storage device capabilities.
- the present invention is not limited to rotating media type storage devices or magnetic media devices, but has application to optical, tape and other storage devices as well.
- FIG. 1 illustrates a block diagram of a prior art control system of a disk drive.
- the control board 12 is coupled to the disk drive 10 through 5 control lines 17 and 18.
- the control for the disk drive 10 is provided by processor 16 which is coupled to the disk through bus 18.
- Programming for the processor 16 is contained in EPROM 15 coupled to processor 16 through line 21.
- the processor 16 is coupled, through line 19, to a small computer systems interface (SCSI) bus 14.
- the SCSI bus 14 is coupled to a RAM buffer 10 13, through line 22.
- the RAM buffer is coupled to disk 10, through input/ output line 17.
- the disk 11 includes a user area 32 and a reserved special area (SA) 23.
- SA special area
- a "soft loading" technique is utilized to provide a control program to an onboard processor-
- the control program is stored on a hard disk in a restricted area of the disk surface, not accessible by the user.
- a control program kernel is stored in a small ROM on the control board to handle startup.
- the kernel drives the actuator to position the read/write heads over the control program location on the disk surface.
- the control program is then downloaded into a RAM on the control board.
- the control program kernel is used to verify the control program downloading and then operation of the processor is handed over to the stored control program in RAM.
- control board of the present invention utilizes a serial port coupled to the processing unit of the drive.
- the serial port permits the downloading of new control programs, emulation code and testing procedures.
- Emulation and testing programs can replace the control program in the RAM, permitting the use of programs to set break points, disassemble instructions and single step through disk processes.
- a special protocol allows a plurality of disk drives to 12 be daisy chained together for testing purposes with each disk drive assigned a slot on the chain so that test commands and responses can be differentiated between the plurality of drives. This improves the efficiency of manufacturer of drives since only a single host computer is required for a plurality (e.g. up to 254) drives.
- the preferred embodiment of the present invention utilizes distributed control by dividing a master processor for SCSI interface control and a slave processor for disk operation control.
- the slave processor monitors rotation speed, head position and seek operations.
- the master processor monitors the SCSI bus and controls communicating between the drive and host computer.
- the master and slave processor in the preferred embodiment of the present invention are National Semiconductor HPC 46083 microcontrollors running at 24 megahertz.
- the master processor wants to communicate with the slave processor, the master processor outputs a ready signal to the slave processor.
- the slave processor initializes and sends back a ready signal to the master processor.
- the master processor then sends a command byte to the slave processor and the slave processor responds with a status signal. Because of the distributed control functions of the master and slave processor, seeks can be performed more quickly than in prior art devices. Because the slave processor is constantly monitoring the head position and speed, when a seek command is received from the master processor, the seek can be implemented immediately. At the same time, the master processor can be communicating with the host computer, either obtaining information for the next seek or providing status or other information to the host computer.
- the control board 12 of the present invention includes two processors. Master processor 24 and slave processor 25 are both utilized to provide control over different aspects of the disk drive function. Master processor 24 is coupled to the disk drive through a SCSI bus and RAM buffer interface. The master processor 24 is coupled on line 29 to the SCSI bus 14. The SCSI bus 14 is coupled on line 22 to RAM buffer 13 and in turn to input output line 17. The master processor controls the SCSI interface and communication between the host computer system and the disk drive.
- the slave processor 25 is coupled to the disk drive 10 through connection 18 through line 18.
- the control board 12 includes a serial port 27 coupled to master processor 24 through line 30.
- a boot ROM 28 is coupled to slave processor 25 through line 33.
- the master processor is also coupled on line 29 to RAM 26.
- the slave processor monitors disk drive status and operations, such as rotation speed, head position and execution or seek commands.
- a serial port 27 is coupled to the master processor 24 through line 30.
- the ROM boot 28 provides basic code in order to initialize the SCSI interface, spin up the disk, read the control program into the RAM space and execute from the RAM based control program.
- the ROM boot 28 consists of the following code in address range FFFF-EOOO:
- Microwire interface (communications with servo)
- the program code loaded from the special area 23 is mapped to the following areas of the RAM 26 as illustrated in Figure 3.
- the soft boot label area contains revision, documentation numbers and other specific information about soft boot firmware.
- the interrupt vector table area is for all interrupts other than reset.
- the JSRP vector table area is for the emulation code interrupt table that is in use when emulation code is invoked.
- the "real" firmware supports all SCSI commands, all error-handling and normal disk operations.
- the monitor area is for diagnostic capabilities of customized control programs, and debugging the controller.
- the soft boot area 23 on the disk is first loaded with a label.
- the label indicates validity, has numbers for revision and documentation and a production ID code. Immediately following this label is the code.
- the label and code are written in three separate areas within the soft boot area.
- the soft boot label format includes the 16 bytes of signature, revision number (16 bytes), documentation number (16 bytes), production ID number (16 bytes) and 122 to 326 bytes for an ASCI string for right notices, ownership notices, etc.
- the NMI interrupt located in the 8K ROM initializes the processors UART port and allow the download of the rest of the emulation code. This will load into the monitor area of the 32K RAM via serial port 27 on PC to the processors UART port and then start the eulation code functions.
- the preferred embodiment of the present invention includes diagnostics on powerup which consist of initialization of the processors, SCSI interface chip, and microwire interface.
- the memory tests are basic reads/write O's and l's to SCSI memory and to the 32K RAM.
- To test the microwire interface there is a diagnostic command sent to the servo and echoed back.
- the commands are as follows:
- Read defect list 37 Read the P list defects
- these are the only commands the controller accepts after a power on or reset until the code is loaded from the soft boot area if valid. If the soft boot area is not valid, the SCSI status byte will indicate a check condition.
- the OP code assignments are given by way of example of the preferred embodiment only. The OP code assignments can be shifted without departing from the scope of the present invention.
- the host computer system issues a request sense command
- the extended sense data returned will have a hex 2B in the additional sense byte indicating SBNV (soft boot not valid).
- the install command takes raw data from the RAM area starting with the label and loads all 32K bytes to the disk in the soft boot save area. Once loaded the disk will switch heads and start the same process over again.
- Download command uses Intel hex format in the preferred embodiment of the present invention.
- the command strips the information bytes and loads 32K RAM with the data.
- the check sum is calculated and then checked with the checks sum bytes given by the Intel hex format to insure good data.
- the check sum is calculated by adding all bytes except begging of line marker, then taking the 2's complement of the sum.
- Upload command takes the raw data in 32K RAM and inserts the control fields for the intel hex format.
- the areas uploaded will be soft boot label and interrupt vector table, address range 6000-6220, and firmware, address range 7000-BFFF.
- SA command will format only the area on the disk which has the flaw map, soft boot label and firmware. It uses the P list to support some basic flaw management for defective areas within this special area 23. This area is formatted to 512 bytes per sector.
- Read defect list command transfers the P list in "bytes from index" format that was prerecorded on the disk from the factory to the host. Attempting to read the G-list or another defect list format causes an error setting a check condition status. This sets a sense key of "5" and the additional sense code to "24" (hex).
- the interrupt vectors are fixed locations in the boot ROM 28 .
- the vectors point to locations in the 32K RAM area 26. Since RAM comes up in an unknown state, the vectors must be initialized by whoever is going to use these vectors.
- the ROM boot code sets the NMI interrupt vector to point into 8K ROM space to invoke the emulation code.
- the emulation code must initialize it's vectors including NMI to point to its own routines for handling interrupts.
- the 32K RAM based firmware must load these vectors to allow normal disk operations.
- the preferred embodiment of the present invention utilizes National Semiconductor HPC 46083 microcontrollers. However, any suitable 5 microcontroller can be utilized in the present invention.
- the connection of the master and slave processors is illustrated in figure 4.
- Voltage VCC is coupled through resistor Rl to master processor 24 and slave processor 25 at node 32. Number 32 is also coupled through
- Node 32 is coupled to the master and slate processors at the reset inputs.
- the master processor 24 sends commands to the slave processor 25 and the slave processor 25 provides status to the master processor 24.
- the master processor 24 signals the slave processor 25 that a command is to be sent by setting line 37 high.
- SCMD Serial Bus Control
- Line 33 is coupled to the processor at pin PI and to the master processor at pin D6.
- a clock signal SCLK is provided to the master and slave processor on line 36 at pin B6.
- the slave processor 25 After the command is received, if a status signal is required, the slave processor 25 outputs a status signal SSTAT on line 38 to the master processor 24. The signal is provided at pin B5 of slave processor
- Data signal SDATA is provided on line 35 from pin SI of slave processor 25 to pin B5 of master processor 24.
- the communication between processors is performed when the master processor requests information, seeks to cylinder, diagnostics, spins up/ down the drive, etc. to the slave processor.
- the communication link is performed with the microwire interface on each processor.
- the master processor is the master microwire, and the servo processor is the slave. All commands in the preferred embodiment are 16 bits in length, and all returned status is 16 bits. Status is only returned on the master processor sending a status command. The most significant bit of the status/command word is always sent first, the least significant bit (0 placement bit) is sent last.
- the microwire has an eight bit serial shift register, all commands and status are 16 bits.
- the slave processor asserts SRDY active high when it is ready to accept a command. SRDY asserts low after the first command byte has been received. The master processor then sends the final command byte. When SRDY is high, the operation is complete (seek complete or status read). During a status operation, the master processor reads the MSB (byte) or first byte of status, the slave processor asserts SRDY low and the second byte is read by the master processor. SRDY returns high after the last bit is read.
- the master processor monitors an asynchronous SERR set high.
- SERR high indicates to the master processor that status should be performed to determine a fault condition.
- SCMD drops low and the master processor sends a command to receive status. After the last byte of status is sent from the servo processor, SERR returns low. SERR is asserted high for any fault condition that the master processor should be aware of.
- the microwire I/F is used to communicate between the master processor and the slave processor, thus we have the Master (SCSI) and the Slave (SERVO).
- the Slave Upon reset condition, Power up or otherwise, the Slave waits for the Master to initialize first. This is signaled to the Slave by way of SCMD line going high Then the Slave can be initialized. The last thing the Slave does before it leaves its initialization is to clear the uWIREDONE flag, by writing to the SIO register. For a transfer:
- Slave waits for SCMD to go low. Indicating master wants to send a command. Master waits for SRDY to go hi. Set by slave when he's ready. Master sends first byte...and wait for uWIREDONE flag to be set. Slave waits for uWIREDONE flag to be set then reads the first byte from SIO. Slave resets uWIREDONE flag by writing to SIO reg. Slave sets SRDY low for second byte. Master waits for SRDY to go low.
- Master sends the second byte...and waits for uWIREDONE flag to be set. Slave waits for uWIREDONE flag to be set then reads the 2nd byte from SIO. Slave then resets uWIREDONE flag by writing to SIO reg.
- a command sequence is illustrated in Figure 5.
- the master processor pulls SCMD line low as shown at falling edge 50 to signal the slave processor that it is ready to send a command.
- the signal SRDY is set high by the slave processor as shown at rising edge 40 to indicate that slave processor is ready to receive the command.
- the first eight bits of the command are sent as shown by clock signal SCLK.
- the slave processor sets SRDY low at falling edge 47 to indicate that the slave is ready to receive the second byte of the command signal (SCLK) and the command signwal SCMD goes high at rising edge 39 to indicate that the master is done sending the command. If no error is detected, the error signal SERR stays low.
- a command with status return is illustrated.
- the master processor pulls SCMD line low as shown at falling edge 50 to signal the slave processor that it is ready to send a command.
- Signal SRDY is set high at rising edge 40 by the slave processor to indicate to the master that a command may be sent.
- the command sent, command 60 of SCLK signals a status request command.
- the SRDY signal is pulled low at falling edge 41 and SCMND is set high at rising edge 51.
- the end of status command, command 00 of SCLK is transmitted and the SRDY signal is set high to flag the coming status information.
- the status, commands XX on SCLK, is provided to the master processor in two parts.
- the first byte is sent when SRDY is high. After SRDY is set low at falling edge 43 the second status byte is transmitted and SRDY is pulled high at rising edge 44 to signal the end of status
- FIG. 7 illustrates error handling in the protocol of the present invention.
- SCMD is set low at edge 50 in preparation of sending a command.
- SERR is set high by the slave at rising edge 52.
- the slave and master repeat the process described with respect to Figure 6 in that the master asks for status regarding the error. Error status is sent in two bytes on high and low phases of the SRDY line.
- the burn-in environment discussed in this specification makes use of he onboard microprocessor and serial interface of the disk drive to achieve a low cost test environment that has a high degree of automation and data collection.
- the diskdrive control program or the preferred embodiment of the present invention supports a simple LAN (local area network) environment.
- This support can be in the form as a special burn-in version of the firmware that contains the LAN support and several canned diagnostic routines that are referenced via the LAN by the master computer.
- Address 8 Bit Address Field supports 256 addresses, with address
- Checksum 8 Bit Checksum Field - checksum modulus 256 checksum code This command format allows a single host AT to address one or all of the drives under test, and allows the drive under test to send response back to the host AT (address OOh).
- Packets can be sent in as small as four bytes (address, count, command, and checksum) for single command operations (poll, reset, power-on, etc.), and for more complex command strings (if command chaining is included, command length can be near infinite.
- the checksum is reduced to 8 bits. The chances that a bad checksum not being detected are remote.
- a single host computer 50 is utilized to control testing for a plurality of drives P1-P(N).
- the drives are coupled to the host computer serially in a daisy chain configuration through the serial ports of each drive.
- the serial output of the host computer 50 is coupled on line 51 to the serial input of drive PI.
- the serial output of drive PI is coupled on line 52 to the serial input of drive P2.
- the serial output of drive P2 is coupled on line 53 to the input of the next drive.
- the output of drive P(N-1) is coupled on line 54 to the serial input of drive P(N).
- the output of drive P(N) is coupled on line 55 to the input of host computer 50.
- the Host AT (HAT) sends a NOP over the STP (Serial Test Port), and expects to receive command back. This verifies the serial line is a closed circuit, and power is available to all connected drives.
- the HAT sends a Logical Drive Assignment (LAD) to the first drive, address Olh..
- LAD Logical Drive Assignment
- the first drive takes the packet, saves the logical drive address (Olh), increments the address field to 02h, and sends the packet to the next drive.
- Olh logical drive address
- Each drive will accept the LAD command, save the logical address, increment, and resend packet.
- the HAT receives the Command Packet (CP) and keep the CP address (decrement) for the number of drives under test (DUT).
- CP Command Packet
- DUT drives under test
- the HAT POLLS each DUT for status, verifying each DUT responds to its logical address.
- the DUT responds to address OOh (HAT) with a health value (obtained from a basic ROM diagnostic to check RAM, registers, etc.) 6)
- HAT sequences up each DUT, giving a proper interval for powering-up, then powering-up next logical DUT, then POLL for status of the previous DUT.
- the HAT requests drive information from the DUT during the seek test.
- the DUT provides the serial number, bad track table, an current status to the host.
- the HAT sends a Download Test Command all drives.
- Each DUT reads the diagnostic programs from the disk to RAM and await next command from the HAT.
- the HAT sends a Start Test Command (or a macro test) to start the testing.
- Each drive maintains a Bad Track Table (BTT) in RAM, updating the BTT as required.
- BTT Bad Track Table
- the HAT requests, compiles, and prints drive status for all DUT's. 0
- This data includes the bad track table, test parameters, number of soft/hard errors detected, and a pass or fail statement. All of this data is available on the DUT's reserved data areas
- a control system and apparatus for a disk drive storage system which allows soft loading of control programming, testing of a plurality of disk drives with a single host computer, distributed control of drive operations and effecient communication between two onboard processors.
Abstract
La présente invention se rapporte à un système de commande pour dispositifs de stockage sur supports rotatifs. Le dispositif de stockage sur supports rotatifs comprend une carte de commande avec mémoire morte (ROM) destinée à stocker un programme de commande de mise sous tension de base, un ou plusieurs organes processeurs servant à commander le dispositif de stockage et la communication entre le dispositif de stockage et l'ordinateur hôte, ainsi qu'un organe à mémoire de lecture/d'écriture telle qu'une mémoire à accès sélectif (RAM). Lors de la mise sous tension du dispositif de stockage, le code de base contenu dans la mémoire ROM initialise le système de commande, active les supports de stockage rotatifs et permet l'accès à un code de commande stocké sur les supports de stockage. On obtient ainsi un changement et une mise à jour du programme de commande simplement par écriture sur disque et par transfert du nouveau programme dans la mémoire RAM en vue de son exécution. En outre, il n'est pas nécessaire de débrancher l'unité pour changer le programme de commande. Le système de commande de la présente invention comprend une architecture à double processeur permettant une commande répartie des opérations du dispositif de stockage. La communication entre les processeurs s'effectue sur un microfil utilisant un nouveau protocole de communications qui permet un traitement haute vitesse des fonctions réparties individuelles et une communication haute vitesse entre les processeurs. La présente invention décrit une porte d'accès sérielle couplée aux processeurs et utilisée pour mettre en application un contexte d'essai au moyen d'un ordinateur hôte. Un code d'émulation peut être transféré par téléchargement dans le dispositif de stockage par la porte d'accès sérielle et stocké dans la mémoire RAM.The present invention relates to a control system for storage devices on rotary supports. The storage device on rotary supports comprises a control card with read only memory (ROM) intended for storing a basic power-up control program, one or more processor members serving to control the storage device and the communication between the device. and the host computer, as well as a read / write memory device such as a random access memory (RAM). When the storage device is powered up, the basic code contained in the ROM memory initializes the control system, activates the rotary storage media and allows access to a control code stored on the storage media. A change and an update of the control program are thus obtained simply by writing to disk and by transferring the new program to the RAM memory for execution. In addition, it is not necessary to unplug the unit to change the control program. The control system of the present invention includes a dual processor architecture for distributed control of the operations of the storage device. Communication between processors takes place on a microfilm using a new communications protocol which allows high speed processing of individual distributed functions and high speed communication between processors. The present invention describes a serial access door coupled to processors and used to implement a test context using a host computer. An emulation code can be transferred by downloading to the storage device through the serial access door and stored in the RAM memory.
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US26958688A | 1988-11-10 | 1988-11-10 | |
US269586 | 1988-11-10 |
Publications (2)
Publication Number | Publication Date |
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EP0446250A1 true EP0446250A1 (en) | 1991-09-18 |
EP0446250A4 EP0446250A4 (en) | 1995-02-22 |
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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EP89913194A Withdrawn EP0446250A4 (en) | 1988-11-10 | 1989-11-07 | Control for a rotating media storage system |
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EP (1) | EP0446250A4 (en) |
JP (1) | JPH04502974A (en) |
AU (1) | AU4641689A (en) |
WO (1) | WO1990005339A1 (en) |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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-
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- 1989-11-07 JP JP2500395A patent/JPH04502974A/en active Pending
- 1989-11-07 EP EP89913194A patent/EP0446250A4/en not_active Withdrawn
- 1989-11-07 AU AU46416/89A patent/AU4641689A/en not_active Abandoned
- 1989-11-07 WO PCT/US1989/005033 patent/WO1990005339A1/en not_active Application Discontinuation
Non-Patent Citations (2)
Title |
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No further relevant documents disclosed * |
See also references of WO9005339A1 * |
Also Published As
Publication number | Publication date |
---|---|
AU4641689A (en) | 1990-05-28 |
EP0446250A4 (en) | 1995-02-22 |
JPH04502974A (en) | 1992-05-28 |
WO1990005339A1 (en) | 1990-05-17 |
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