JPH04502974A - Rotating media storage control - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] "Controlling Rotating Media Storage Devices" Background of the invention 1. Field of the invention The present invention is in the field of disk drives and methods for onboarding disk drives. It is about law.

2. Many comviator devices are designed to store data and other information within 6m. As a means for this purpose, a rotating media storage device is utilized. Those storage devices store information Magnetic, optical, magneto-optical or other types of media can be employed for the purpose.

The memory H1l is a small computer Hr11 interface (SC5D, 5T- 506, (J, D, check number) or through an interface such as ESDL. and typically communicate with a host computer device. This is the host computer Even more i for H! It imposed a load and limited the performance of memory am. Improve storage performance One way to make it “nifty”! ? It is to make it IFF. good In other words, it is written to handle certain control functions and communication with the host computer. A processing means is provided in the storage device itself. Therefore, traditional storage devices are A processor may be included in the control panel to coordinate certain functions. process The processor is typically a read-only memory such as ROM, EFROM, or EEFROM. It is controlled by a program (firmware) stored in the system.

Winchester-type hard disk drives that utilize such onboard controls The manufacture of disk-type storage devices such as disk drives is controlled to control the operation of processors. It is necessary to create and debug a control program. Then fr! 4 prog Store RAM in lilIgIai or program when storage is active. To program the processor, an EFROM is built. This ** professional The program is burned into an EFROM, and then the EFROM is may be soldered to. One disadvantage of this traditional method of making disk drives In order to correct the error in the control program, the EFROM must be removed from the board. Also, do not run an emulator (tester) on the storage device. When using the control program, it is necessary to change the control program to an electric or range program. There is a need to open the storage device again.

Typically, the storage device is an original equipment manufacturer tailored to each manufacturer's specific package. Since it is an OEM device provided by Create and debug different control programs before inserting them into the EPRO control panel. Must be embedded into M. Difficulty in exchanging control programs and due to the expense and time required to update and replace the I control program. , to minimize the size of the sting program and, therefore, to minimize the memory storage options. There is an incentive to minimize onboard control sophistication and intelligence. That is, The fewer lines of code in a control program, the less buggy the program will be. There will be fewer things to do. However, the traditional method of realizing control programs is Nature limits the size and effectiveness of programs.

You may want to reduce the dimensions of the physical package that makes up the storage device. It is also desirable to improve functionality, features, and capacity. Reduce physical size of memory HH One way to reduce this is to reduce the size of fHrMlli in the storage device. be.

This reduces the profile of the storage device or takes up additional area for storage. I can do it. One way to reduce the size of a control panel is to separate individual components from the board. high-density packaging, or condensing functions and combining them into one component. This is Saseko Shichi. Furthermore, the height of the control panel can be lowered to save space. Bringing control over parts gIJ! There is a way to attach it to i. For example, “surface-mounted” By using this technique, a lower profile control alt11 can be obtained. death However, one drawback of surface mounting technology for control panels for storage devices is that surface mounting This is due to the fact that the attached device cannot be easily removed from the panel. Furthermore, it is equipped with connecting legs. surface-mounted equipment without running the high risk of disconnecting from the It is not possible to attach a Control board processor can be removed If the control program cannot be replaced, the entire board must be replaced. If the probe cannot be attached to the processor, testing and emulation Unable to run.

In the conventional technology, one host computer is required for each storage device to test the storage device. Requires Vieta. Probe storage HI2 coupled to processor, single instruction , the emulation scene hardware to take advantage of breakpoint and decomposition instructions. It was not possible to use surface mounting in those conventional storage devices.

One approach to surface-mount technology is to use an The objective is to provide an onboard emulator for single-step instructions and decomposition instructions. death However, this takes up a lot of board space, reduces storage costs, and Storage '4: Make it complicated.

In storage devices in which the processor is connected to II'C, the control It is desirable to have as many processor handles as there are functions; free the computer from those functions and improve the operation of the host vtlIf. on Allocated to the board processor and conventional storage (do+t4m, i.e. There are two main areas: interface control operations and device operations. For example, 5 If a C5I interface is used, the processor uses its 5C3I bus. monitors communications from the host computer device. The operation of the device is based on the media, Rotation speed, read/write head position, etc. to rotate the system This involves management of the memory 1JII itself.

To keep storage costs low and gain size advantages, commercially available Off-the-shelf processing units are the standard on-board control means for storage systems. used stylistically. Those commercially available processing devices are used for storage operation. are not optimized, so the performance of those processing Hrn is not optimized to improve the performance of the equipment. It is often an obstacle to this. I decided to make a sub-door device for the storage device. You can improve the performance of the writing team, but if you do so, you will remember! The cost of IIF is low. It is a disadvantage to become.

Therefore, one object of the present invention is to easily update and replace control programs. The object of the present invention is to obtain a method of providing a control program that makes it possible to do this.

Another object of the present invention is that it is easy to implement and update, making it easy to implement and update sophisticated and complex programs. The goal is to obtain a control program that facilitates management.

Another object of the invention is that the disk drive itself can be easily updated without opening it. To obtain the WA121 program.

Another object of the present invention is to maintain the performance and test performance of the emulator at all times. The purpose of this book is to obtain a control panel that utilizes optimal mounting techniques such as surface mounting techniques. Yet another object of the invention is to improve commercially available gl control devices, while improving operational performance. The objective is to obtain a storage device that utilizes .

Summary of the invention Another object of the invention is directed to control systems for rotating media storage devices. This rotating media storage device is used to store basic power-up control programs. control panel and the storage device, as well as the connection between the storage device and the host computer. one or more processing means for controlling communications and a readout/processing means such as a RAM; When power is supplied to the storage device, the basic code in the ROM is initializes the control vtrn, starts the rotating storage medium, and starts the rotation storage medium Access control code. The #14 control code connects to any suitable connection, such as a 5CSI connection. Transferred to onboard RAM via the interface. Then the storage device The 111m program runs from a RAM-based control program. this is based on the “firmware” implemented in the onboard EEOROM. This eliminates the need for a control program to write to disk and You can change your program by simply transferring the new program to RAM for execution. and updates can be performed. In addition, to change the control program, There is no need to cut off the power supply to the unit.

The control device of the present invention provides dual processor access for distributed control of storage device operations. control by the mask processor, including the Monitor communications via a communications interface. In one embodiment of the present invention , the interface brings up the SC5I bus. ! T2 “slave” processor However, equipment such as rotational speed, read/write head position, and loading The dual processor scheme of the present invention utilizes commercially available processing equipment. Ru. Communication between processors is important for fast processing of individual distributed functions and Microwires utilize a novel communication protocol that enables high-speed communication of It will be held in

In order to reduce the physical size of the memory H of the present invention, the control board architecture is The purpose is to provide a series boat that can be used to realize an experimental environment. Emule - Download the code to the serial board and store it in RAM memory. I can do it. This allows the microprocessor to operate from RAM memory. In between, step through the program, set breakpoints, and update the microprocessor. Ability to decompose instructions is provided. Microprocessor operates from RAM memory External hardware for decomposing instructions, providing those breakpoints from ~ to By using a serial boat and a novel test protocol that eliminates the need for , multiple to test and emulate scenes with one host computer This enables "circular chaining" of storage devices.

Brief description of the drawing FIG. 1 is a block diagram of a conventional storage device.

FIG. 2 is a block diagram of the storage device of the present invention.

FIG. 3 is a block diagram of the system memory map of the present invention.

FIG. 4 is a block diagram of the mask processor and slave processor of the present invention.

FIG. 5 is a timing diagram showing a normal command sequence of the present invention.

Figure 6 shows the state of the present invention! FIG. 3 is a timing diagram illustrating the command to grow the 1ulI family.

FIG. 7 is a timing diagram illustrating the error handler of the present invention.

FIG. 8 is a block diagram showing a test configuration of a preferred embodiment of the present invention.

Detailed description of the invention Control Ivt settings for rotating media storage devices will be described. In the following explanation, In order to more fully explain the present invention, we will discuss the details of the program length, RAM capacity, etc. There are many specific details to explain. But without those specific details It will be apparent to those skilled in the art that the invention can be practiced. In other cases, the invention In order to avoid ambiguity, well-known configurations have not been described.

The present invention relates to the operation of a storage device, the communication between the storage device and a host computer, and the control program. method and apparatus for creating a program and controlling the distribution of amplifier power. Directed to the control aII device. A detailed description of the invention is provided by a Winchester-type hard drive. One or more disk drives A rotating storage disk and reading information from storage tracks on the surface of the disk. and a read/write head for writing information to the storage track. , a control panel containing the architecture for controlling disk drive operation, and a an interface for communication between the disk drive and the host computer. include.

Although the invention will be described in the context of hard disk drive storage vtIl, Any type of mass storage H! that requires communication to the device and performance of the storage device H! ! It will be obvious to those skilled in the art that the invention is equally applicable to, for example, books! l1lIIy) is limited to rotating media type storage devices or magnetic media type storage devices. but also applies to optical storage, tape, and other storage devices as well. be done.

foreground FIG. 1 shows the conventional control I! of a disk drive. Line 1 shows a block diagram of the lvt position. 2 is control #17. It is coupled to disk drive 10 via I8. bus 18 The disk drive 10 is operated by a processor 16 coupled to the disk via the 11IIgR is performed. coupled to processor 16 via control gs1m21 The programming for the processor 16 is contained in the EFROM 15 contained therein. Professional The processor 16 has a small computer interface (SC5I) via at9. ) is coupled to bus 14. The scs i bus 14 connects the RAM buffer via line 22. *RAM' buffer 13 is connected to input/output! buffer 113. via 117 , coupled to disk IO. The disk 11 has a user area 32 and a reserved area. The special area (SA) 23 of conventional drives includes the special area (SA) 23 that A marker and a composition pen, a small number of markers (both are typically reserved for one, or or a parking area for read/write heads. Figure 1 shows the conventional The disk drive is locked to the control program provided in EFROM15. be done. Allows you to update or change the control program for your disk drive. If desired, the entire EP'ROM 15 would have to be replaced. for that purpose The drive must be powered down and opened. Of course, during this power supply interruption Disk drives are unavailable and power supply interruptions are often very common. There is.

present invention In a preferred embodiment of the invention, a control program is provided to the onboard processor. “Soft loading” techniques are used to provide disk drive ring In the environment, the control program is located on the hard disk surface, which is accessed by the user. stored in a limited area that cannot be accessed. To handle the start, the f49I program Position the disc over the control program location on the disk surface. Then w4alp The program is downloaded to RAM on the control panel. The core of the control program is Used to check the downloading of the control program and then The operation of the processor is transferred to a control program stored in RAM. This software By using loading technology, the data stored in EFROM can be The conventional drawbacks associated with the use of software are eliminated. For example, the control program Because the firmware is easier to update, it is easier to update the debugger than traditional firmware control programs. ging can be easily performed at low cost. Therefore, longer (and more advanced) ram is accelerated and the operation of the disc is improved. Furthermore, it is tailored to various buyers. Easy to write control programs and replaces otherwise expensive EFROM Small size that uses t1 special program that may not be possible due to development Enables the production of "custom-made" bolted disk drives. Furthermore, the operating You must remove power to the drive to upgrade to a new control program. is unnecessary. Upgrades can be copied to the drive and the onboard emulator - I can do it. This reduces downtime, improves disk behavior, and increases efficiency. Ru.

In addition to the SC5I interface, the control board of the present invention also provides disk drive processing. Utilizes a serial port connected to the control equipment. New program with series boat Downloading of RAM, emulator code, and test procedures is permitted. Ru. Control program for emulation training program and test program in RAM can be interchanged with breakpoints, decomposition instructions, and single steps in a disk process. and to be able to use it. This allows onboard emulation, or This eliminates the need to connect the probe to the board processing Hffl, thus processing 1 Jr. No external physical connections are required to the Il, allowing surface mount technology to be used. A special protocol combines multiple disk drives together for testing purposes. Can be chained in a circular manner. Each test command and response can be differentiated between multiple drives. Disk drives are assigned slots on the chain. In this way, multiple ( For example, target only one host computer for up to 254 drives. This increases drive manufacturing efficiency.

A preferred embodiment of the invention includes a mask process for controlling the 5C5I interface. split processor and slave processor for disk operation gJ4r1g. By using distribution control. The slave processor is controlled by the transmission speed and head position. 2 times in front of you and then stop moving. The master processor monitors the 5C5I bus and control communication between the disk drive and the host computer. This architecture of the processor in the microwire to take advantage of the additional speech allowed by A novel protocol for leap communication is implemented in a preferred embodiment of the present invention.

The master processor and slave processors in the preferred embodiment of the invention are 24 National Semiconductor (National Sem1) operating at megahertz conductor) HOC46083 microcontroller. master process When a processor wishes to communicate with a slave processor, the mask processor Outputs a ready signal to the slave processor. The slave processor initializes and sends the D signal back to the mask processor. Then the master processor The slave processor responds with a status signal. Ma To control the distribution of star processors and slave processors, seek can be done using conventional devices. can be executed more quickly than The slave processor constantly monitors the head position and speed. When a seek command is received from the master processor, the seek is executed quickly. It can be realized quickly. At the same time, the master processor communicates with the slave processor. You can retrieve information for the next seek, or retrieve state or other information from the host controller. supply to pewter.

Traditional control panels use only one processor, so traditional disk drives Certain inefficiencies are inherent in Eve. For example, if the 5C8I bus When used to interface with a host computer, the servo control Abandoned. When a seek command is received, the processor starts a seek operation fl It must first get the servo status.

Reference is now made to FIG. 2, where a block diagram of a preferred embodiment of the present invention is shown.

The control board 12 of the present invention includes two processors. Master processor 4 and sleigh A processor 25 is used to control various aspects of disk drive functionality. I can stay. The mask processor 24 connects the SC8I path to the RAM buffer interface. connected to the disk drive via the host. The mask processor 24 is the control panel 2 9 to the SCS I bus 14. The 5C8I bus 14 connects the control panel 22 to RAM buffers 1!3, which processor RAM buffers have input and output It is coupled to a force control panel 17. The master processor has an scst interface , which controls communication between the host computer and the disk drive.

Slave processor 25 is a line! 8 to the disk drive 10; Serial boat 27 of control panel 12 couples mask processor to 24 via 1a30 be done. ROM 28 is coupled to slave processor 25 via line 23. Ru. The mask processor is coupled via line 29 to RAM 2B. slave pro The processor monitors disk drive status and operations such as rotational speed and head position. Monitor line or seek commands. The series boat 27 connects to the mass via the line 3o. The data processor 24 is coupled to a processor 24.

When power is applied, it initializes the 5C5I interface and rotates the disk. Load the control program into the RAM space and load the control program based on the RAM. Provides basic code to run from RAM. RAM port 28 has an address range. It consists of the following code with a box of FFFF-EOOO.

1.1Ell simplified diagnosis 2. Microwire interface (communication with servo) 3. Basic missing parts! tube 4. Partial emulation replacement hood (U ARTlJJ period (1, Emi, load the rest of the Lachine code) 5.5C5I Passphase Support 6. Support for RESET interrupt and NMI interrupt 7. Use the following SC5I command support a, REQUEsT 5ENSE b, READ DEFECTS LISTc, DOWNLOAD d.UPLOAD e, 5TART EXECUTION f,lN5TALL t, FORMAT h, READ 5BL i, D summer AGNO5TIC5 The program code loaded from the special area 23 is stored in the RAM as shown in FIG. mapped to the area below 26.

1. Address 6000-81FF, soft boot label area (512 bytes) 2 , address 6200-6200, interrupt vector table (32 bytes) 3, address 6300-6400JSRP, vector table for emulation scene code ( 256 bytes) 4. Address 0000~DFFF, emulator code (84 bytes) software The top label area is subject to revisions, documentation numbers, and soft top labels. Contains other special information about the firmware. The interrupt vector table area is reset. This applies to all interrupts except for interrupts. JSRP vector table is emulator - Emulation code interrupt used when scene code is called It is a table. The "real" firmware commands all scs and handles all errors. It supports all basic disk operations and all standard disk operations. Monitor area is custom made This corresponds to the program diagnostic performance and debugging controller.

When power is supplied to the disk, the code to be used as the ROM pace in the ROM boot 28 is Do the following:

! , initialize the processor 2. Initialize the interfaced SC3I 3. Microwire interface Initialize the face 4. Send diagnostic commands via microwire r/f 5. 6. Rapid test of RON to test the interface RAM area 7. Spin up the disk 8. Read softput area and check validity if valid 9. Load the code into 32K EAM 10. Inspect a certain RAM and find out that the code is Check if the transfer was successful, jump the code to 32K RAM 12, respect the command if not valid 9a, check set condition and status byte 10a, additional sense byte 5BN As if it were a T (hew) set 11m, 8K limited fingers in ROM The label is first loaded into the soft put area 23 on the disk which is then skipped over to the next step. is coded.

This label indicates validity, revision, documentation, maintenance and production. There is a number for the rD code. The label and the code that immediately follows this label. The code is placed in three separate areas within the soft boot area. soft pop - Label size - Matt has a 16-byte signature, revised 31 number (IS byte), and a doki. .

Menthesis 1 number (16 bytes), Grodaxene 10 number (16 bytes), and a 122-326 bar for ASCI columns for rights notices, proprietary notices, etc. Including light. The NMJn input provided in the 8KROM is the UART of the processor. Initialize the boat and allow the rest of the emulation scene code to download. this loads 32K RAM area via serial port 27 on the PC. Load the processor UART port and then start the emulator 1 hood skill. start.

A preferred embodiment of the invention includes diagnostics for power-up, which diagnostics include process Initialize the processor, initialize the 5C5I interface chip, and initialize the microwire This consists of initializing the interface. Mesoso's exam is 5C5I memory and 32 K: Basic read/write of 0s and 1s to RAM. Micro wire A diagnostic finger is sent to the servo and then reflected back to test the interface. There is an order.

Those directives are:

Mutual op code description Requirement sense 03 Defect list reading 37 P list call defect Download 35 5C5I to RAM (inter hex Fut-Mat) Ab Broad 3B Start execution from RAM to SC3I 3CRA Start at M place Installation I 38 Load from there disk Format SA 39 Format disk soft put area 5BLi! Protrusion 3A Area to read soft output label A.M. Diagnosis 3B Extended execution diagnosis controller In a preferred embodiment of the invention, the code may The only commands the controller receives after powering up or resetting until it is received from There is. Assuming the soft put area is not valid, the 5C5I status byte is OP code assignments are provided by the preferred embodiment only, e.g. OP code assignments may be shifted without departing from the spirit of the invention. Hoss If the client computer device issues the request sense command, the returned extended set The sense data shows an additional sense buy showing 5BNV (W-ineffective soft put). It has hsx 2B in it. The installation command reads raw data from the RAM area and from the label. For the first time, take all 32 bites and store them in the disk area of 8 rows. Start the process again. Three of the 32K RAM in the soft boot area on the disk. This process continues until there is a copy (the download command is In the embodiment, the Intel (1nter) h a x format is used.

This command steals the information bytes and loads the data into RAM at 32. inspection The total is calculated and then the intel hex format is used to ensure good data. - Tested with the checksum given by Matt. line marker begging Add all bytes except (begging), then add 2 of that total. The checksum is computed by taking the complement of .

Abroad command takes raw data in 32K RAM and transfers it to Intel hex format. Insert f11gI field for mat. The uploaded area is It is a foot label, a vector table, an address range of 6000 to 6220, Interrupt the firmware and address range 7000-BFFF.

Format SA directives are used to display defective map and soft output labels and firmware. Format only the area on the disk that has software. It is this special To support some basic defect management for defective areas within the Use the P list for this purpose. The defect list read command is sent from the factory to the host. The P list of “bytes from index” that was previously recorded in the Forward. Read G-list or other defective list formats An attempt to do so will cause the test condition state to be set in error. This is the sense key of "5" and set the additional sense code to r24J (hew). Split The inclusion vector is a fixed location within Boo FROM 28. Their vectors are 32 Refers to a location within KR5M area 26. RAM comes with unknown decoys, so those vectors Vectors have to be initialized by those that are starting to use vectors. Yes, the ROM putcode sets the 8M1 interrupt vector and Points to the 8K ROM space to call the 1-in code. to handle interrupts , its vector containing the NMI that points the emulane code's own routine to The emulation scene hood must be initialized, based on 32KRAM Load those vectors into the firmware to ensure normal operation of the disk. We have to make it possible.

microwire interface A preferred embodiment of the invention is manufactured by National Semiconductor. The HPC46083 microcontroller from Sono 1 conductor is used. deer However, any suitable microcontroller may be utilized in the present invention. master process The connection between the processor and the slave processor is shown at 41J.

The voltage DCC is connected to the mask processor 24 and the thread via the resistor R1 at the node 32. 2S. Number 32 is installed via capacitor CI Ru. Node 32 connects the mask processor and straight processor at the reset input terminal. bound to the processor. The mask processor 24 sends the command to the slap processor 25. Slepe processor 25 provides status to mask processor 24 . trout The processor 24 indicates that a command should be sent by setting line 27 high. Signal to sleip processor 25. SCMI (SC5I command) line is masked is supplied to the bin-in PO of the processor 24 and input to the bin D7 of the processor 25. Ru. When the slave processor 25 is ready to receive commands, it sends a ready signal. Output 5RDY to 11134. Slape processor 25 sends the signal to bin PO master processor 24 receives it in bin D7. Suppose there is a mistake , the sleip processor 25 outputs the signal Par! Output to 1cEPR33. line 33 is coupled to processor bin P1 and coupled to processor bin D6.

Clock signal 5CLK is connected to the mask processor via line 36 at bin B6. Supplied to rape processor. After the command has been received, a warning signal is received. - then the slave processor 25 outputs the status signal 5STAT via line 38. output to the screen processor 24. This signal is the bin BS of the slave processor 25. and is input to bin S1 of mask processor 24. Data signal 5DA TA from Bin St of Slape Processor 25! Master processor via I35 It is supplied to the bin B5 of the server 24.

Communication between processors is such that the master processor requests information, consults Linda, and When the drive is disconnected and the drive is spun up/down, the Communication is performed on the microwire interface in each processor. A communication link is established. The mask processor is a mask microwire, The servo processor is Slave. All commands in the preferred embodiment are 16-bit All states returned are 16 bits long. The state is the square that sends the state command. It is simply returned to the processor. Status I! ! /The most significant bit after the command is always the most significant bit. The least significant bit (the bit placed at 0) is sent last.

communication signal Master processor Slave processor Signal name baud) PO (output) TBO ( Human power) SCMD (SC5I command) Boat D7 (input) TBO (output) SR MD (4 Ichiban Reti) Boat DB (human power) TBO (output) 5ERR ( Servo error) Boat B5/So (output) Baud) +5/Sl (input) 5SD A baud) 15/Sl (input) boat B5/SK (output) 5STA baud) B5 /SK (output) Boat Be/SK (manpower) 5CLK microwire is 8 bit All commands and states are 16 bits. Slay When the processor is ready to receive commands, it makes 5RDI active high. assert. 5RDI asserts low after first command byte is received . Then the mask processor sends the last command byte, if 5RDI is high, the Page change ends (seek ends or status read). state of operation During the process, the mask processor reads the MSB (byte) or the first byte of the state. read by the sleip processor. 5RDY after the last bit is read Return to high.

When the mask processor sets SCMD high, the mask processor sets SCMD high. Monitor the asynchronous 5ERRs that have been triggered. 5ERR high to determine fault condition Instructs the master processor that the state should be executed. SCMD is low (and the mask processor sends an instruction to receive the state. The last byte of the state 5ERR returns low after the signal is sent from the servo processor. mask processor The 5ERR must be aware of the Asserted.

Microwire frequency is SK=24MHz/+9=1.26MHz or 160 bytes 7 seconds be programmed.

Processor overhead can be delivered to within about 100 μSec.

command word (MSB) (LSB) bl5 bl4 bl3 bl2 bl l blObo9 bo8 bo7 boa bo5 bo4 bo3 bo2 bol boO command field Data field Command field Data field 0tlz - Disk spin up 000HxIHX - Disk spin down 0OOHx28X-Seek Shilling Address <11:07>O-40953H X-Thermal Head Head Address <11:O> O~34) IX-) Rack Offset Offset amount <11:O> O~358X-Diagnosis Reflection number <11 :0＞　O~40958Hx-73　000　Hz 7Hx-Read sector status 0OOHz88X-Read track status 0O OHz91+z - Sector size, band set to 0 Sector size in bytes Size<II:0>AHx - sector size, band set to 1, expressed in bytes Sector size <II:O> Reflection number part (MSB) (LSB) bl5 bl4 bl3 bl2 bll blObo9 bo8 bo7 b o8 bo5 bo4 bo3 bo2 bol bo.

ku□　Reflection number　□〉 Sector-like III read MSB) (LSB) bl6 bl4 bl3 bl2 bll blo bo9 bo8 bo7 bog bo5 bo4 bo3 bo2 boI boo <- Sector number sending (RPS) <11: O> → Read track status MSB) (LSB) GHz-Disk pin up 0OOHxIHX-Disk spin down 0O OHx28X-Seek Schilling Address <II:07>0 -40953HX -’)-Mulhead Hept Address <zoo> o~348X-) Rack Off Set Offset It<11:O> O~35HX-Diagnosis Reflection Number<11: O> O~40958Hx-fi 0OOHz 7HX-Sector status read 0OOHz8Hx-Track-shaped fi read 0 00Hz9Hz - Sector size, band set to 0 Sector size in bytes Size<II:O>ATo-Sector size, band set to 1, expressed in bytes Sector size <II:0> Reflection number part (MSB) (LSB) bl6 bl4 bl3 bl2 bll blObo9 bo8 bo7 b o6 bo5 bo4 bo3 bo2 bol bo.

ku□　Reflection number　□〉 Read sector status MSB) (LSB) bl5 bl4 bl3 bl2 bll blObo9 bo8 bo7 b o6 bo5 bo4 bo3 bo2 boI boO - sector number sending ( RPS) <11:O> → Read track status MSB) (LSB) bl6 bl4 bl3 bl2 bl l blo bo9 bo8 bo7 bo6 bo5 bo4 bo3 bo2 bol bo■ □Reflection book number (RPS) <15: o> -> Status read back MSB) (LSB) b16b14b13b12bllbsummer0b09b08bOfub08b05b04 b03b02b01b00b15-Pending bl4-pending bl3-pending bl2-pending bll-hold blo-pending bo9 - Spindle motor stopped by stop command bO8 - Power-on reset state exists b07-Pending bo6-interface failure bo5 - invalid command or not fulfilled bo4-seek disorder bo3-) rack offset faulty write gate b02-pending bol-failure write boo-hold Microwire interface for HCP used to communicate between the slepe processor and the slepe processor, thus Grow Mastev (SCSI) Slave (SERTU).

When in a reset state power up or otherwise, the slepe will start with the mask first. wait for it to be updated. This is due to the rising SCMDll. is combined with Then we can initialize the slepe. Slape leaves it's initialization The last thing to do before the μWIR The goal is to clear the EDONE flag. Slape SCMD for transfer wait for it to become low. Indicates that Musk wishes to take command.

Set.

The mask sends the first byte and the μWIREDONE flag is set. Wait for , then read the first byte from 810.

Slape is performed by writing to the S■0 register.μW I RF, D ON F. Reset the flag.

Slape waits for the μWIREDONE flag to be set, then Read second byte from i2, slepe then write to SIO register This resets the μWIREDONE flag.

At this point, Mask and Slape determine which commands were sent. according to directive , Slape takes information from the rest of the command and responds to it with an action or returns to the state. Ru. In any case Set Y high.

Assuming there is no state・Senken Check whether the mask increases the 5ERR...means there is an error.

Assuming there is no error, Φ parable Mask sets SCMD high.

The command sequence is shown in FIG. The mask processor has a falling edge Draw the SCMD line low as shown at 50, ready to send commands. Signal this to the sleip processor. Signal 5RDY is on the rising edge 40. As shown, the sleip processor is set higher and the sleip processor indicates that it is ready to receive commands. In a preferred embodiment, at the beginning of the directive 8 bytes of data are sent as shown by the block signal 5CLK. Then, slap When the processor falls, it sets 5CLK low in the u section 47, and the slave Indicates that it is ready to receive the second byte of the command signal (SCLK) and The command signal SCMD is high at the rising edge '39, when the mask sends the command. Indicates that the If it is detected that there is no error, the error (; RR remains low.

Next, the state afj! Refer to FIG. 6, where a command with a return is shown. as before , the master processor pulls down the SCMD line as shown at falling edge 50. signal to the Slave Processor that it is ready to send commands.

Signal 5RDY is set high (set) by the Slave processor on the rising edge. informs the mask that it can send commands. The command sent, 5CL K's command 60 signals a state request command. 5RDY signal is falling edge 51 is set high. End of status command, i.e. command 00 of 5CLK is sent and the 5RDY signal is set high to flag incoming information.

The command XX in state fi, 5CLK is given to the master processor in two parts. It will be done. The first byte is sent when 5RDY is high. Falling edge 43 odor The second status byte is sent after 5RDY is set low and the rising edge 5RDY is raised at 44 to signal the end of the condition.

m7rl! J sends a command f indicating error handling in the protocol of the present invention. For preparation, SCMD is set low at edge 50. However, the command An error occurs during the transmission, and at the rising edge 52, 5ERR is bounced by slapping. is set. In this respect, Sleip and Mask follow the process described with reference to Figure 6. The mask returns and asks the status about the error. The status is 5RDY. It is sent in two bytes in the high and low phases of II.

Test environment The burn-in environment described in this specification is an advanced automaton and data collection environment. Disk drive onboarding to achieve a low-cost testing environment that fosters using a serial interface with a microprocessor.

The disk drive control program, the preferred embodiment of the present invention, is a simple LA N (Local Area Network). This support port and the packed port referenced via the LAN by the master computer. Includes some trick routines and a special burn-in of the firmware. It can be made into Mochi-sama as Ji, N.

Command packet format address count inspection table a1 Address 8-bit address field - Supports 256 addresses.

Address 00h is reserved for the host AT processor and address FFh is reserved for the host AT processor. Reserved for access for all drives, up to 26 per A-series boat. 4 drives can be tested.

Count 8-bit count field - indicates to transfer 4 to 256 bytes forgive.

Command Allows commands in the 8-bit command field -256.

Test sum 8-bit test sum field - Test sum modulus 256 test sums meter code.

This command foot-map allows one host AT to control one or more of the drives under test. is allowed to address the entire AT, and the drive under test sends responses to the host AT Allow to send back to address 00h).

With 256 instructions available, each macro can be downloaded to control/modify. “Macro” directives, which can contain parameter tables specified for special test sequences. Many of these directives can be reserved for the purpose of

Packets are for single command operator (polling, reset, power up, etc.) in small bytes like 4 bytes (address, count, command, checksum). For more complex command sequences (if they include command chains) can reduce the length of the command to near infinity.

The checksum is reduced to 8 bits. The chances of a bad checksum going undetected are very small. do not have.

Up to four instrument rows can be tested at one time.

The configuration for the test environment of the present invention is shown in FIG. Multiple drives P1~ One host computer 50 is used to control the test of P(N). Ru. The drives are connected to the host computer in series in a circular chain through each drive's series ports. connected to the computer. The serial output terminal of host computer 50 is connected via line 51. and is coupled to the series input terminal of the drive PI. The series output terminal of drive Pl is wire 52 to the series input terminal of drive P2. Series output of drive P2 The terminal is coupled by a54 to the series input terminal of drive P(N). drive The output terminal of P(N) is coupled to the input terminal of host computer 50 by line 55. It will be done.

l) The host AT (HAT) sends the NOP via the STP (serial test board) Anticipate being sent and receiving instructions. This means that the series wires are connected in a closed circuit. Verify that power is available to all drives installed.

2) HAT sends reset via STP. This is a test drive with no activity should not be allowed to occur.

3) The HAT sends a signal to select all over the wire and requires the operator's input before proceeding. Wait for intervention. This ensures that all drives recognize commands via STP and also Be prepared to inspect. Drives that fail this test will be sent to 5D for debugging. It should be returned to S-1000.

4) After the operator resumes the test, the HAT performs the logical drive assignment (LAD ) to the first drive, address 01h1.

The first drive receives the packet and keeps the logical drive address (Olh). hold, increment the address field to 02h, and send the packet to the next drive.

Each drive receives a LAD command, holds a logical address, increments it, and replays the packet. send.

The HAT receives the command packet (CP) and directs the command packet (CP) to that number of drives (DUTs) under test. CP address is retained (decreased) for the CP address.

5) The HAT balls the state of each DUT and each DUT responds to its logical address. Check that the answer is correct.

The DUT obtained from the basic tricks to check the healthy values (RAM, registers, etc.) ) to address OOh (HAT).

6) The HAT sequence abducts each HAT at the appropriate time to buff it up. pause, then power up the next logic DUT, then return to the previous OUT state. to ball.

7) After all OUTs are powered up and before testing read and write Preliminary seek test, max access conduct.

8) The HAT reads drive information from the DtJT during the seek test. DUT is a series Provide the number, bad track list, and current status to the host.

9) The DAT shall perform a full test for the DtJT test/state at most every 2 minutes after this point. Ball test for all drives. DUT error rate is the maximum threshold , the DUT is flagged as a failed drive.

10) HAT sends download test command to all drives. Each DυT is diagnostic Load the program from the disk to the RAM and wait for the next command from the HAT 11) The HAT sends a test start command (or macro test) to start the test.

12) Each drive maintains a bad track table (BTT) in RAM and responds to requests. and update the BTT.

13) HAT calculates, edits, and prints drive status for all DUTs. Ru. This data includes tables of bad tracks, test parameters, detected soft/hard This data includes the number of errors and a pass or fail statement. All of the data is available in the OUT reserved data area.

14) The HAT maintains a combined historical log of all tests on the DUT. Ru.

Preliminary command set: download exam format Logical drive assignment (LAD) Macro [50] op ball reading physical readout seek Start of exam situation write physical write Test stop Send results The above describes the soft loading of control programming and the use of a single host computer. testing of multiple disk drives using a computer, and distribution control of drive operation. A disk drive storage device that allows efficient communication between on-board processors of This paper has explained the control method and control device for the station.

Engraving (no changes to the content) FIGLII? E 3 Fl(EIUI?E 8 ""! 22222211 Procedure amendment writing method) %formula% 1.Display of the incident 2. Name of the invention Rotating media storage control 3. Person who makes corrections 6. Subject of correction 7. Contents of correction international search report m-1-^--〇-”=　r/II(RQ10’/l’l’1PCr/US89 105033 Group I, claims 1-8 (first occurrence ), drawn to the rading and first and 　5econd　control　mans.

Group III, claims 15-16. drawn to a Methcxl of testing a plural Amakashi ■ of disk drives using a host alpha ter.

1"'""*++ a~l Aeekcals"lie,, 工~S891050 33

Claims (16)

[Claims] 1. a process of storing a control program in a part of a rotating medium storage device; a starting program is executed by the control means to read a program from said rotating storage medium; the process of storing said control program in memory means coupled to said control means; With mode, The control program is executed by the control means to realize the operation of the storage device. the process of carrying out the A method for supplying a control program to a control means of a rotating media storage device, comprising: 2. 2. The method of claim 1, wherein the control program reads from the storage medium. The method further comprising the step of checking the control program when issued. 3. 2. The method according to claim 1, wherein the step of reading the control program comprises: a process of initializing the control means; initializing an interface between the control means and the host computer coater; , testing the memory means; A process of initializing the rotation of the storage medium, reading the control program, and reading the control program. a step of validating a program and transferring said program to said memory means; process and method for preparing. 4. The method of claim 1, wherein the control means comprises a microprocessor. Method. 5. 2. The method of claim 1, wherein the memory means comprises a random access memory ( RAM). 6. The method of claim 1, wherein the storage device comprises a magnetic disk drive. How to do it. 7. 2. The method of claim 1, wherein the initiator program is stored in a read-only memory ( How to store data in ROM). 8. a control means for controlling operation of the rotating media storage device; and a control means coupled to the control means; a first storage means for initializing a start program of the storage device; when the media storage device is coupled to the control means and the initialization program is executed; a control program stored in the storage device that controls the operation of the storage device after startup of the device; reading out the control program and storing the control program in the second storage means; /writing means; a host computer for communication between the host computer means and said control means; and interface means coupled to said control means. Storage device. 8. 8. The apparatus of claim 7, wherein the rotating medium is a magnetic drive, and the rotating medium is a magnetic drive. The control program is located in a portion of said drive that is separate from the disk area of said drive. device stored in. 9. 8. The apparatus according to claim 7, wherein the first storage means comprises a read-only memory ( ROM). 10. 8. The apparatus of claim 7, wherein said second memory means is randomly accessed. A device equipped with memory (RAM). 11. 2. The apparatus according to claim 1, wherein the control means includes a first processing means and a second processing means. the first processing means controls the interface and the second processing means controls the interface; The processing means is a device for controlling access to the rotating medium. 12. 8. The apparatus according to claim 7, wherein said serial input means to said first processing means. A device with coupled serial ports. 13. A first control means and a second control means for controlling the operation of the rotating media storage device. In a rotating medium storage device having stages, a first signal in a first state is transmitted to the first control. supplying from the control means to the second control means; The second control means is initialized, and the second signal in the first state is transmitted to the second control means. a step of supplying the second signal from the first control means to the first control means; At a certain time, a 1-byte command signal is sent from the first control means to the second control means. a step of supplying a second byte when the second signal is in the second state; supplying the command signal from the first control means to the second control means; A method for communicating between the first control means and the second control means, comprising: 14. 14. The method of claim 13, wherein the first control means comprises a first processor. A method comprising: said second control means comprising a second processor. 15. One host combination coater with input series port and output series port In a method of testing a plurality of disk drives, each of said plurality of disk drives providing a serial input port and a serial output port on the bus; The output serial port of the host computer is connected to the plurality of disk drives. coupling to said input port of a first one disk drive; Connecting the output serial port of the disk drive to the second disk of the disk drive. the process of coupling to said input serial port of a disk drive and each successive disk drive. Connect the output port of the drive to the front of each subsequent disk drive after the disk drive. the process of combining the input serial port and the output serial port of the nth disk drive; coupling a port to the input serial port of the host compicoter; a test program from said host computer to a first memory means in said disk drive; The process of providing logging and processing means in each said plurality of disk drives. performing said test programming; One host compicoter with input serial port and output serial port with How to test multiple disk drives. 16. 16. The method of claim 15, wherein the test programming includes a first test. sending commands from the host computer to test the complete circuit; A drive assignment command is sent to each of the plurality of drives to identifying the drive; A process of polling the status of each said drive and a diagnostic test sequence for each said drive. sending a test start sequence command to each said drive; polling the status of each of the drives after executing the test sequence; How to prepare.