KR20060082309A - Method of forming a metal line in semiconductor device - Google Patents

Abstract

The idea of the present invention is to form a source contact plug and a drain contact plug on a semiconductor substrate, each having a source region and a drain region of a cell region, a source / drain region of a peripheral circuit region, and a gate electrode pattern, wherein the drain contact Sequentially forming and patterning a second etch stop layer and a third interlayer insulating layer on a resultant product on which a plug is formed, and forming an amorphous insulating layer on the entire surface of the resultant product And sequentially forming an inorganic antireflection film, patterning the amorphous insulating film, and forming the first metal contact hole to be connected to the source contact plug by using the patterned amorphous insulating film as an etch stop film and an etching mask. A second metal contact hole to be connected to the drain contact plug, a third metal contact hole to be connected to a source / drain region of the peripheral circuit region, and a fourth metal contact to be connected to a gate electrode pattern of the peripheral circuit region Forming a hole and allowing the conductive film to be embedded only in the first, second, third and fourth metal contact holes, thereby forming the first metal wiring, the second metal wiring, the third metal wiring and the fourth metal wiring. And completing the forming process.

Metal wiring

Description

Method of forming a metal line in semiconductor device             

1 to 5 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

* Description of the symbols for the main parts of the drawings *

44: carbon-based amorphous oxide film

46: In-organic antireflection film

M1, M2, M3, M4; Metal wiring

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming metal wiring of a semiconductor device.

Recently, in the method of manufacturing a flash memory device, a process of forming a metal wiring using a dual damascene process is performed.

A metal wiring trench for forming an upper layer wiring is formed, a metal contact hole for connecting the metal wiring trench with a junction region formed in a lower wiring or a substrate is formed to fill a conductive film, and then a planarization process is performed to form a metal wiring trench. .

However, due to the different spacing of the patterns (gate electrode, source / drain regions) formed in each region in the metal contact hole formation process formed at the same time in the cell region and the peripheral circuit region, nonuniformity of the contact hole formation, pattern defect, contact sickle Problems such as open will occur.

An object of the present invention for solving the above problems is the nonuniformity of contact hole formation generated during the metal contact hole formation process, which is simultaneously formed in the cell region and the peripheral circuit region, which are the regions where the patterns (gate electrode patterns, etc.) are different from each other, The present invention provides a method for forming a metal wiring of a semiconductor device that can solve problems such as pattern defects, contact knock-opening, and the like.

An object of the present invention for achieving the above object is to provide a first contact plug exposing a first joining region and a second joining region formed in a region different from the first joining region having a height higher than that of the first contact plug. Forming a semiconductor substrate provided with a cell region having an exposed second contact plug and a peripheral circuit region having a third junction region formed in a region different from the first and second junction regions, the front surface of the semiconductor substrate Sequentially forming an amorphous insulating film and an antireflection film in the first metal contact hole exposing the first contact plug, the second contact plug, and the third junction region by patterning the antireflection film and the amorphous insulating film, respectively; Forming a second metal contact hole and a third metal contact hole, and allowing the conductive film to be embedded only in the first, second and third metal contact holes, respectively. Comprising the steps of forming the first metal wiring, the second metal wiring and the third metal wiring.

Preferably, the amorphous insulating film includes a carbon-based amorphous oxide film.

It is preferable that the antireflection film includes an inorganic antireflection film.

Preferably, the first or second junction region is a source region of the cell region.

Preferably, the first or second junction region is a drain region of the cell region.

Preferably, the third junction region is a source / drain region of the peripheral circuit region.

Preferably, the second contact plug has a height higher than that of the first contact plug because the second contact plug is formed after at least one interlayer insulating film is formed on the first contact plug.                     

The third metal contact hole exposing the third junction region is preferably about the height of the sum of the heights of the second contact plug, the amorphous insulating film, and the anti-reflection film.

The first metal contact hole may be about the height of the height of the interlayer insulating film formed on the first contact plug and the height of the amorphous insulating film and the antireflection film.

Another idea of the present invention is to form a first interlayer insulating film on a semiconductor substrate, each having a source region and a drain region of a cell region, a source / drain region of a peripheral circuit region, and a gate electrode pattern, and forming the first interlayer insulating layer. Forming a source contact hole by patterning the source contact hole exposing the source region of the cell region, and then forming a source contact plug by forming a conductive layer to fill only the inside of the source contact hole, and forming a source contact plug on the resultant on which the source contact plug is formed. A stop layer and a second interlayer insulating layer are sequentially formed, and the second interlayer insulating layer and the first etch stop layer are patterned to form a drain contact hole exposing the drain region of the cell region, and then filling only the inside of the drain contact hole. Forming a drain contact plug by forming a conductive film so that the drain contact plug is formed After the second etch stop layer and the third interlayer insulating film are sequentially formed on the substrate, a region in which metal wiring to be connected to the source contact plug is to be formed, a region in which a metal wiring to be connected to the drain contact plug are to be formed, and the peripheral circuit region is formed. Patterning the region where the metal interconnection to be connected to the source / drain region and the region where the metal interconnection to be connected to the gate electrode pattern of the peripheral circuit region are to be formed on the third interlayer insulating layer and the second etch stop layer, respectively; Amorphous insulating film on the front And sequentially forming an inorganic antireflection film, a region in which a metal wiring to be connected to the source contact plug is formed, a region in which a metal wiring to be connected to the drain contact plug are formed, and a metal wiring to be connected to a source / drain region of the peripheral circuit region. Patterning the region to be formed and the region in which the metal wiring to be connected to the gate electrode pattern of the peripheral circuit region are to be formed in the amorphous insulating layer, and using the amorphous insulating pattern in which the regions are patterned as an etch stop layer and an etching mask. Etching the interlayer insulating layer and the first etch stop layer to form a first metal contact hole to be connected to the source contact plug, forming a second metal contact hole to be connected to the drain contact plug, and forming the second interlayer insulating layer and first etching The stop layer and the first interlayer insulating layer are etched and connected to the source / drain regions of the peripheral circuit region. Forming a third metal contact hole and etching the second interlayer insulating layer, the first etch stop layer, and the first interlayer insulating layer to form a fourth metal contact hole to be connected to the gate electrode pattern of the peripheral circuit region; Completing the process of forming the first metal wiring, the second metal wiring, the third metal wiring, and the fourth metal wiring by allowing the conductive film to be embedded only in the first, second, third and fourth metal contact holes. do.

The amorphous insulating film is preferably a carbon-based amorphous oxide film.

A region where a metal wiring to be connected to the source contact plug is to be formed, a region where a metal wiring to be connected to the drain contact plug is to be formed, a region where a metal wiring to be connected to the source / drain region of the peripheral circuit region is to be formed, and a gate of the peripheral circuit region. The patterning of the region in which the metal wiring to be connected to the electrode pattern is to be formed in the amorphous insulating film may include forming a region in which the metal wiring to be connected to the source contact plug is to be formed and a region in which the metal wiring to be connected to the drain contact plug is to be formed. Forming patterns for defining regions in which metal wirings to be connected to the source / drain regions of the peripheral circuit region and regions in which metal wirings to be connected to the gate electrode pattern of the peripheral circuit region are formed, and etching the patterns. Etching and patterning the inorganic anti-reflective coating layer Preferably, the amorphous insulating film is etched using the turns and the patterned inorganic anti-reflection film as an etching mask.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, embodiments of the present invention may be modified in many different forms, but the scope of the present invention should not be construed as being limited by the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In addition, when a film is described as being on or in contact with another film or semiconductor substrate, the film may be in direct contact with the other film or semiconductor substrate, or a third film is interposed therebetween. It may be done.

1 to 5 are cross-sectional views illustrating a method for forming metal wirings of a semiconductor device according to the present invention.

Referring to FIG. 1, an insulating film 14 for a tunnel oxide film, a first polysilicon film 16 for a floating gate electrode, and a semiconductor oxide layer 10 defined as a cell region A and a peripheral circuit region B are defined. The ONO film 18, the second polysilicon film 20 for the control gate electrode, and the tungsten silicide film 22 are sequentially formed.

A photoresist pattern (not shown) for a gate electrode is formed on the tungsten silicide layer 20, and the tungsten silicide layer 22, the second polysilicon layer 20 for a control gate electrode, and an ONO layer are used as an etching mask. (18), the first polysilicon film 16 for the floating gate electrode and the insulating film 14 for the tunnel oxide film are etched and patterned to form a gate electrode pattern.

In the gate electrode pattern, a cell transistor CT, a gate electrode pattern SSL for SSL, and a gate electrode pattern DSL for DSL are formed in the cell region A, and a peripheral circuit is formed in the peripheral circuit region B. A gate electrode pattern PT is formed.

The first junction region 24a is formed by performing an ion implantation process on the entire surface of the resultant product having the gate electrode patterns.

After the nitride film is formed on the entire surface of the resultant gate electrode pattern formed thereon, an etch back process is performed on the nitride film, so that both side walls of the peripheral circuit gate electrode pattern PT and the gate select pattern (DSL) gate electrode pattern DSL are formed. The spacer 26 is formed on one side wall of the sidewall and one side wall of the gate electrode pattern SSL for the source select line (SSL). In addition, the nitride layer is buried between the cell transistor, the cell transistor, one side wall of the DSL gate electrode pattern DSL and the cell transistor, one side wall of the SSL gate electrode pattern SSL, and the cell transistor to insulate them from each other.

Subsequently, after only the peripheral circuit region is exposed, an ion implantation process is performed to form a second junction region 24b on a semiconductor substrate in an adjacent region where the first junction region 24a is formed.

Subsequently, a photoresist pattern (not shown) is formed to etch the peripheral electrode gate electrode pattern PT to form a butting contact hole, and the photoresist pattern is etched using an etching mask. A butting contact hole through which the ONO film is exposed is formed. An ashing process for removing the photoresist pattern (not shown) is performed.

An oxidation process is performed on the entire surface of the resultant substrate in which the butting contact hole is formed in the gate electrode pattern for the peripheral circuit, and a buffer oxide layer (not shown) is formed, and the SAC nitride layer 28 is formed in the buffer oxide layer (not shown).

The first interlayer insulating film 30, such as the HDP oxide film, is formed on the entire surface of the formed buffer oxide film (not shown) and the SAC nitride film 28, and the upper portion of the HDP oxide film 30 to define a trench type source contact. After the photoresist pattern (not shown) is formed in the trench, an etching process is performed using an etching mask to form a trench-type source contact hole (not shown) in which the junction region 24a is exposed. An ashing process of removing the photoresist pattern (not shown) is performed.

A layer including a tungsten silicide layer is formed on the entire surface of the resultant in which the source contact hole (not shown) is formed, and a planarization process such as a CMP process is performed until the first interlayer insulating layer 31 is exposed to form a source contact 32. Form.

A first etch stop layer 34 and a second interlayer insulating layer 36 are formed on the entire surface of the resultant on which the source contact 32 is formed, and a photoresist pattern is formed on the interlayer insulating layer 36 to define a trench type drain contact. After forming (not shown), an etching process is performed using an etching mask to form a trench-type drain contact hole (not shown) in which the junction region 24a is exposed. An ashing process of removing the photoresist pattern (not shown) is performed. A metal material is formed on the entire surface of the resultant in which the drain contact hole is formed, and the drain contact 40 is formed by performing a planarization process such as a CMP process until the etch stop layer 38 is exposed.

Subsequently, a second etch stop layer 38 and a third interlayer insulating layer 42 are sequentially formed on the resultant product on which the drain contact 40 is formed, and a metal contact is formed in a predetermined region of the formed third interlayer insulating layer 42. A photoresist pattern (not shown) for forming a trench is formed, and the third interlayer insulating layer 42 and the second etch stop layer 38 are etched using the etching mask to form the first, second, third and third layers. 4 Metal wiring trenches MTP1, MTP2, MTP3, and MTP4 are formed.

The first, second, third and fourth metal wiring trenches MTP1, MTP2, MTP3, and MTP4 are trenches for defining regions in which metal wirings, which are bit lines, are to be formed.

Referring to FIG. 2, a carbon-based amorphous oxide film 44 and an in-organic antireflection film 46 are sequentially formed on the entire surface of the resultant product. Subsequently, in order to form the metal contact trench formation pattern on the carbon-based amorphous oxide film 44 and the inorganic antireflection film 46, a photoresist pattern PR is formed on the inorganic antireflection film 46. do.

The carbon-based amorphous oxide film 44 is formed to have a thickness that is greater than that of the buried metal contact trench.                     

In addition, since it is easy to damage the carbon-based amorphous oxide film deposited under the O ₂ treatment, the inorganic anti-reflective film 46 to prevent the carbon-based amorphous oxide film from being damaged during the etching process for forming the contact hole. Will be deposited.

In addition, the carbon-based amorphous oxide film has a selectivity ratio of about 10: 1 higher between the oxide film and the conductive film such as the polysilicon film, and maintains a low reflectance of 0.5% or less for easy CD (critical dimension) control. One characteristic is that the density of the pattern is less affected, so that the nonuniformity of contact formation generated during the metal contact formation process, which is simultaneously formed in the cell region and the peripheral circuit region, in which the intervals between the patterns (gate electrode patterns, etc.) are different from each other, It is possible to solve problems such as a pattern defect and contact open.

On the other hand, the photoresist pattern PR to be formed is a photoresist for forming a conventional metal wiring trench in view of the high etching selectivity of the deposition of the carbon-based amorphous oxide film 44 and the inorganic anti-reflection film 46 It can be lower than the thickness of the pattern, it is possible to implement a finer metal wiring trench than conventional.

Referring to FIG. 3, the inorganic antireflection film 46 is etched using the formed photoresist pattern PR as an etching mask to pattern the inorganic antireflection film 46. Subsequently, the carbon-based amorphous oxide film 44 is etched using the photoresist pattern PR and the inorganic anti-reflective film 46 as an etch mask, and the first, second, third and third layers of the carbon-based amorphous oxide film 44 are etched. The fourth metal wiring trenches MTP1, MTP2, MTP3, and MTP4 are formed, and due to the formation of these patterns, the third interlayer insulating layer 42 and the second etch stop layer 38 of FIG. 1 may be formed. The metallization trenches MTP1, MTP2, MTP3, MTP4 are exposed.

The first metal wiring trench MTP1 is formed in a region where a metal wiring for exposing a source contact on the cell region A is defined, and the second metal wiring trench MTP2 is a drain on the cell region A. The metal wiring for exposing the contact is formed in the region to be defined, and the third metal wiring trench MTP3 is formed in the region in which the metal wiring for exposing the source or drain region on the peripheral circuit region B is defined. The metal contact trench forming pattern MTP4 is formed in a region where a metal wiring for exposing the gate electrode on the peripheral circuit region B is defined.

Referring to FIG. 4, an etching process is performed using the first, third and fourth metal interconnection trenches MTP1, MTP2, and MTP4 formed as etching masks.

As a result, the source contact of the cell region A is exposed, but the second interlayer insulating layer 36 and the first etch stop layer 34 formed on the source contact are etched to be in contact with the upper first metal wiring trench. A metal contact hole MT1 for exposing a source contact is formed, and the second interlayer insulating layer 36, the first etch stop layer 34, and the first interlayer insulating layer 32 are etched to form a source or a drain of a peripheral circuit region ( 24b) An exposure metal contact hole MT3 is formed, and the second interlayer insulating layer 36, the first etch stop layer 34, and the first interlayer insulating layer 32 are etched to expose the gate electrode in the peripheral circuit region. Metal contact holes MT4 are formed, respectively.

The metal contact hole MT3 for exposing the source or drain and the metal contact hole MT4 for exposing the gate electrode are formed by etching the lower layers with the formed third and fourth metal wiring trenches MTP3 and MTP4 as an etch mask. do.

On the other hand, during the etching process using the metal contact holes (MTP1, MTP3, MTP4) as an etching mask, the carbon-based amorphous oxide film 44 functions as an etch stop film.

Referring to FIG. 5, the formed source contact exposure metal contact hole MT1, drain contact exposure metal contact hole MT2, peripheral circuit region source or drain exposure metal contact hole MT3, and peripheral circuit region Source contact exposure is formed by forming a conductive film such as copper or aluminum on the entire surface of the resultant product including the metal contact hole MT4 for gate electrode exposure, and performing a planarization process such as a CMP process until the second interlayer insulating film is exposed. The process of forming the metal wiring M1, the drain contact metal wiring M2, the source or drain exposure metal wiring M3 in the peripheral circuit region and the gate electrode exposure metal wiring M4 in the peripheral circuit region is completed. .

According to the present invention, by depositing the carbon-based amorphous oxide film and the inorganic anti-reflection film and performing an etching process for forming a metal contact hole, the metal contact is formed at the same time in the area between the pattern (gate electrode pattern, etc.) different from each other It is possible to solve problems such as non-uniformity of contact formation, poor pattern, and open contact which are generated during the formation process.

In addition, by depositing a carbon-based amorphous oxide film and applying it to the metal contact hole forming process, the pattern has a small influence on the density of the pattern and has a selective etching ratio of about 10: 1 between the oxide film and the conductive film such as the polysilicon film. The metallization trench can be lower than the thickness of the photoresist pattern to be formed, it is possible to implement a finer metallization trench than conventional.

In addition, the carbon-based amorphous oxide film and the inorganic antireflection film maintain a low reflectance of 0.5% or less, and thus are easier to control the critical dimension (CD) than when the organic antireflection film is used.

As described above, according to the present invention, by depositing the carbon-based amorphous oxide film and the inorganic anti-reflection film and performing an etching process for forming a metal contact hole, the pattern density (gate electrode pattern, etc.) is less affected. There is an effect that can solve problems such as non-uniformity of contact formation, pattern defect, contact open, etc. generated during the metal contact hole forming process formed at the same time between the gaps.

In addition, by depositing a carbon-based amorphous oxide film and applying it to a metal contact hole forming process, the metallization trench has a high selectivity ratio of about 10: 1 between the oxide film and the conductive film such as a polysilicon film. It can be lower than the thickness of the photoresist pattern, there is an effect that can implement a finer metal wiring trench than conventional.

In addition, the carbon-based amorphous oxide film and the inorganic anti-reflection film maintain a low reflectance of 0.5% or less, which is easier to control the critical dimension (CD) than when the organic anti-reflection film is used.

Although the present invention has been described in detail only with respect to specific embodiments, it will be apparent to those skilled in the art that modifications and variations can be made within the scope of the technical idea of the present invention, and such modifications or changes are defined in the claims of the present invention. Will belong.

Claims (13)

A cell region including a first contact plug exposing a first junction region and a second contact plug having a height higher than that of the first contact plug, and a second contact plug exposing a second junction region formed at a region different from the first junction region; Forming a semiconductor substrate provided with a peripheral circuit region having a third junction region formed in a region different from the first and second junction regions; Sequentially forming an amorphous insulating film and an anti-reflection film over the semiconductor substrate; Patterning the anti-reflection film and the amorphous insulating film to form first metal contact holes, second metal contact holes, and third metal contact holes respectively exposing the first contact plug, the second contact plug, and the third junction region, respectively. Doing; And Comprising the steps of completing the process of forming the first metal wiring, the second metal wiring and the third metal wiring by filling the conductive film only in the first, second and third metal contact holes. Wiring formation method. The method of claim 1, wherein the amorphous insulating film A metal wiring forming method for a semiconductor device comprising a carbon-based amorphous oxide film. The method of claim 1, wherein the anti-reflection film A metal wiring formation method for a semiconductor device comprising an inorganic antireflection film. The method of claim 1, wherein the first or second junction region is And forming a source region of said cell region. The method of claim 1, wherein the first or second junction region is And forming a drain region of the cell region. The method of claim 1, wherein the third junction region is And forming a source / drain region of the peripheral circuit region. The method of claim 1, wherein the second contact plug has a height higher than that of the first contact plug. And forming the second contact plug after the at least one interlayer insulating film is formed on the first contact plug. The metal contact hole of claim 1, wherein the third metal contact hole exposes the third junction region. And forming a height of the second contact plug, the height of the amorphous insulating film, and the anti-reflection film. The method of claim 1 or claim 7, wherein the first metal contact hole And a height of the height of the interlayer insulating film formed on the first contact plug and the height of the amorphous insulating film and the anti-reflection film are about the sum of the heights. The source region and the drain region of the cell region, the source / drain region of the peripheral circuit region and the gate electrode pattern are respectively provided. Forming a first contact insulating layer on the semiconductor substrate, patterning the first insulating interlayer to form a source contact hole exposing the source region of the cell region, and then forming a conductive layer to fill only the inside of the source contact hole, thereby forming a source contact plug. Forming a; A drain contact sequentially forming a first etch stop layer and a second interlayer insulating layer on a resultant on which the source contact plug is formed, and patterning the second interlayer insulating layer and the first etch stop layer to expose a drain region of the cell region Forming a drain contact plug by forming a conductive layer to fill only the inside of the drain contact hole after forming the hole; After sequentially forming the second etch stop layer and the third interlayer insulating layer on the resultant on which the drain contact plug is formed, a region in which metal wiring to be connected to the source contact plug is to be formed, and a metal wiring to be connected to the drain contact plug is to be formed. A region, a region in which metal wiring to be connected to the source / drain region of the peripheral circuit region, and a region in which a metal wiring to be connected to the gate electrode pattern of the peripheral circuit region are formed are formed on the third interlayer insulating layer and the second etch stop layer. Patterning each; Amorphous insulating film on the entire surface of the resultant And forming an anti-reflection film sequentially, a region in which metal wiring to be connected to the source contact plug is formed, a region in which a metal wiring to be connected to the drain contact plug are formed, and a metal wiring to be connected to a source / drain region of the peripheral circuit region. Patterning a region to be formed and a region in which a metal wiring to be connected to a gate electrode pattern of the peripheral circuit region is formed, on the amorphous insulating layer; The second insulating interlayer and the first etch stop layer are etched to form a first metal contact hole to be connected to the source contact plug by using the amorphous insulating layer patterned with the regions as an etch stop layer and an etch mask, and the drain contact. Forming a second metal contact hole to be connected to the plug, and etching the second interlayer insulating film, the first etch stop layer, and the first interlayer insulating film to form a third metal contact hole to be connected to the source / drain region of the peripheral circuit region. Etching the second interlayer insulating layer, the first etch stop layer, and the first interlayer insulating layer to form a fourth metal contact hole to be connected to the gate electrode pattern of the peripheral circuit region; And Completing the process of forming the first metal wiring, the second metal wiring, the third metal wiring and the fourth metal wiring by filling the conductive film only in the first, second, third and fourth metal contact holes. Metal wiring forming method of a semiconductor device comprising a. The method of claim 10, wherein the amorphous insulating film A metal wiring forming method for a semiconductor device, characterized in that the carbon-based amorphous oxide film. The method of claim 10, wherein the anti-reflection film A metal wiring formation method for a semiconductor device comprising an inorganic antireflection film. The method of claim 10, wherein the metal wiring to be connected to the source contact plug is to be formed, the metal wiring to be connected to the drain contact plug is to be formed, the metal wiring to be connected to the source / drain area of the peripheral circuit region, and Patterning the region where the metal wiring to be connected to the gate electrode pattern of the peripheral circuit region is to be formed on the amorphous insulating film, A region in which a metal wiring to be connected to the source contact plug is to be formed, a region in which a metal wiring to be connected to the drain contact plug is to be formed, a region in which a metal wiring to be connected to a source / drain region of the peripheral circuit region is formed, and the Forming patterns to define regions in which metal wirings to be connected to gate electrode patterns of the peripheral circuit regions are to be formed; Etching and patterning the anti-reflection film using the patterns as an etching mask; And And etching the amorphous insulating layer using the patterns and the patterned anti-reflective layer as an etch mask.

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