KR20060080377A - Thin film transistor array panel - Google Patents

Abstract

A thin film transistor array panel according to the present invention includes a gate line formed on a substrate, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, a data line and a drain electrode formed on the semiconductor layer, A lower passivation layer formed on the data line and the drain electrode, a color filter formed on the lower passivation layer, an upper passivation layer covering the color filter, a pixel electrode formed on the upper passivation layer, and a top passivation layer formed on the upper passivation layer First and second contact auxiliary members connected to gate lines and ends of the data line through first and second contact holes, respectively, and the upper passivation layer is connected to the first and second contact holes, respectively. A plurality of inclined surface portions, the first and second contacts The auxiliary member completely covers the plurality of inclined surface portions.

Color filter, upper protective film, COA, contact hole, organic insulating film, thin film transistor, slit

Description

Thin Film Transistor Display Panels {THIN FILM TRANSISTOR ARRAY PANEL}

1 is a layout view of a thin film transistor array panel according to a first exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel of FIG. 1 taken along the line II-II ′ of FIG. 1.

FIG. 3A is a layout view at the first stage of a method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 according to one embodiment of the present invention.

FIG. 3B is a cross-sectional view of the thin film transistor array panel of FIG. 3A taken along line IIIb-IIIb'-IIIb'-IIIb ".

4A is a layout view of a thin film transistor array panel in the next step of FIG. 3A.

4B is a cross-sectional view of the thin film transistor array panel of FIG. 4A taken along a line IVb-IVb'-IVb'-IVb '.

FIG. 5A is a layout view of a thin film transistor array panel in the next step of FIG. 4A.

FIG. 5B is a cross-sectional view of the thin film transistor array panel of FIG. 5A taken along the line Vb-Vb'-Vb'-Vb ".

6A is a layout view of a thin film transistor array panel in the next step of FIG. 5A.

FIG. 6B is a cross-sectional view of the thin film transistor array panel of FIG. 6A taken along the line VIb-VIb'-VIb'-VIb ".                 

FIG. 7 is a cross-sectional view of the thin film transistor array panel of FIG. 6A taken along the line VIb-VIb'-VIb'-VIb ", and is taken along the line of FIGS. 6A and 6B.

FIG. 8 is a cross-sectional view of the thin film transistor array panel of FIG. 6A taken along the line VIb-VIb'-VIb'-VIb ", and is taken along the line of FIG.

9A is a layout view of a thin film transistor array panel in the next step of FIG. 6A.

FIG. 9B is a cross-sectional view of the thin film transistor array panel of FIG. 9A taken along the line IXb-IXb'-IXb'-IXVb ".

FIG. 10 is a cross-sectional view of the thin film transistor array panel of FIG. 9A taken along a line IXb-IXb'-IXb'-IXVb ", and is taken in the next step of FIG. 9B.

11 is a layout view of a TFT array panel for an LCD according to another embodiment of the present invention.

FIG. 12 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 11 taken along the line XII-XII'-XII'-XII ".

* Description of symbols on the main parts of the drawings *

110: insulating substrate, 121: gate line, 151: semiconductor, 171: data line, 190: pixel electrode, R, G, B: color filter, 81, 82: contact auxiliary member, 180a, 180b: protective film

The present invention relates to a thin film transistor array panel.                         

The liquid crystal display is one of the most widely used flat panel displays, and includes a field generating electrode that generates an electric field such as a pixel electrode and a common electrode, and a liquid crystal layer filled in the gap between the display panel and the display panel having a gap therebetween. It includes. In such a liquid crystal display, an electric field is formed on the liquid crystal layer by applying a voltage to two field generating electrodes to determine the alignment of liquid crystal molecules and to adjust the polarization of incident light to display an image.

The liquid crystal display includes a plurality of pixels including a field generating electrode and a thin film transistor connected thereto and arranged in a matrix form, and a plurality of signal lines transferring signals thereto. The signal line includes a gate line for transmitting a scan signal and a data line for transmitting a data signal, and each pixel includes a color filter for displaying color in addition to the field generating electrode and the thin film transistor.

In order to improve the luminance of such a liquid crystal display device, it is important to secure a high aperture ratio of the panel. For this purpose, the color filter is formed on the same display panel as the thin film transistor, thereby minimizing the process margin between the two display panels, thereby improving the aperture ratio. In order to form satisfactorily, the organic insulating film excellent in the planarization characteristic is formed.

When the organic insulating layer is used, the separation distance between the data line and the pixel electrode can be secured by a predetermined distance or more, for example, about 3 μm or more, so that the data line and the pixel electrode can be superimposed to increase the aperture ratio.

However, when the organic insulating film is used, the thickness of the insulating film becomes thick. As a result, contact failure occurs in a contact portion in which a part of the organic insulating film is etched for contact with another layer. That is, the step difference between the layer positioned above the organic insulating layer and the layer positioned below the organic insulating layer is large, so that a portion of the organic insulating layer is disconnected or not normally connected.

To this end, the thickness of the organic insulating film formed near the contact portion is gradually reduced to have a smooth profile. However, a portion of the organic insulating layer may be excessively etched at a portion where the thickness of the organic insulating layer becomes thin during the subsequent process to adversely affect the layer under the organic insulating layer. In particular, during the etching process performed to form the pixel electrode, when the data line and the like disposed under the organic insulating layer are exposed, the data line and the like are disconnected, thereby causing a problem in signal transmission.

Therefore, the technical problem to be achieved by the present invention is to improve the reliability by reducing the disconnection failure of the signal line.

A thin film transistor array panel according to an aspect of the present invention includes a gate line formed on a substrate, a gate insulating film formed on the gate line, a semiconductor layer formed on the gate insulating film, a data line formed on the semiconductor layer, A lower passivation layer formed on the drain electrode, the data line and the drain electrode, a color filter formed on the lower passivation layer, an upper protection layer covering the color filter, a pixel electrode formed on the upper passivation layer, and the upper passivation layer And first and second contact auxiliary members formed thereon and connected to first ends of the gate line and the data line through first and second contact holes, respectively, wherein the upper passivation layer is formed of the first and second contacts. A plurality of inclined surface portions connected to the holes, respectively; And the second contact assistant member completely covers the plurality of inclined surface portions.

The upper passivation layer includes a plurality of first planarization portions adjacent to the first and second contact holes and connected to the plurality of inclined surface portions, and a plurality of second planarization portions respectively connected to the plurality of inclined surface portions. The first and second contact assistants may extend to the second planarization part.

The upper protective film is preferably an organic insulating film.

Preferably, the first and second contact auxiliary members are connected to the gate line or the data line and cover more second planarization portions than the end portions of the gate line and the end portion of the data line.

The color filter may express red, green, and blue.

The semiconductor device may further include an ohmic contact layer formed between the semiconductor and the data line.

The semiconductor and the ohmic contact layer may extend along the shape of the data line.

Preferably, the drain electrode is connected to the pixel electrode through a third contact hole.

It may further include a conductor for a storage capacitor made of the same layer as the data line and overlapping the gate line.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A thin film transistor array panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a layout view illustrating a structure of a liquid crystal display according to a first exemplary embodiment of the present invention, and FIG. 2 illustrates a structure of a liquid crystal display including the thin film transistor array panel of FIG. 1, taken along line II-II ′ of FIG. 1. It is a cross-sectional view shown.

The liquid crystal display according to the exemplary embodiment may include a lower panel 100, an upper panel 200 facing the lower panel, a liquid crystal layer 300 interposed between the lower panel 100 and the upper panel 200. Include.

In addition, the liquid crystal display according to the exemplary embodiment is disposed between the polarizers (not shown) attached to the outer surfaces of the upper and lower display panels 100 and 200, and is disposed between the display panels 100 and 200 and the polarizers, and the liquid crystal layer 300. It may include a compensation plate (not shown) for compensating the phase of the light passing through).

In this case, the liquid crystal layer 300 may be aligned in a vertical alignment method or a twisted nematic alignment method, and may have a bent arrangement symmetrically with respect to the center planes of the two substrates 110 and 210. The transmission axes of the polarizing plates may be disposed perpendicular to or parallel to each other.

The upper panel 200 is formed on the upper substrate 210 made of a transparent insulating material such as glass, the upper electrode 210, a common electrode 270 made of a transparent conductive material such as ITO or IZO, and applied thereon. The alignment film 21 is included.

Referring to the thin film transistor array panel 100, a plurality of gate lines 121 for transmitting a gate signal are formed on an insulating substrate 110 such as transparent glass. Each gate line 121 mainly extends in a horizontal direction and has an area for connection with a plurality of gate electrodes 124, a plurality of projections 127 protruding downward, and another layer or an external driving circuit. It includes a wide end 129. The driving circuit may be mounted on a flexible printed circuit film attached to the substrate 110 or directly mounted on the substrate 110.

The gate line 121 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, molybdenum (Mo) or molybdenum It may be made of molybdenum-based metals such as alloys, chromium (Cr), tantalum (Ta), and titanium (Ti). However, the gate line 121 may have a multilayer structure including two conductive layers (not shown) having different physical properties. One of the conductive layers is made of a low resistivity metal, for example, an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce a signal delay or voltage drop of the gate line 121. The other conductive layer may be made of another material, particularly a material having excellent physical, chemical and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metal, chromium, tantalum, or titanium. . A good example of such a combination is a chromium bottom film and an aluminum top film, and an aluminum bottom film and a molybdenum top film.

The side of the gate line 121 is inclined with respect to the surface of the substrate 110, the inclination angle is preferably about 30 ~ 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (a-Si), polycrystalline silicon, or the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction from which a plurality of projections 154 extend toward the gate electrode 124. In addition, the linear semiconductor 151 increases in width near the point where the linear semiconductor 151 meets the gate line 121 to cover a large area of the gate line 121.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor 151. The linear ohmic contact 161 has a plurality of protrusions 163, and the protrusion 163 and the island-type ohmic contact 165 are paired and positioned on the protrusion 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30-80 °.

The plurality of data lines 171, the plurality of drain electrodes 175, and the plurality of storage capacitor conductors are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140. 177 is formed.

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. Each data line 171 has a wide end portion 179 for connecting a plurality of source electrodes 173 extending toward the gate electrode 124 with another layer or an external device.

The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to each other with respect to the gate electrode 124. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. A protrusion 154 is formed between the electrode 173 and the drain electrode 175.                     

The data line 171, the drain electrode 175, and the conductor 177 for the storage capacitor are preferably made of a refractory metal such as molybdenum, chromium, tantalum, titanium, or an alloy thereof. However, these may also have a multilayer film structure including a conductive film having a low resistance and a conductive film having good contact characteristics. Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

Similarly to the gate line 121, the data line 171 and the drain electrode 175 are inclined at an angle of about 30 to 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 above and serve to lower the contact resistance. The linear semiconductor 151 has a portion exposed between the source electrode 173 and the drain electrode 175 and not covered by the data line 171 and the drain electrode 175. The linear semiconductor 151 also has a width of the linear semiconductor 151 smaller than that of the data line 171 in most places, but as described above, the width of the linear semiconductor 151 is increased to smooth the profile of the surface. Disconnection of the data line 171 can be prevented.

A lower passivation layer 180a made of silicon nitride or silicon oxide is formed on the data line 171, the drain electrode 175, the storage capacitor conductor 177, and the exposed semiconductor 151.

Red, green, and blue color filters R, G, and B are formed on the lower passivation layer 180a. Each of the color filters R, G, and B extends in the longitudinal direction. However, instead of the color filters R, G, and B, a rectangular color filter may be formed in an area partitioned by the gate line 121 and the data line 171.

An upper passivation layer 180b is formed on the lower passivation layer 180a to cover the color filters R, G, and B, and includes silicon nitride or silicon oxide, such as the lower passivation layer 180a. The upper passivation layer 180b is made of an organic insulating layer, but may be made of another material.

The lower and upper passivation layers 180a and 180b respectively include a plurality of contact holes exposing one end portion 179 of the data line 171, the drain electrode 175, and at least a portion of the storage capacitor conductor 177. contact holes 182, 185, and 187 are provided. In addition, the lower and upper passivation layers 180a and 180b and the gate insulating layer 140 are provided with a plurality of contact holes 181 exposing the end portion 129 of the gate line 121. On the other hand, the color filters R, G and B also have openings 235 and 237 exposing the drain electrode 175 and the conductor 177 for the storage capacitor. The openings 235 and 237 of B) are larger than the contact holes 185 and 187 of the protective films 180a and 180b. However, the contact holes 185 and 187 of the upper passivation layer 180b may be larger than the openings 235 and 237, in which case a stepped sidewall is formed. The upper passivation layer 180a around the contact holes 181, 182, 185, and 187 is gradually reduced in thickness from a predetermined portion to the contact holes 181, 182, 185, and 187, so that these contact holes 181, 182, 185, The sidewalls of 187 have a gentle profile, that is, the upper passivation layer 180a around the contact holes 181, 182, 185, and 187 has substantially the thinnest first planarization portion, inclined surface portion, and substantially thickness. Includes the thickest second planarization portion.

A plurality of pixel electrodes 190 made of IZO or ITO and a plurality of contact auxiliary members 81 and 82 are formed on the passivation layers 180a and 180b.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 and the storage capacitor conductor 177 through the openings 235 and 237 and the contact holes 185 and 187, respectively, from the drain electrode 175. The data voltage is applied and the data voltage is transferred to the conductor 177.

The pixel electrode 190 to which the data voltage is applied generates an electric field together with the common electrode 270 of the upper panel 200 to which the common voltage is applied, thereby generating liquid crystal molecules of the liquid crystal layer 300 between the two display panels 100 and 200. Rearrange them.

In addition, as described above, the pixel electrode 190 and the common electrode 270 form a capacitor (hereinafter referred to as a “liquid crystal capacitor”) to maintain the applied voltage even after the thin film transistor is turned off. There are other capacitors connected in parallel with the liquid crystal capacitor, which are called maintenance capacitors. The storage capacitor is formed by overlapping the pixel electrode 190 and the neighboring gate line 121 (hereinafter, referred to as a shear gate line). The storage capacitor is connected with the gate line 121 to increase the capacitance of the storage capacitor, that is, the storage capacitance. An extended protrusion 127 is provided to increase the overlapped area, while a conductive capacitor conductor 177 connected to the pixel electrode 190 and overlapped with the protrusion 127 is placed under the protective film 180 to provide a distance therebetween. You can get close. Alternatively, a storage capacitor may be formed by overlapping a separate storage electrode line (not shown) and the pixel electrode 190.

The pixel electrode 190 also overlaps the neighboring gate line 121 and the data line 171 to increase the aperture ratio, but may not overlap.

The contact auxiliary members 81 and 82 are connected to the exposed end portions 129 and 179 of the gate line 121 and the data line 171 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 compensate for and protect the adhesion between the end portions 129 and 179 of the gate line 121 and the data line 171 and the external device. The contact auxiliary members 81 and 82 completely cover not only the contact holes 181 and 182 but also the first flattening portion and the inclined surface portion, and then extend to a predetermined portion of the second flattening portion. In particular, the contact auxiliary members 81 and 82 of the data line 171 and the end portions 179 and 129 of the gate line 121 connected to the data line 171 or the gate line 121 are opposite to each other. It extends longer than the contact auxiliary members 81 and 82 of. In the present embodiment, the thickness of the first planarization portion of the upper passivation layer 180b is about 10000 GPa or less, and the thickness of the second planarization portion is about 30,000 GPa. One portion of the contact assisting members 81 and 82 preferably extends between the end of the color filters R, G and B and the second flattening portion.

Finally, an alignment layer 11 is formed on the pixel electrode 190, the contact auxiliary members 81 and 82, and the passivation layer 180.

In the liquid crystal display according to the exemplary embodiment of the present invention, the opposing display panel 200 includes only the common electrode 270 and the alignment layer 21 formed on the entire surface of the substrate 210.

Next, a method of manufacturing the thin film transistor array panel for the liquid crystal display device illustrated in FIGS. 1 and 2 will be described with reference to FIGS. 3A to 7B.

1 is a layout view of a thin film transistor array panel according to a first exemplary embodiment of the present invention, and FIG. 2 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel of FIG. 1 taken along line II-II ′ of FIG. 1. 3A is a layout view at the first stage of the method of manufacturing the thin film transistor array panel shown in FIGS. 1 and 2 according to one embodiment of the present invention. 3B is a cross-sectional view of the thin film transistor array panel of FIG. 3A taken along line IIIb-IIIb'-IIIb'-IIIb ". FIG. 4A is a layout view of the thin film transistor array panel in the next step of FIG. 3A, and FIG. 4B is a view of FIG. The thin film transistor array panel is cut along the line IVb-IVb'-IVb'-IVb ". FIG. 5A is a layout view of a thin film transistor array panel in the next step of FIG. 4A, and FIG. 5B is a cross-sectional view of the thin film transistor array panel of FIG. 5A taken along the line Vb-Vb′-Vb′-Vb ″. Fig. 6B is a cross-sectional view of the thin film transistor array panel of Fig. 6A taken along the line VIb-VIb'-VIb'-VIb '. FIG. 7 is a cross-sectional view of the thin film transistor array panel of FIG. 6A taken along the line VIb-VIb'-VIb'-VIb ", and is a view of the next step of FIGS. 6A and 6B. FIG. 8 is a view of the thin film transistor array panel of FIG. 6A. FIG. 7 is a cross-sectional view taken along the line VIb-VIb'-VIb'-VIb ", and is a view in the next step of FIG. 7. 9A is a layout view of a thin film transistor array panel in the next step of FIG. 6A. FIG. 9B is a cross-sectional view of the thin film transistor array panel of FIG. 9A taken along the line IXb-IXb'-IXb'-IXVb '. FIG. 10 is a cross-sectional view of the thin film transistor array panel of FIG. 9B is a cross sectional view taken along the line, and is a view at the next step of FIG. 9B.                     

First, as shown in FIGS. 3A and 3B, a conductive film is laminated on an insulating substrate 110 made of transparent glass, such as sputtering, and then etched to include a gate electrode 124 and a protrusion 127. The gate line 121 is formed.

Next, as shown in FIGS. 4A and 4B, a three-layer film of a gate insulating layer 140, intrinsic amorphous silicon, and an impurity amorphous silicon layer is successively stacked, and an impurity amorphous silicon layer and Photo-etching the intrinsic amorphous silicon layer forms a linear intrinsic semiconductor 151 including a plurality of linear impurity semiconductors 164 and protrusions 154.

5A and 5B, a plurality of data lines 171 including the source electrode 173, a plurality of drain electrodes 175, and a plurality of holdings are formed by stacking and patterning a metal film by sputtering or the like. The conductor 177 for a capacitor is formed.

The plurality of linear ohmic contacts including the protrusion 163 may be removed by removing portions of the impurity semiconductor 164 that are not covered by the data line 171, the drain electrode 175, and the storage capacitor conductor 177. 161 and the plurality of islands of ohmic contact 165 are completed, while the portion of the intrinsic semiconductor 151 underneath is exposed. In order to stabilize the surface of the portion of the intrinsic semiconductor 151, oxygen plasma is preferably followed.

Next, as shown in FIGS. 6A and 6B, silicon nitride is deposited on the insulating substrate 110 by chemical vapor deposition (CVD) to form a lower passivation layer 180a, and then red and green layers. , Blue filters R, G, and B are formed. The color filter coats a photosensitive film for a filter containing a pigment. At this time, the photosensitive film is formed by applying a photopolymerizable photosensitive composition including a photopolymerization initiator, a monomer, a binder, and the like and a non-aqueous dispersion containing one of red, green, and blue pigments.

Thereafter, the photomask for color filters is exposed and developed using an optical mask to form a color filter. This process is performed for each color filter. The openings 235 and 237 exposing the drain electrode 175 and the storage capacitor conductor 177 may be formed in the red, blue, and green filters, and may be patterned in a subsequent process.

Subsequently, as shown in FIG. 7, the organic insulating layer 800 is formed by stacking the organic insulating layer on the red, green, and blue filters R, G, and B and the exposed passivation layer 180a by chemical vapor deposition. Subsequently, the photoresist layer 70 is coated on the organic insulating layer 800 to a thickness of 1 μm to 2 μm.

The photomask 50 is composed of a transparent substrate 51 and an opaque light shielding layer 52 thereon, the light-transmitting region D having a width of the light shielding layer 52 not less than a predetermined width and a light shielding layer having a predetermined width or more ( 52 and a slit-like transflective area F whose width or spacing of the light shielding layer 52 is equal to or less than a predetermined value.

The transmissive region D includes the end portion of the gate line 121 and the end portions 129 and 179 of the data line 171, approximately the center portion of the extension portion 177 of the drain electrode 175, and the conductor for the storage capacitor. The semi-transmissive region F faces the end portion 129 of the gate line 121, the end portion 179 of the data line 171, and the drain electrode 175. It faces around the center part of the extension part 177 and about the center part of the conductor 177 for holding capacitors, and the other part faces the light-shielding area E. As shown in FIG.

When the photosensitive film 60 is irradiated with light through the photomask 50 and developed, as shown in FIG. 8, a thick first portion 62 and a thin second portion 64 remain. Corresponds to the remaining parts except the hatched parts in 7.

The thickness of the developed photosensitive film 60 varies depending on the position. In FIG. 8, the photosensitive film 60 is composed of three parts whose thickness becomes smaller. That is, in the first portion facing the light blocking region E, the thickness of the photosensitive film 60 does not decrease, and in the second portion facing the transflective region F, the photosensitive film 60 is reduced by a predetermined thickness. . In addition, in the third part facing the transmission region D, all of the corresponding photoresist layer 60 is removed to have a thickness of zero, and the organic insulating layer 800 below is exposed. The ratio of the thicknesses of the first part and the second part depends on the process conditions in the subsequent process.

As described above, when the thickness of the photoresist film is changed according to the position by providing a translucent area, the lattice pattern or the thin film having a medium transmittance or a medium thickness in addition to the slit pattern is also present in the transflective area. It may be provided. As shown in Fig. 7, when using the slit pattern, it is preferable that the width of the slit and the interval between the slits are smaller than the resolution of the exposure machine used for the photographing process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist film with a conventional mask having only a transmissive area and a light shielding area, and then reflowing so that the photoresist film flows into an area where no photoresist film remains.                     

Given the appropriate process conditions for the remaining photoresist portions 62, 64, the lower layers can be selectively etched due to the difference in thickness of the photoresist portions 62, 64. Accordingly, as shown in FIGS. 9A and 9B, the upper passivation layer 180b having the plurality of contact holes is formed through a series of etching steps. That is, the upper and lower passivation layers 180b and 180a respectively have an end portion 179 of the data line 171 and an approximately center portion of the extension portion 177 of the drain electrode 175 and the conductor 177 for the storage capacitor. The contact holes 182, 185 and 187 exposing the center portion are formed, and the contact holes 181 exposing the end portion 129 of the gate line 121 are formed. At this time, the amount of light transmitted varies according to the slit size or interval of the transflective region F, so that the etching degree of the upper passivation layer 180b may be adjusted, so that the thickness of the final lower passivation layer 180b may be changed. That is, the upper passivation layer 180b may be formed of the first planarizing portion, semi-transmissive region F, which is immediately adjacent to the contact holes 181 and 182 and substantially thinnest in the region facing the transflective region F. An inclined surface portion inclined at a predetermined angle among the regions facing each other, and a portion facing the light blocking region E and substantially thickest in thickness of the lower passivation layer 180b includes the second flattening portion.

Next, as shown in FIG. 10, a transparent conductive film 90 such as IZO or ITO is formed, a photoresist PR having a predetermined pattern is applied thereon, and then exposed and exposed to the pixel electrode 190 and the contact assistant member. (81, 82) are formed. In the case of IZO, a product called indium x-metal oxide (IDIXO) manufactured by Idemitsu Co., Ltd. can be used as a target, and includes In ₂ O ₃ and ZnO, and zinc occupies about 15 indium and zinc. It is preferably in the range of -20 atomic%. In addition, the sputtering temperature of IZO is preferably 250 ° C. or lower to minimize contact resistance with other conductors.

In this case, the plurality of contact auxiliary members 81 and 82 completely cover not only the contact holes 181 and 182 but also the first planarization portion and the inclined surface portion of the upper passivation layer 180b, and further extend to a portion of the second planarization portion. In the plurality of contact auxiliary members 81 and 82, portions connected to the gate line 121 and the data line 171 extend more than the opposite portions.

In this manner, the plurality of contact auxiliary members 81 and 82 extend beyond the contact holes 181 and 182 through the first flattening portion and the inclined surface to the second flattening portion. For this reason, even if the metal film below the first flattening part is exposed, the signal transmission failure is prevented due to the contact auxiliary members 81 and 82 applied thereon.

Thereafter, a process of forming a substrate spacer (not shown) and the alignment layer 11 may be added. The substrate spacer may be formed on the upper insulating substrate 110.

Next, the unit pixel structure of the TFT panel for liquid crystal display according to another exemplary embodiment of the present invention will be described in detail with reference to FIGS. 11 and 12.

FIG. 11 is a layout view of a thin film transistor array panel for a liquid crystal display according to another exemplary embodiment. FIG. 12 is a cross-sectional view of the thin film transistor array panel illustrated in FIG. 11 taken along the line XII-XII′-XII′-XII ″. .

As shown in Figs. 11 and 12, the layered structure of the thin film transistor array panel for liquid crystal display device according to the present embodiment is generally the same as the layered structure of the thin film transistor array panel for liquid crystal display device shown in Figs. . That is, the plurality of linear semiconductors including the plurality of gate lines 121 including the plurality of gate electrodes 124 is formed on the substrate 110, and the gate insulating layer 140 and the plurality of protrusions 154 thereon. 151, a plurality of linear ohmic contact members 161 each including a plurality of protrusions 163, and a plurality of island type ohmic contact members 165 are sequentially formed. A plurality of data lines 171 including a plurality of source electrodes 173 and a plurality of drain electrodes 175 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140, and the lower passivation layer 180a is formed thereon. ) Is formed.

Color filters R, B, and G are formed on the lower passivation layer 180a, and an upper passivation layer 180b made of an organic insulating layer is formed on the color filters R, G, and B.

A plurality of contact holes 181, 182, 185, and 187 are formed in the passivation layers 180a and 180b and / or the gate insulating layer 140, and the plurality of pixel electrodes 190 and the plurality of contact assistants are formed on the passivation layer 180b. Members 81 and 82 are formed.

However, unlike the thin film transistor array panel shown in FIGS. 1 and 2, the thin film transistor array panel according to the present embodiment is electrically connected to the gate line 121 on the same layer as the gate line 121 instead of having an extension portion on the gate line 121. The storage capacitor is formed by overlapping the drain electrode 175 with the plurality of storage electrode lines 131 separated by the drain electrode 175. The storage electrode line 131 receives a predetermined voltage such as a common voltage from the outside, and the storage electrode line 131 may be omitted when the storage capacitor generated due to the overlap of the pixel electrode 190 and the gate line 121 is sufficient. In order to maximize the aperture ratio of the pixel, the pixel may be disposed at an edge of the pixel area.

The semiconductor 151 has a planar shape substantially the same as that of the data line 171, the drain electrode 175, and the ohmic contacts 161 and 165, except for the protrusion 154 where the thin film transistor is located. . In detail, the linear semiconductor 151 may include the source electrode 173 and the drain electrode 175 in addition to the data line 171, the drain electrode 175, and the portions below the ohmic contacts 161 and 165. ) Has an exposed portion between them.

As described above, since the contact auxiliary member extends beyond the inclined surface portion of the lower passivation layer to the flattening portion, a part of the lower passivation layer is excessively etched so that even if the signal line of the lower data line or gate line is exposed, As a result, the signal line is prevented from being exposed to the outside. This reduces signal line defects and increases reliability.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

Claims (9)

A gate line formed on the substrate, A gate insulating film formed on the gate line, A semiconductor layer formed on the gate insulating film, A data line and a drain electrode formed on the semiconductor layer; A lower passivation layer formed on the data line and the drain electrode; A color filter formed on the lower passivation layer, The color filter is covered with an upper protective film, A pixel electrode formed on the upper passivation layer, and First and second contact auxiliary members formed on the upper passivation layer and connected to end portions of the gate line and the data line through first and second contact holes, respectively. Including, The upper passivation layer includes a plurality of inclined surface portions connected to the first and second contact holes, respectively. The first and second contact assistant members completely cover the plurality of inclined surface portions. Thin film transistor array panel. In claim 1, The upper passivation layer includes a plurality of first planarization portions adjacent to the first and second contact holes and connected to the plurality of inclined surface portions, and a plurality of second planarization portions respectively connected to the plurality of inclined surface portions. , The first and second contact assistants extend to the second planarization part. In claim 2, The upper passivation layer is an organic insulating layer. In claim 3, The first and second contact assistants may be connected to the gate line or the data line and cover more second planarization portions of the gate line or the data line than the end portion of the gate line and the end portion of the data line. In claim 1, The color filter is a thin film transistor array panel representing red, green, blue. In claim 1, A thin film transistor array panel further comprising an ohmic contact layer formed between the semiconductor and the data line. In claim 5, The semiconductor and the ohmic contact layer extend along the shape of the data line. In claim 1, The drain electrode is connected to the pixel electrode through a third contact hole. In claim 1, The thin film transistor array panel of claim 1, further comprising a conductor for a storage capacitor formed of the same layer as the data line and overlapping the gate line.

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