KR20060082096A - Thin film transistor array panel - Google Patents

Abstract

The present invention provides a thin film transistor array panel in which a color filter is formed in a test element group (TEG) of a thin film transistor array panel.

By forming a TEG capable of measuring the resistance and capacitance of the pixel including the color filter, it is possible to predict a difference in characteristics generated due to the presence of the color filter, thereby making the pixel design accurate and reducing defects.

TEG, Color Filter, Resistance, Capacitance, Test

Description

Thin Film Transistor Display Panels {THIN FILM TRANSISTOR ARRAY PANEL}

1 is a layout view of a thin film transistor array panel according to an exemplary embodiment of the present invention.

FIG. 2 is a cross-sectional view of the liquid crystal display including the thin film transistor array panel of FIG. 1 taken along the line II-II′-II ″ of FIG. 1.

3 is a layout view of a test element group (TEG) formed in a thin film transistor array panel according to an exemplary embodiment of the present invention.

4 is a diagram illustrating a region in which a TEG (Test Element Group) may be formed in a thin film transistor array panel according to an exemplary embodiment of the present invention.

5 is a cross-sectional view of a test element group (TEG) for measuring contact resistance between a data line and a pixel electrode according to an exemplary embodiment of the present invention.

6 is a cross-sectional view of a test element group (TEG) for measuring capacitance between a gate line and a pixel electrode according to an exemplary embodiment of the present invention.

FIG. 7 is a diagram illustrating a cross section of a TEG (Test Element Group) for measuring capacitance between a data line and a pixel electrode according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

10: display area 20: pad area

100: thin film transistor array panel 110: insulating substrate                 

121: gate line 124: gate electrode

140: gate insulating film 151, 154: semiconductor

171: data line 173: source electrode

175: drain electrode 177: holding conductor

180a: lower passivation layer 180b: upper passivation layer

230: color filter 182, 185, 187: contact hole

190: pixel electrode

50: TEG (Test Element Group) 55: Individual TEG

197: pads for TEGs 186 and 188: TEG contact holes

The present invention relates to a thin film transistor array panel.

The liquid crystal display is one of the most widely used flat panel displays, and includes a field generating electrode that generates an electric field such as a pixel electrode and a common electrode, and a liquid crystal layer filled in the gap between the display panel and the display panel having a gap therebetween. It includes. In such a liquid crystal display, an electric field is formed on the liquid crystal layer by applying a voltage to two field generating electrodes to determine the alignment of liquid crystal molecules and to adjust the polarization of incident light to display an image.

The liquid crystal display includes a plurality of pixels including a field generating electrode and a thin film transistor connected thereto and arranged in a matrix form, and a plurality of signal lines transferring signals thereto. The signal line includes a gate line for transmitting a scan signal and a data line for transmitting a data signal, and each pixel includes a color filter for displaying color in addition to the field generating electrode and the thin film transistor.

The gate line, the data line, the pixel electrode, and the thin film transistor are disposed on one of two display panels, and the other display panel is generally provided with a common electrode and a color filter. However, in some cases, the color filter is formed on the same display panel as the thin film transistor. In this case, a difference occurs with the conventional liquid crystal display.

In the thin film transistor array panel, a test element group (TEG) is formed to easily measure the characteristics, capacitance, and resistance of the thin film transistor.

However, when the color filter is formed on the thin film transistor array panel, the difference between the actual resistance and the capacitance occurs when the resistance and the capacitance are measured by using a conventional test element group (TEG). This is because an additional color filter is formed so that the dielectric constant between layers changes.

The resistance and capacitance values measured in the TEG (Test Element Group) cannot be used to predict the characteristics of the thin film transistor of the pixel.

An object of the present invention is to provide a thin film transistor array panel that can accurately measure resistance and capacitance through a test element group (TEG) even when a color filter is formed on the thin film transistor array panel.

In order to solve this problem, the present invention provides a thin film transistor array panel in which a color filter is formed in a test element group (TEG) of the thin film transistor array panel.

Specifically, a pixel including a gate line, a data line, a thin film transistor, a color filter, and a pixel electrode, and is formed through the same material and process as that of the pixel, and includes a first pad, a second pad, the first pad, and the second pad. It relates to a thin film transistor array panel including a test element group (TEG) including a stacked structure formed between pads,

The TEG is preferably formed in an area of the mother glass except for the display area and the pad area.

The TEG is stacked in order of a data line, a passivation layer, a color filter, and a pixel electrode, and has a stacked structure in which the pixel electrode is connected to the data line through an opening formed in the passivation layer and the color filter. The pad may be connected to the data line, and the second pad may be connected to the pixel electrode.

Preferably, the resistance is measured by applying current to the first and second pads.

It is preferable to further include a second passivation layer between the color filter and the pixel electrode,

The TEG has a stacked structure in which a gate line, a gate insulating film, a protective film, a color filter, and a pixel electrode are stacked in order, wherein the first pad is connected to the gate line, and the second pad is connected to the pixel electrode. Desirable,                     

After applying a voltage to the first and second pads, it is preferable to measure the amount of change in current over time, and integrate the value to measure capacitance.

It is preferable to further include a second passivation layer between the color filter and the pixel electrode,

Preferably, the TEG has a layered structure in which data lines, passivation layers, color filters, and pixel electrodes are stacked in order, wherein the first pad is connected to a data line, and the second pad is connected to a pixel electrode.

After applying a voltage to the first and second pads, it is preferable to measure the amount of change in current over time, and integrate the value to measure capacitance.

It is preferable to further include a second passivation layer between the color filter and the pixel electrode,

The TEG is preferably formed for each color filter.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, area, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

A thin film transistor array panel according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention, and FIG. 2 is a line II-II′-II ″ of the liquid crystal display including the thin film transistor array panel of FIG. 1. It is a cross-sectional view cut along.

The liquid crystal display according to the exemplary embodiment of the present invention may include a thin film transistor array panel 100, an upper panel facing the display panel (not shown), and a liquid crystal layer interposed between the thin film transistor array panel 100 and the upper panel. ), And the like.

In addition, the liquid crystal display according to the exemplary embodiment may be disposed between the thin film transistor array panel 100 and the polarizer (not shown) attached to the outer surface of the upper panel and between the thin film transistor array panel 100, the upper panel, and the polarizer. It may include a compensation plate (not shown) for compensating the phase of the light passing through.

In this case, the liquid crystal layer may be aligned in a vertical alignment method or a twisted nematic alignment method, and may have an arrangement that is symmetrically bent with respect to the center plane of the thin film transistor array panel 100 and the upper display panel. The transmission axes of the polarizing plates may be disposed perpendicular to or parallel to each other.

The upper panel includes an upper substrate made of a transparent insulating material such as glass, a common electrode formed on the upper substrate and made of a transparent conductive material such as ITO or IZO, and an alignment layer coated thereon.

Referring to the thin film transistor array panel 100, a plurality of gate lines 121 for transmitting a gate signal are formed on an insulating substrate 110 such as transparent glass. Each gate line 121 mainly extends in a horizontal direction and has an area for connection with a plurality of gate electrodes 124, a plurality of projections 127 protruding downward, and another layer or an external driving circuit. It includes a wide end. The driving circuit may be mounted on a flexible printed circuit film attached to the substrate 110 or directly mounted on the substrate 110.

The gate line 121 may be formed of aluminum-based metal such as aluminum (Al) or aluminum alloy, silver-based metal such as silver (Ag) or silver alloy, copper-based metal such as copper (Cu) or copper alloy, molybdenum (Mo) or molybdenum It may be made of molybdenum-based metals such as alloys, chromium (Cr), tantalum (Ta), and titanium (Ti). However, the gate line 121 may have a multilayer structure including two conductive layers having different physical properties. One of the conductive layers is made of a low resistivity metal, for example, an aluminum-based metal, a silver-based metal, or a copper-based metal so as to reduce a signal delay or voltage drop of the gate line 121. The other conductive layer may be made of another material, particularly a material having excellent physical, chemical and electrical contact properties with indium tin oxide (ITO) and indium zinc oxide (IZO), such as molybdenum-based metal, chromium, tantalum, or titanium. . A good example of such a combination is a chromium bottom film and an aluminum top film, and an aluminum bottom film and a molybdenum top film.                     

The side of the gate line 121 is inclined with respect to the surface of the substrate 110, the inclination angle is preferably about 30 ~ 80 °.

A gate insulating layer 140 made of silicon nitride (SiNx) is formed on the gate line 121.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (a-Si), polycrystalline silicon, or the like are formed on the gate insulating layer 140. The linear semiconductor 151 extends mainly in the longitudinal direction from which a plurality of projections 154 extend toward the gate electrode 124. In addition, the linear semiconductor 151 increases in width near the point where the linear semiconductor 151 meets the gate line 121 to cover a large area of the gate line 121.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as hydrogenated amorphous silicon doped with silicide or n-type impurities at a high concentration are formed on the semiconductor 151. The linear ohmic contact 161 has a plurality of protrusions 163, and the protrusion 163 and the island-type ohmic contact 165 are paired and positioned on the protrusion 154 of the semiconductor 151.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30-80 °.

The plurality of data lines 171, the plurality of drain electrodes 175, and the plurality of storage capacitor conductors are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140. 177 is formed.                     

The data line 171 mainly extends in the vertical direction to cross the gate line 121 and transmit a data voltage. Each data line 171 has a wide end portion for connecting a plurality of source electrodes 173 extending toward the gate electrode 124 with another layer or an external device.

The pair of source electrode 173 and the drain electrode 175 are separated from each other and positioned opposite to each other with respect to the gate electrode 124. The gate electrode 124, the source electrode 173, and the drain electrode 175 form a thin film transistor (TFT) together with the protrusion 154 of the semiconductor 151, and the channel of the thin film transistor is a source. A protrusion 154 is formed between the electrode 173 and the drain electrode 175.

The data line 171, the drain electrode 175, and the conductor 177 for the storage capacitor are preferably made of a refractory metal such as molybdenum, chromium, tantalum, titanium, or an alloy thereof. However, these may also have a multilayer film structure including a conductive film having a low resistance and a conductive film having good contact characteristics. Examples of the multilayer film structure include a triple film of molybdenum film, aluminum film, and molybdenum film in addition to the above-described double film of chromium lower film and aluminum upper film or aluminum lower film and molybdenum upper film.

Similarly to the gate line 121, the data line 171 and the drain electrode 175 are inclined at an angle of about 30 to 80 ° with respect to the surface of the substrate 110.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 at the bottom thereof, the data line 171 and the drain electrode 175 thereon, and serve to lower the contact resistance. The linear semiconductor 151 has a portion exposed between the source electrode 173 and the drain electrode 175 and not covered by the data line 171 and the drain electrode 175. The linear semiconductor 151 also has a width of the linear semiconductor 151 smaller than that of the data line 171 in most places, but as described above, the width of the linear semiconductor 151 is increased to smooth the profile of the surface. Disconnection of the data line 171 can be prevented.

A lower passivation layer 180a made of silicon nitride or silicon oxide is formed on the data line 171, the drain electrode 175, the storage capacitor conductor 177, and the exposed semiconductor 151.

Red, green, and blue color filters 230R, 230G, and 230B are formed on the lower passivation layer 180a. Each color filter 230R, 230G, 230B extends in the longitudinal direction. Alternatively, the color filters 230R, 230G, and 230B may be formed in a rectangular shape in an area divided by the gate line 121 and the data line 171.

An upper passivation layer 180b formed of an organic material having excellent planarization characteristics is formed on the color filters 230R, 230G, and 230B. The upper passivation layer 180b may have photosensitivity and have a dielectric constant of 4.0 or less, such as a-Si: C: O and a-Si: O: F, which are formed by plasma enhanced chemical vapor deposition (PECVD). It may be made of a low dielectric constant insulating material.

In the lower and upper passivation layers 180a and 180b, a plurality of contact holes exposing one end of the data line 171 and at least a portion of the drain electrode 175 and the storage capacitor conductor 177, respectively. 182, 185, and 187 are provided. In addition, the lower and upper passivation layers 180a and 180b and the gate insulating layer 140 are provided with a plurality of contact holes 181 exposing the ends of the gate line 121. On the other hand, the color filters 230R, 230G and 230B also have openings 235 and 237 exposing the drain electrode 175 and the conductor 177 for the storage capacitor. As shown in the drawing, the color filters 230R, 230G, The openings 235 and 237 of 230B are larger than the contact holes 185 and 187 of the protective films 180a and 180b. However, the contact holes 185 and 187 of the upper passivation layer 180b may be larger than the openings 235 and 237, in which case a stepped sidewall is formed.

A plurality of pixel electrodes 190 made of IZO or ITO and a plurality of contact auxiliary members 81 and 82 are formed on the passivation layers 180a and 180b.

The pixel electrode 190 is physically and electrically connected to the drain electrode 175 and the storage capacitor conductor 177 through the openings 235 and 237 and the contact holes 185 and 187, respectively, from the drain electrode 175. The data voltage is applied and the data voltage is transferred to the conductor 177.

The pixel electrode 190 to which the data voltage is applied rearranges the liquid crystal molecules of the liquid crystal layer between the thin film transistor array panel 100 and the upper panel by generating an electric field together with the common electrode of the upper panel to which the common voltage is applied.

In addition, as described above, the pixel electrode 190 and the common electrode form a capacitor (hereinafter, referred to as a "liquid crystal capacitor") to maintain the applied voltage even after the thin film transistor is turned off. There are other capacitors connected in parallel which are called maintenance capacitors. The storage capacitor is formed by overlapping the pixel electrode 190 and the neighboring gate line 121 (hereinafter, referred to as a shear gate line). The storage capacitor is connected with the gate line 121 to increase the capacitance of the storage capacitor, that is, the storage capacitance. An extended protrusion 127 is provided to increase the overlapped area, while a conductive capacitor conductor 177 connected to the pixel electrode 190 and overlapped with the protrusion 127 is placed under the protective film 180 to provide a distance therebetween. You can get close. Alternatively, a storage capacitor may be formed by overlapping a separate storage electrode line (not shown) and the pixel electrode 190.

The contact assistants 81 and 82 are connected to exposed ends of the gate line 121 and the data line 171 through the contact holes 181 and 182, respectively. The contact assistants 81 and 82 compensate for and protect the adhesion between the ends of the gate line 121 and the data line 171 and the external device.

Finally, an alignment layer 11 is formed on the pixel electrode 190, the contact auxiliary members 81 and 82, and the passivation layer 180.

In the thin film transistor array panel having such a configuration, a TEG (Test Element Group) is formed to measure resistance and capacitance in a pixel.

3 is a layout view of a TEG (Test Element Group) formed in a thin film transistor array panel according to an exemplary embodiment of the present invention, and FIG. 4 is a TEG (Test Element Group) formed in a thin film transistor array panel according to an exemplary embodiment of the present invention. It is a figure which illustrates an area | region.

As shown in Fig. 3, a TEG (Test Element Group) 50 is formed with a separate TEG 55 capable of measuring capacitance and resistance. The individual TEGs 55 shown in FIG. 3 clearly indicate only the positions of the TEGs. The structure of the individual TEGs 55 consists of a pair of TEG contact pads 197 and a laminated structure formed therebetween, the cross section of which is shown in Figs. The stacked structure is formed through the same materials and processes as those for forming pixels of the thin film transistor array panel.

In FIG. 3, gate refers to the gate line 121, and SD refers to the data line 171 or the source electrode 173 and the drain electrode 175. ITO means the pixel electrode 190, and ACT means the semiconductor 150. Each individual TEG 55 has a pad 197 configured to measure a value that can be measured in that TEG. As shown in Fig. 3, the individual TEGs 55 are formed at regular intervals such that the left and right intervals are X and the upper and lower intervals are Y. In general, the left and right spacing is formed to 3000㎛, the vertical space is formed to 800㎛.

As illustrated in FIG. 4, the TEG (Test Element Group) 50 is formed outside the display area 10 and the pad area 20 in the mother glass, and is not limited to the area shown in FIG. 4. .

5 to 7 are cross-sectional views of the laminated structure between the TEG pads 197 of the individual TEGs 55. FIG.

5 is a cross-sectional view illustrating a test element group (TEG) for measuring contact resistance between a data line and a pixel electrode according to an exemplary embodiment of the present invention, and FIG. 6 illustrates capacitance between the gate line and the pixel electrode according to an exemplary embodiment of the present invention. FIG. 7 is a diagram illustrating a cross section of a TEG (Test Element Group) to be measured, and FIG. 7 is a diagram illustrating a cross section of a TEG (Test Element Group) for measuring capacitance between a data line and a pixel electrode according to an exemplary embodiment of the present invention.

The stacked structure of the individual TEGs 55 for measuring the resistance of the data line and the pixel electrode shown in FIG. 5 will be described below.

The data line 171 is formed, and the lower passivation layer 180a is formed thereon, and the color filter 230, the upper passivation layer 180b, and the pixel electrode 190 are sequentially stacked thereon. A contact hole 188 is formed in the lower passivation layer 180a, the color filter 230, and the upper passivation layer 180b so that the pixel electrode 190 is connected to the data line 171. One TEG pad 197 is connected to one end of the data line 171 through the opening 186 of the passivation layer 180a, and the other is connected to the pixel electrode 190. When current flows through the pair of TEG pads 197, current flows through the contact portion of the data line 171, the data line 171 and the pixel electrode 190, and the pixel electrode 190. A voltage is applied across the pad 197. By measuring this voltage, the contact resistance between the data line and the pixel electrode can be known.

6 and 7 show a cross-section of a stacked structure of individual TEGs 55 measuring capacitance. 6 illustrates a structure capable of measuring capacitance between the gate line 121 and the pixel electrode 190, and FIG. 7 illustrates a structure capable of measuring capacitance between the data line 171 and the pixel electrode 190.

In FIG. 6, a gate insulating layer 140, a lower passivation layer 180a, a color filter 230, an upper passivation layer 180b, and a pixel electrode 190 are sequentially stacked on the gate line 121. One pad for TEG 197 is connected to the gate line 121 through contact holes 186 formed in the gate insulating layer 140, the lower passivation layer 180a, the color filter 230, and the upper passivation layer 180b. The other TEG pad 197 is connected to the pixel electrode 190.

In FIG. 7, a lower passivation layer 180a, a color filter 230, an upper passivation layer 180b, and a pixel electrode 190 are sequentially stacked on the data line 171. One pad for TEG 197 is connected to the data line 171 through a contact hole 186 formed in the lower passivation layer 180a, the color filter 230, and the upper passivation layer 180b, and the other TEG pad 197. The pad 197 is connected to the pixel electrode 190.

In the TEG 55 shown in Figs. 6 and 7, after applying a voltage to the pad 197 for TEG, the amount of change in current over time is measured, and the capacitance can be obtained by integrating this value.

Each of the individual TEGs 55 of FIGS. 5 to 7 is preferably formed for each color filter. That is, in the case of having red, green, and blue color filters, individual TEGs 55 including red, green, and blue color filters 230 are formed to measure the resistance and capacitance in each case to display pixels of each color. Clearly predict star resistance, capacitance, and transistor characteristics.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

As described above, by forming a TEG that can measure the resistance and capacitance of the pixel including the color filter, it is possible to predict the difference in the characteristics generated due to the presence of the color filter, so that the pixel design can be accurate, Can be reduced.

Claims (12)

A pixel including a gate line, a data line, a thin film transistor, a color filter, and a pixel electrode, TEG (test element group) formed through the same material and process as the pixel and including a first pad, a second pad, and a stacked structure formed between the first pad and the second pad. Thin film transistor array panel comprising a. In claim 1, The TEG is a thin film transistor array panel formed in a mother glass except for a display area and a pad area. In claim 1, The TEG is stacked in order of a data line, a passivation layer, a color filter, and a pixel electrode, and has a stacked structure in which the pixel electrode is connected to the data line through an opening formed in the passivation layer and the color filter. The first pad is connected to the data line, and the second pad is connected to the pixel electrode. In claim 3, A thin film transistor array panel for measuring resistance by applying current to the first and second pads. In claim 3, And a second passivation layer between the color filter and the pixel electrode. In claim 1, The TEG has a stacked structure in which a gate line, a gate insulating film, a protective film, a color filter, and a pixel electrode are stacked in this order. The first pad is connected to the gate line, and the second pad is connected to the pixel electrode. In claim 6, And applying a voltage to the first and second pads, measuring a change in current over time, and integrating this value to measure capacitance. In claim 6, And a second passivation layer between the color filter and the pixel electrode. In claim 1, The TEG has a layered structure in which data lines, protective films, color filters, and pixel electrodes are stacked in this order. The first pad is connected to the data line, and the second pad is connected to the pixel electrode. In claim 9, And applying a voltage to the first and second pads, measuring a change in current over time, and integrating this value to measure capacitance. In claim 9, And a second passivation layer between the color filter and the pixel electrode. In claim 1, The thin film transistor array panel of which the TEG is formed for each color filter.

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