KR20060078570A - Shift register - Google Patents

Abstract

The present invention is to provide a shift register that can prevent the malfunction due to the gate bias stress.

The shift register of the present invention comprises: a pull-up thin film transistor each of the plurality of stages outputs a pulse to an output line in response to the start pulse; A pair of pull-down thin film transistors connected in parallel with the output line to alternately supply a first driving voltage to the output line after the pulse is output; The gate electrode of each of the pair of pull-down thin film transistors may maintain a lower voltage than its source electrode or drain electrode in the turn-off period.

Description

Shift register {SHIFT REGISTER}

1 is a block diagram showing a conventional two-phase shift register.

FIG. 2 is a circuit diagram mainly showing an output buffer of the first stage shown in FIG.

3 is a detailed circuit diagram of one stage in a shift register according to the first embodiment of the present invention;

4 is a drive waveform diagram of the stage shown in FIG.

5 is a voltage waveform diagram for each node of the pull-down TFT shown in FIG. 3;

6 is a detailed circuit diagram of one stage of a shift register according to a second embodiment of the present invention.

7 is a voltage waveform diagram for each node of the pull-down TFT shown in FIG. 6;

<Description of the code | symbol about the principal part of drawing>

10: control unit 30: output buffer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving circuit of a liquid crystal display, and more particularly, to a shift register using an amorphous silicon (a-Si) thin film transistor.

A liquid crystal display device used as a display device of a television and a computer displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, the liquid crystal display includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix, and a driving circuit for driving the liquid crystal panel.

The liquid crystal panel includes a liquid crystal cell formed for each region defined by the intersection of the gate line and the data line, and a thin film transistor (hereinafter referred to as TFT) connected between the gate line and the data line and the pixel electrode included in the liquid crystal cell. The TFT supplies the data signal from the data line to the pixel electrode in response to the scan signal from the gate line. The liquid crystal cell displays gray scales by rotating liquid crystal molecules having dielectric anisotropy according to the voltage difference between the pixel electrode and the common electrode to adjust light transmittance.

The driving circuit includes a gate driver for driving a gate line and a data driver for driving a data line. The gate driver sequentially supplies a scan signal to the gate line. The data driver converts digital data into analog data signals and supplies them to the data lines whenever a scan signal is supplied.

The gate driver includes a shift register to generate sequential scan signals. The data driver also includes a shift register to generate a sequential sampling signal that can sequentially sample data signals input from the outside.

Referring to FIG. 1, there is shown a general shift register having first to nth stages connected dependently to a start pulse Vst input line.

The first and second clock signals C1 and C2 are commonly supplied to the first to nth stages of the shift register illustrated in FIG. 1 together with the high potential and the low potential driving voltages VDD and VSS. Vst) or the output signal of the preceding stage is supplied. The first stage outputs the first output signal Out1 in response to the start pulse Vst and the first and second clock signals C1 and C2. The second through n-th stages output the second through n-th output signals Out2 through Outn in response to the output signal of the previous stage and the first and second clock signals C1 and C2. The first to n-th stages have the same circuit configuration, and sequentially output the start pulse Vst in response to the first and second clock signals C1 and C2. The first to nth output signals Out1 to Outn from the first to nth stages are supplied as scan signals for sequentially driving the gate lines of the liquid crystal panel, or sequentially sampling the video signals in the data driver. Is supplied as a sampling signal.

FIG. 2 illustrates a configuration of one stage shown in FIG. 1 based on an output buffer.

The stage shown in FIG. 2 includes a pull-up TFT Tpu which outputs the clock signal C to an output line under the control of the Q node, and a low potential drive voltage VSS as the output line under the control of the QB node. An output buffer section 30 composed of a pull-down TFT (Tpd) for outputting, and a control section 10 for controlling the Q node and the QB node.

The controller 10 charges the Q node by the output signal of the previous stage, that is, the start pulse Vst, so that the pull-up TFT Tpu outputs the high voltage of the clock signal C as the output signal Out_i. do. The control unit 10 discharges the Q node by the clock signal C, charges the QB node, and causes the pull-down TFT Tpd to output the low potential voltage VSS as the output signal Out_i. Here, the pull-down TFT Tpd is turned on for most of the period except for the period in which the pull-up TFT Tpu is turned on to output the low potential voltage VSS as the output signal Out_i. To this end, the QB node maintains a high state for most of the period by the control unit 10, so that the pull-down TFT Tpd receives a large gate bias stress and the threshold voltage Vth fluctuates and malfunctions.

Accordingly, it is an object of the present invention to provide a shift register that can prevent malfunction due to gate bias stress.

In order to achieve the above object, the shift register according to the embodiment of the present invention is a shift register having a plurality of stages for supplying each output signal and the next stage start pulse by shifting the input start pulse, Each stage of the pull-up thin film transistor outputs a pulse to an output line in response to the start pulse; A pair of pull-down thin film transistors connected in parallel with the output line to alternately supply a first driving voltage to the output line after the pulse is output; The gate electrode of each of the pair of pull-down thin film transistors may maintain a lower voltage than its source electrode or drain electrode in the turn-off period.

The stage further includes a first control unit including another pair of pull-down thin film transistors alternately supplying the first driving voltage to a gate electrode of the pull-up transistor.

The gate electrode of each of the other pair of pull-down thin film transistors maintains a lower voltage than its source electrode or drain electrode in the turn-off period.

A second driving voltage is supplied to its gate electrode for turning off each of the pull-down thin film transistors; The first driving voltage is higher than the second driving voltage.

The second driving voltage is lower than the second driving voltage included in the pulse signal, and the first driving voltage is greater than the difference voltage obtained by subtracting the threshold voltage of the pull-down thin film transistor from the first driving voltage. .

The stage includes a first node controller controlled by an output signal of the start pulse and a next stage stage to charge and discharge a first node connected to a gate electrode of the pull-up thin film transistor; A second node controller controlled by the first node to charge and discharge the second node to have a voltage opposite to that of the first node; Third node control for charging and discharging a third node connected to a gate electrode of a first pull-down thin film transistor among the pair of pull-down thin film transistors by controlling the clock signal; A fourth node controller configured to charge and discharge a fourth node connected to a gate electrode of a second pull-down thin film transistor among the pair of pull-down thin film transistors opposite to the third node by controlling the clock signal; It is provided with.

The first node controller includes: a first thin film transistor connected in a diode type between the start pulse input line and the first node; And a second thin film transistor connected between the first node and an input line of the second driving voltage and controlled by an output signal of the next stage.

The second node controller may include a third thin film transistor connected in a diode type between the third driving voltage input line and the second node; And a fourth thin film transistor connected between the second node and the input line of the second driving voltage and controlled by the first node.

The fourth thin film transistor is formed larger than the third thin film transistor.

The pull-up thin film transistor has a fifth thin film transistor connected between an input line and the output line of a first clock signal and controlled by the first node; The pair of pull-down thin film transistors include a sixth thin film transistor connected between an output line of the stage and an input line of the first driving voltage and controlled by the third node; And a seventh thin film transistor connected in parallel with the sixth thin film transistor and controlled by the fourth node.

The stage is further provided with a capacitor connected to the fifth thin film transistor for bootstrapping the first node using the first clock signal.

The third node controller is connected between the second node and the third node and is connected between an eighth thin film transistor controlled by the first clock signal, an input line of the second driving voltage, and the third node. And a ninth thin film transistor controlled by a second clock signal.

The fourth node controller includes: a tenth thin film transistor connected between the second node and the fourth node and controlled by the second clock signal; And an eleventh thin film transistor connected between the input line of the second driving voltage and the fourth node and controlled by the first clock signal.

The other pair of pull-down thin film transistors may include: a twelfth thin film transistor connected between the first node and an input line of the first driving voltage and controlled by the third node; A thirteenth thin film transistor connected in parallel with the twelfth thin film transistor and controlled by the fourth node is provided.

The stage is composed of thin film transistors of the same channel type.

The stage is composed of an NPMOS thin film transistor.

The stage is composed of amorphous-silicon thin film transistors.

The first and second clock signals are phase inverted.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 8.

4 illustrates a detailed circuit for one stage in a shift register according to an embodiment of the present invention, and FIG. 5 illustrates a driving waveform.

One stage of the shift register shown in FIG. 4 includes a fifth NMOS TFT T5 for outputting the clock signal C1 to the output line under the control of the Q node, and a low potential driving voltage under the control of the QB1 and QB2 nodes. An output buffer having sixth and seventh NMOS TFTs T6 and T7 for outputting VSS to an output line; A Q node control unit including first and second NMOS TFTs T1 and T2 for controlling the Q node, and twelfth and thirteenth NMOS TFTs T12 and 13; A QB node controller having third and fourth NMOS TFTs T3 and T4 for controlling the QB node; QB1 node control unit having eighth and ninth NMOS TFTs (T8, T9) for controlling the QB1 node, and QB2 node control unit having tenth and eleventh NMOS TFTs (T10, T11) for controlling the QB2 node. do.

The fifth NMOS TFT T5, which is a pull-up transistor in the output buffer, is connected between the clock signal C1 input line and the output line of the stage and controlled by the Q node. The sixth and seventh NMOS TFTs T6 and T7, which are pull-down transistors, are connected in parallel between the output line of the stage and the low potential voltage VSS input line, and are controlled by the QB1 and QB2 nodes, respectively.

The Q node control unit includes a precharge unit for precharging the Q node and a discharge unit for discharging. The first NMOS TFT T1 of the Q node precharge part is connected in a diode type between the start pulse Vst input line and the Q node. The Q node discharge portion is connected between the low potential voltage (VSS) supply line and the Q node to control the second NMOS TFT (T2), the Q node and the low potential voltage (VSS) controlled by the output signal Out_i + 1 of the next stage. 12th and 13th NMOS TFTs (T12, T13) connected in parallel between the supply lines and controlled by the QB1 and QB2 nodes, respectively.

The third NMOS TFT T3 of the QB node controller is connected in a diode type between the high potential driving voltage VDD supply line and the QB node, and the fourth NMOS TFT T4 supplies the QB node and the low potential voltage VSS. It is connected between lines and controlled by the Q node.

The eighth NMOS TFT T8 of the QB1 node controller is connected between the QB node and the QB1 node and controlled by the first clock signal C1, and the ninth NMOS TFT T9 is connected to the low potential voltage VSS input line. It is connected between the QB1 nodes and controlled by the second clock signal C2.

The tenth NMOS TFT T10 of the QB2 node controller is connected between the QB node and the QB2 node and controlled by the second clock signal C2, and the eleventh NMOS TFT T11 is connected to the low potential voltage VSS input line. It is connected between the QB2 nodes and controlled by the first clock signal C1.

NMOS or PMOS TFT may be applied to the first to thirteenth NMOS TFTs (T1 to T13), but the following description will be given only by using an NMOS TFT.

An operation process of such a stage will be described with reference to the driving waveform shown in FIG. 4.

In the period A, the first NMOS TFT T1 is turned on by the high voltage of the start pulse Vst, and the Q node is precharged to the high state by the start pulse Vst. The fifth NMOS TFT T5 is turned on by the Q node precharged to the high state to supply the low voltage of the clock signal C1 to the output line. At the same time, the fourth PMOS transistor T4 is turned on by the Q node precharged to the high state, and the third NMOS TFT T3, which is diode-connected to the high potential voltage VDD input line, is turned on. do. In this case, the fourth NMOS TFT T4 is formed larger than the third NMOS TFT T3 so that the low potential voltage VSS reaches the QB node faster than the high potential voltage VDD so that the QB node becomes low. do. For example, the size ratio of the third and fourth NMOS TFTs T3 and T4 is formed to be about 1: 3. The ninth and tenth NMOS TFTs T9 and T10 are turned on by the second clock signal C2, so that the low voltage supplied to the QB node is supplied to the QB1 node, and the low potential voltage VSS is supplied to the QB2 node. do. Accordingly, the sixth and seventh NMOS TFTs T6 and T7 and the twelfth and thirteenth NMOS TFTs T12 and T13 are turned off. As a result, in the period A, the output line of the stage outputs the output signal Out_i in the low state.

In the period B, the first NMOS TFT T1 is turned off by the low voltage of the start pulse Vst, so that the Q node floats to a high state, and thus the fifth NMOS TFT T5 maintains the turn-on state. In this case, as the high voltage of the first clock signal C1 is supplied, the floating Q node is bootstrapping under the influence of the capacitor CB formed between the gate electrode and the source electrode of the fifth NMOS TFT T5. As a result, the Q-node voltage further rises and the fifth NMOS TFT T5 is reliably turned on, so that the high voltage of the first clock signal C1 is quickly supplied to the output line. At this time, even if the third NMOS TFT T3 is turned on by the fourth PMOS transistor T4 turned on by the bootstrapped Q node, the QB node is turned low. The eighth and eleventh NMOS TFTs T8 and T11 are turned on by the first clock signal C1, so that the low voltage supplied to the QB node is supplied to the QB1 node, and the low potential voltage VSS is applied to the QB2 node. Is supplied. Accordingly, the sixth and seventh NMOS TFTs T6 and T7 and the twelfth and thirteenth NMOS TFTs T12 and T13 are turned off. As a result, in the period B, the output line of the stage outputs the high output signal Out_i + 1. As a result, the start pulse Vst supplied in the A period is shifted through the first and fifth NMOS TFTs T1 and T5 and output as the output signal Out_i in the B period.

In the C period, since the second NMOS TFT T2 is turned on by the high voltage of the output signal Out_i + 1 of the next stage, the low potential voltage VSS is supplied to the Q node, so that the fifth NMOS TFT T5 is supplied. Is turned off. In addition, the fourth NMOS TFT T4 is turned off by the low potential voltage VSS of the Q node, and the high potential voltage VDD is applied through the third NMOS TFT T3 that maintains the turn-on state of the QB node. Is supplied. In addition, the ninth and tenth NMOS TFTs T9 and T10 are turned on by the second clock signal C2 so that the low potential driving voltage VSS is supplied to the QB1 node and the QB node is supplied to the QB node. The above driving voltage VDD is supplied. As a result, the seventh NMOS TFT T7 is turned on to supply the low potential driving voltage VSS to the output line. In addition, the thirteenth NMOS TFT T13 is turned on to supply the low potential driving VSS to the Q node. Accordingly, the output node Out_i + 1 of the next stage becomes low so that the Q node is surely low even when the second NMOS TFT T2 is turned off. As a result, in the period C, the output line of the stage outputs the output signal Out_i in the low state.

In the D period, the first and second NMOS TFTs T1 and T2 are turned off by the low voltage of the start pulse Vst and the output signal Out_i + 1 of the next stage. Accordingly, since the fourth NMOS TFT T4 is turned off by the low voltage of the Q node, the high potential voltage VDD is supplied to the QB node through the third NMOS TFT T3 that maintains the turn-on state. . The eighth and eleventh NMOS TFTs T9 are turned on by the clock signal C1, so that the high potential voltage VDD supplied to the QB node is supplied to the QB1 node, and the low potential voltage VSS is supplied to the QB2 node. Is supplied. Accordingly, the sixth NMOS TFT T6 is turned on to supply the low potential driving voltage VSS to the output line. In addition, the twelfth NMOS TFT T12 is turned on to supply the low potential driving VSS to the Q node. Accordingly, even when the first and second second NMOS TFTs N2 are turned off, the Q node is surely brought into a low state. As a result, in the period D, the output line of the stage outputs the output signal Out_i in the low state.

In the remaining periods, the stage operates in the same manner as the C and D periods, so that the output signal Out_i of the stage is kept low.

As such, the shift register according to the present invention includes a pair of pull-down TFTs, i.e., sixth and seventh NMOS TFTs (T6, T7), and the QB1 and QB2 nodes for controlling them include first and second clock signals. The gate bias stress is reduced by alternating current driving according to (C1, C2). In addition, gate bias stress is reduced by alternatingly driving the gate electrodes of the twelfth and thirteenth NMOS TFTs (T12, T13) holding the Q node at a low voltage by QB1 and QB2.

However, the gate / source / drain electrodes of each of the sixth and seventh NMOS TFTs T6 and T7 and the twelfth and thirteenth NMOS TFTs T12 and T13 have a low potential voltage VSS for each turn-off period as shown in FIG. 5. Will be the same.

Referring to FIG. 5, a high voltage is applied to the source electrodes of the sixth and seventh NMOS TFTs T6 and T7 connected to the output line in the period B. FIG. The gates of the seventh and thirteenth NMOS TFTs T7 and T13 connected to the QB1 node during the C and D periods in which the low voltage is applied to the source electrodes of the sixth and seventh NMOS TFTs T6 and T7 are repeated. The high voltage is alternately supplied to the electrode and the gate electrodes of the sixth and twelfth NMOS TFTs T6 and T12 connected to the QB1 node. Accordingly, the seventh and thirteenth NMOS TFTs T7 and T13 and the sixth and twelfth NMOS TFTs T6 and T12 are alternately turned on. In other words, the C period in which the sixth and twelfth NMOS TFTs T6 and T12 are turned off and the D period in which the seventh and thirteenth NMOS TFTs T7 and T13 are turned off are alternately repeated. . However, in the C period in which the sixth and twelfth NMOS TFTs T6 and T12 are turned off, their source / drain / gate electrodes are the same as the low potential driving voltage VSS, and the seventh and thirteenth NMOS TFTs T7. In the period D where T13 is turned off, their source / drain / gate electrodes become equal to the low potential driving voltage VSS. Thus, the gate electrodes of the seventh and thirteenth NMOS TFTs T7 and T13 and the sixth and twelfth NMOS TFTs T6 and T12 are subjected to bias stress not only during the turn-on period but also during the turn-off period. This may cause a problem that their threshold voltages Vth are shifted.

In order to solve this problem, the shift and register according to the second embodiment of the present invention illustrated in FIG. 6 include the seventh and thirteenth NMOS TFTs T7 and T13 and the sixth and twelfth NMOS TFTs T6 and T12. Each period of turn-off allows their gate voltage to remain below the drain voltage.

In other words, in the stage of the shift register illustrated in FIG. 6, the drain electrodes of the seventh and thirteenth NMOS TFTs (T7 and T13) and the drain electrodes of the sixth and twelfth NMOS TFTs (T6 and T12) may have a low potential driving voltage (VSS). Is connected to the supply line of the second low potential driving voltage VSS2 higher than). Since the remaining components of the stage illustrated in FIG. 6 overlap with the stage illustrated in FIG. 3, a detailed description thereof will be omitted.

As shown in FIG. 8, the second low potential driving voltage VSS2 shown in FIG. 6 is set higher than the low potential driving voltage VSS. In addition, when the high voltage (ie, VDD) is supplied to the gate electrodes of the seventh and thirteenth NMOS TFTs T7 and T13 and the sixth and twelfth NMOS TFTs T6 and T12, the second low voltage is turned on. The potential driving voltage VSS2 is set lower than the high potential driving voltage VDD-threshold voltage Vth.

Referring to FIG. 7, a high voltage is applied to the source electrodes of the sixth and seventh NMOS TFTs T6 and T7 connected to the output line in the period B, and then the sixth and seventh NMOS TFTs T6 and T7 are applied. The gate electrodes of the seventh and thirteenth NMOS TFTs T7 and T13 connected to the QB1 node and the sixth and twelfth NMOS TFTs connected to the QB1 node during C and D periods in which a low voltage is applied to the source electrode are repeated. The high voltage is alternately supplied to the gate electrodes of T6 and T12. Accordingly, the C period in which the seventh and thirteenth NMOS TFTs T7 and T13 are turned on and the D period in which the sixth and twelfth NMOS TFTs T6 and T12 are turned on are repeated. In other words, the C period in which the sixth and twelfth NMOS TFTs T6 and T12 are turned off and the D period in which the seventh and thirteenth NMOS TFTs T7 and T13 are turned off are alternately repeated. .

In this case, the low potential driving voltage VSS is applied to their gate / source electrodes in the C period when the sixth and twelfth NMOS TFTs T6 and T12 are turned off, while the second low potential is applied to their drain electrodes. The driving voltage VSS2 is supplied. Further, in the D period in which the seventh and thirteenth NMOS TFTs T7 and T13 are turned off, a low potential driving voltage VSS is applied to their gate / source electrodes, while a second low potential driving is applied to their drain electrodes. The voltage VSS is supplied. Accordingly, the gate electrodes of the seventh and thirteenth NMOS TFTs T7 and T13 and the sixth and twelfth NMOS TFTs T6 and T12 may have a second low potential driving voltage supplied to the drain electrode during the turn-off period. It is possible to maintain the low potential driving voltage VSS lower than VSS2). As a result, the gate electrodes of the seventh and thirteenth NMOS TFTs T7 and T13 and the gate electrodes of the sixth and twelfth NMOS TFTs T6 and T12 compensate for the bias stress received in the turn-on period in the turn-off period and thus the thresholds. The shift of the voltage Vth can be prevented.

As described above, the shift register according to the present invention includes a pair of pull-down TFTs alternately applying a low voltage to an output line, and another pair of pull-downs alternately applying a low voltage to a Q node. The gate electrode of the TFT keeps the voltage lower than the drain electrode in the turn-off period. Accordingly, the shift register according to the present invention can prevent the malfunction due to the shift of the threshold voltage Vth by compensating the bias stress received by the pull-down TFT in the turn-on period in the turn-off period.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (18)

A shift register comprising a plurality of stages for shifting an input start pulse to supply each output signal and a next stage start pulse, wherein each of the plurality of stages A pull-up thin film transistor outputting a pulse to an output line in response to the start pulse; A pair of pull-down thin film transistors connected in parallel with the output line to alternately supply a first driving voltage to the output line after the pulse is output; And a gate electrode of each of the pair of pull-down thin film transistors maintains a lower voltage than its source electrode or drain electrode in a turn-off period. The method of claim 1, The stage is And a first control unit including another pair of pull-down thin film transistors alternately supplying the first driving voltage to a gate electrode of the pull-up transistor. The method of claim 2, And a gate electrode of each of the other pair of pull-down thin film transistors maintains a lower voltage than its source electrode or drain electrode in a turn-off period. The method of claim 2, A second driving voltage is supplied to its gate electrode for turning off each of the pull-down thin film transistors; And the first driving voltage is higher than the second driving voltage. The method of claim 4, wherein The second driving voltage is lower than the second driving voltage included in the pulse signal, The first driving voltage is greater than the first driving voltage, the shift register, characterized in that greater than the difference voltage minus the threshold voltage of the pull-down thin film transistor. The method of claim 2, The stage is A first node control unit controlled by the start pulse and an output signal of a next stage stage to charge and discharge a first node connected to the gate electrode of the pull-up thin film transistor; A second node controller controlled by the first node to charge and discharge the second node to have a voltage opposite to that of the first node; A third node control for charging and discharging a third node connected to a gate electrode of a first pull-down thin film transistor among the pair of pull-down thin film transistors by controlling the clock signal; A fourth node controller configured to charge and discharge a fourth node connected to a gate electrode of a second pull-down thin film transistor among the pair of pull-down thin film transistors opposite to the third node by controlling the clock signal; A shift register, characterized in that provided with. The method of claim 6, The first node controller is A first thin film transistor connected in a diode type between the start pulse input line and the first node; And a second thin film transistor connected between the first node and an input line of the second driving voltage and controlled by an output signal of the next stage. The method of claim 7, wherein The second node controller A third thin film transistor connected in a diode type between the third driving voltage input line and the second node; And a fourth thin film transistor connected between the second node and an input line of the second driving voltage and controlled by the first node. The method of claim 8, And the fourth thin film transistor is larger than the third thin film transistor. The method of claim 9, The pull-up thin film transistor is A fifth thin film transistor connected between an input line and an output line of a first clock signal and controlled by the first node; The pair of pull-down thin film transistors A sixth thin film transistor connected between an output line of the stage and an input line of the first driving voltage and controlled by the third node; And a seventh thin film transistor connected in parallel with the sixth thin film transistor and controlled by the fourth node. The method of claim 10, The stage is And a capacitor connected to the fifth thin film transistor for bootstrapping the first node using the first clock signal. The method of claim 10, The third node controller An eighth thin film transistor connected between the second node and the third node and controlled by the first clock signal; And a ninth thin film transistor connected between the input line of the second driving voltage and the third node and controlled by a second clock signal. The method of claim 12, The fourth node controller is A tenth thin film transistor connected between the second node and the fourth node and controlled by the second clock signal; And an eleventh thin film transistor connected between the input line of the second driving voltage and the fourth node and controlled by the first clock signal. The method of claim 15, The other pair of pull-down thin film transistors A twelfth thin film transistor connected between the first node and an input line of the first driving voltage and controlled by the third node; And a thirteenth thin film transistor connected in parallel with the twelfth thin film transistor and controlled by the fourth node. The method of claim 15, And the stage comprises a thin film transistor of the same channel type. The method of claim 15, And the stage comprises an NPMOS thin film transistor. The method of claim 15, And said stage comprises an amorphous silicon silicon transistor. The method of claim 15, And the first and second clock signals are phase inverted.

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