KR20060077813A - Column control circuit of a semiconductor memory device - Google Patents

Abstract

A column control circuit of a semiconductor memory device capable of optimizing operation timing is disclosed. The column control circuit of the semiconductor memory device includes a column controller, a column driver, and a column control bus. The column controller activates or deactivates column lines of the memory cell array. The column driver receives the column control signal to improve the current driving capability. The column control bus is provided with a first bus for providing the column control signal having the improved current driving capability to all areas of the column control unit, and receives the column control signal with the improved current driving capability from the column driver and provides it to the center of the first bus. To have a second bus. Therefore, the semiconductor memory device using the column control circuit can optimize the operation timing due to skew between signals passing through paths having different lengths.

Description

COLUMN CONTROL CIRCUIT OF A SEMICONDUCTOR MEMORY DEVICE

1 is a diagram schematically illustrating a structure of a general DRAM device.

FIG. 2 is a diagram illustrating a column control circuit in the DRAM device of FIG. 1.

3 shows a column control circuit according to a first embodiment of the present invention.

4 is a diagram illustrating a column control circuit according to a second embodiment of the present invention.

FIG. 5 is a diagram comparing timing margins of a DRAM device having a column control bus of the related art and a DRAM device having a column control bus according to the present invention.

Explanation of symbols on the main parts of the drawings

11, 12, 13, 14: Memory Bank

15, 16, 17, 18: column control area

19: IOSA

20: input / output drive circuit

21: peripheral circuit area

23, 123, 223: column control bus

24, 224 column driver

The present invention relates to a semiconductor memory device, and more particularly, to a column control circuit of a semiconductor memory device capable of optimizing an operation timing.

Recently, as the operation speed of a semiconductor memory device, in particular, a DRAM (Dynamic Random Access Memory) becomes faster, an operation timing between various signals used in the DRAM device has emerged as an important problem. In particular, optimizing the operation timing between signals related to an input / output sense amplifier (IOSA) in a DRAM device has become an essential item in the design of a DRAM device.

FIG. 1 is a schematic diagram illustrating a structure of a general DRAM device, and mainly illustrates a circuit part related to output of data stored in a memory cell. Referring to FIG. 1, a DRAM device includes memory banks 11, 12, 13, and 14, column control regions 15, 16, 17, and 18, and a peripheral circuit region 21 formed of a memory cell array. do. The peripheral circuit area 21 includes an IOSA 19, an output driver circuit 20, and the like. Each of the memory banks 11, 12, 13, and 14 stores data by a write command and outputs data stored in a cell by a read command. Path circuits in the column control regions 15, 16, 17, and 18 selectively enable column selection lines CSLs according to address information during a write operation or a read operation. The IOSA 19 functions to amplify the data from the memory banks 11, 12, 13, 14 during a read operation. The output driver circuit 20 functions to send data amplified by the IOSA 19 out of the semiconductor integrated circuit. In general, the memory cell array is divided into four banks as shown in FIG. 1 and is activated by upper address bits of two bits of the address bits. The IOSA has a current IOSA and a voltage IOSA and the IOSA 19 in FIG. 1 is the current IOSA. The DRAM device also includes a column control bus 23 for transferring the column control signal PWRD to each of the column control regions 15, 16, 17, and 18.

The IOSA enable signal FRP is generated in the peripheral circuit area 21 and the distance to the IOSA 19 is relatively short. The column control signal PWRD drives column lines of each of the memory banks 11, 12, 13, and 14 through the column control bus 23, and is located in the column control regions 15, 16, 17, and 18. Drives load transistors (not shown).

FIG. 2 is a diagram illustrating a column control bus in the DRAM device of FIG. 1. As shown in FIG. 2, the column control bus 23, which provides the column control signal PWRD to the column control region 15 through the column driver 24, has a structure in which small branches appear on a straight large branch. Have Further, since the conventional column control bus 23 shown in Fig. 2 is driven by one driver 24, bussing is simple. 1 and 2, there is a difference in time between the column control signal PWRD reaching an area near the first end A and an area near the second end B of the column control area 15. Because of the skew of the column control signal PWRD, it is difficult to set a criterion for setting the enable time and the disable time of the IOSA enable signal FRP. For example, when the operation timing is optimized based on the region near the first stage A, the operation timing of the column control signal PWRD and the IOSA enable signal FRP of the region near the second stage B is It is hard to be the best timing. On the contrary, when the operation timing is optimized based on the region near the second stage B, the operation timing of the column control signal PWRD and the IOSA enable signal FRP of the region near the first stage A is optimal. It is hard to be timing.

The timing of control signals related to the IOSA should be properly adjusted and optimized to obtain a good operating characteristic of the IOSA 19. As described above, it is difficult to optimize the timing of the control signal passing through the short path and the timing of the control signal passing through the long path using a conventional column control bus.

Therefore, there is a need for a method of optimizing the operation timing of the column control signal PWRD and the IOSA enable signal FRP.

An object of the present invention for solving the above problems is to provide a column control circuit of a semiconductor memory device that can optimize the operation timing.

It is another object of the present invention to provide a method that can solve the difficulty of optimizing motion timing due to skew between signals passing through different length paths.

In order to achieve the above object, a column control circuit of a semiconductor memory device according to one embodiment of the present invention includes a column control unit, a column driver, and a column control bus.

The column controller activates or deactivates column lines of the memory cell array. The column driver receives the column control signal to improve the current driving capability. The column control bus may receive a first bus for providing the column control signal having the improved current driving capability to all areas of the column control unit, and receive the column control signal having the improved current driving capability from the column driver, thereby receiving the first bus. It has a second bus for providing in the center.

A column control circuit of a semiconductor memory device according to another embodiment of the present invention includes a column controller, a column driver, and a column control bus.

The column controller activates or deactivates column lines of the memory cell array. The column driver receives the column control signal to improve the current driving capability. The column control bus is a first bus for providing a column control signal with improved current driving capability in an area from the center of the column controller to one end, and the current driving capability in an area from the center of the column control to the other end. A second bus for providing this enhanced column control signal, a third bus for receiving the column control signal with improved current driving capability from the column driver and providing it to the center of the first bus, and the current from the column driver And a fourth bus for receiving and providing a column control signal having improved driving capability to a center portion of the second bus.

A semiconductor memory device according to one embodiment of the present invention includes a memory cell array, an input / output sense amplifier, and a column control circuit. The input / output sense amplifier amplifies data output from the memory cell array during a read operation and amplifies data input during a write operation. The column control circuit includes a column controller, a column driver, and a column control bus.

The column controller activates or deactivates column lines of the memory cell array. The column driver receives the column control signal to improve the current driving capability. The column control bus may receive a first bus for providing the column control signal having the improved current driving capability to all areas of the column control unit, and receive the column control signal having the improved current driving capability from the column driver, thereby receiving the first bus. It has a second bus for providing in the center.

A semiconductor memory device according to another embodiment of the present invention includes a memory cell array, an input / output sense amplifier, and a column control circuit. The column control circuit includes a column controller, a column driver, and a column control bus.

The column control bus is a first bus for providing a column control signal with improved current driving capability in an area from the center of the column controller to one end, and the current driving capability in an area from the center of the column control to the other end. A second bus for providing this enhanced column control signal, a third bus for receiving the column control signal with improved current driving capability from the column driver and providing it to the center of the first bus, and the current from the column driver And a fourth bus for receiving and providing a column control signal having improved driving capability to a center portion of the second bus.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a diagram illustrating a column control bus according to a first embodiment of the present invention.

Referring to FIG. 3, a column control circuit of a semiconductor memory device includes a column control unit 15, a column control bus 123, and a column driver 24. The column driver 24 receives the column control signal PWRD to improve the current driving capability. The column control bus 123 is composed of a first bus 123-2 and a second bus 123-1, and the second bus 123-1 is connected to a central point of the first bus 123-2. do. The first bus 123-2 of the column control bus 123 has a structure in which twigs are connected to a linear branch, and the first bus A to the second bus B of the column control unit 15 are connected. The column control signal PWRD is provided to the area. The second bus 123-1 receives the column control signal PWRD through the column driver 24 and transmits the signal to the center point of the first bus 123-2.

The column control circuit having the structure of FIG. 3 reduces the skew of the signal according to the position of the memory cell array because the path of the column control signal PWRD to both ends A and B of the column driver 15 is substantially the same. Can be. Therefore, the semiconductor memory device using the column control circuit of FIG. 3 can optimize the operation timing of the column control signal PWRD and the IOSA enable signal FRP.

4 is a diagram illustrating a column control circuit according to a second embodiment of the present invention.

Referring to FIG. 4, the column control circuit of the semiconductor memory device includes a column controller 15, a column control bus 223, and a column driver 224. The column driver 224 receives the column control signal PWRD to improve the current driving capability. The column control bus 123 includes a first bus 223-1, a second bus 223-2, a third bus 223-3, and a fourth bus 223-4. Each of the first bus 223-1 and the second bus 223-2 has a structure in which twigs are connected to a straight large branch. In addition, the first bus 223-1 and the second bus 223-2 apply the column control signal PWRD to the region from the first stage A to the second stage B of the column control unit 15. to provide. The third bus 223-3 is connected to the center point of the second bus 223-2, and the fourth bus 223-4 is connected to the center point of the first bus 223-1. The third bus 223-3 and the fourth bus 223-4 receive the column control signal PWRD through the column driver 24 and transmit the signal to the second bus 223-2 and the first bus, respectively. To the central point of (223-1).

The column driver 224 in the column control circuit of FIG. 4 is composed of a first column driver 224-1 and a second column driver 224-2. The first column driver 224-1 receives the column control signal PWRD to improve the current driving capability and provide it to the second bus 223-2 through the third bus 223-3. The second column driver 224-2 receives the column control signal PWRD to improve the current driving capability and provide it to the first bus 223-1 through the fourth bus 223-4. In the column control circuit of FIG. 4, the distance from the third bus 223-3 to the second bus 223-2 and the distance from the fourth bus 223-4 to the first bus 223-1 are substantially the same. Design the same as

In the column control circuit having the structure of FIG. 4, since the paths of the column control signals PWRD to both ends A and B of the column driver 15 are substantially the same, the skew of the signal according to the position of the memory cell array is reduced. Can be. Therefore, in the semiconductor memory device using the column control circuit of FIG. 4, the enable time and the disable time of the column control signal PWRD can be set to be substantially the same for the entire area of the column control part. Thus, the column control signal PWRD and the IOSA The operation timing of the enable signal FRP may be optimized.

FIG. 5 is a diagram comparing timing margins of a DRAM device having a column control bus according to the related art and a DRAM device having a column control bus according to the present invention. Referring to FIG. 5, since the enable skew and the disable skew of the column control signal PWRD are large in the semiconductor memory device having the column control circuit according to the related art, a large signal margin is required. In the semiconductor memory device having the column control circuit according to the present invention, since the enable skew and the disable skew of the column control signal PWRD are small, much signal margin is not required as compared with the prior art.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, the column control circuit of the semiconductor memory device according to the present invention can optimize operation timing due to skew between signals passing through paths having different lengths.

Claims (13)

A column controller for activating or deactivating column lines of the memory cell array; A column driver for receiving a column control signal to improve current driving capability; And A first bus for providing the column control signal having the improved current driving capability to all areas of the column controller, and receiving the column control signal having the improved current driving capability from the column driver and providing the column control signal to the center of the first bus; And a column control bus having a second bus for the column control circuit of the semiconductor memory device. The method of claim 1, wherein the first bus A column control circuit of a semiconductor memory device, characterized in that it has a structure in which twigs are connected to a straight large branch. A column controller for activating or deactivating column lines of the memory cell array; A column driver for receiving a column control signal to improve current driving capability; And A first bus for providing a column control signal with improved current driving capability in an area from the center of the column control unit to one side end, and a column control with improved current driving capability in an area from the center of the column control unit to the other side end A second bus for providing a signal, a third bus for receiving the column control signal with improved current driving capability from the column driver and providing the column control signal to a central portion of the first bus, and the current driving capability is improved from the column driver. And a column control bus having a fourth bus for receiving column control signals and providing them to the center portion of the second bus. 4. The system of claim 3, wherein the first and second buses are A column control circuit of a semiconductor memory device, characterized in that it has a structure in which twigs are connected to a straight large branch. 4. The system of claim 3, wherein the third and fourth buses are A column control circuit of a semiconductor memory device, characterized in that the length is similar to each other. The method of claim 3, wherein the column driver A first column driver configured to receive the column control signal to improve current driving capability and provide the same to the third bus; And And a second column driver which receives the column control signal to improve current driving capability and provides the fourth bus to the fourth bus. Memory cell arrays; An input / output sense amplifier for amplifying data output from the memory cell array during a read operation and amplifying data input during a write operation; And A column controller for activating or deactivating column lines of the memory cell array; A column driver for receiving a column control signal to improve current driving capability; And A first bus for providing the column control signal having the improved current driving capability to all areas of the column controller, and receiving the column control signal having the improved current driving capability from the column driver and providing the column control signal to the center of the first bus; And a column control circuit having a column control bus having a second bus for the semiconductor memory device. The semiconductor memory device of claim 7, wherein the semiconductor memory device comprises: And an input / output driving circuit configured to receive the amplified data from the input / output sense amplifier, output the outside of the chip, and receive data from the outside of the chip and transmit the data to the input / output sense amplifier. 8. The system of claim 7, wherein the first bus is A semiconductor memory device having a structure in which twigs are connected to a straight large branch. Memory cell arrays; An input / output sense amplifier for amplifying data output from the memory cell array during a read operation and amplifying data input during a write operation; And A column controller for activating or deactivating column lines of the memory cell array; A column driver for receiving a column control signal to improve current driving capability; And A first bus for providing a column control signal with improved current driving capability in an area from the center of the column control unit to one side end, and a column control with improved current driving capability in an area from the center of the column control unit to the other side end A second bus for providing a signal, a third bus for receiving the column control signal with improved current driving capability from the column driver and providing the column control signal to a central portion of the first bus, and the current driving capability is improved from the column driver. And a column control circuit having a column control bus having a fourth bus for receiving column control signals and providing them to the center portion of the second bus. The semiconductor memory device of claim 10, wherein the semiconductor memory device comprises: And an input / output driving circuit configured to receive the amplified data from the input / output sense amplifier, output the outside of the chip, and receive data from the outside of the chip and transmit the data to the input / output sense amplifier. 11. The method of claim 10, wherein the first and second buses are A semiconductor memory device having a structure in which twigs are connected to a straight large branch. 11. The system of claim 10, wherein the third and fourth buses are A semiconductor memory device, characterized in that the length is similar to each other.

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