KR20060077717A - Timer circuit with double buffer structure - Google Patents

Abstract

TECHNICAL FIELD The present invention relates to electronic circuit design techniques, and more particularly, to a timer circuit. An object of the present invention is to provide a timer circuit that can change a set time without a reset operation. The present invention applies a double buffer structure to change the set time of the timer in real time. Therefore, it is not necessary to increase the number of timers required for the system, and it is not necessary to reset the timer to change the timer setting time. Therefore, the system can be controlled at various and accurate time intervals in applications requiring sequential system control.

Timer circuit, interface module, timer control module, counter module, setting time change, double buffer

Description

Timer circuit with double buffer structure {TIMER CIRCUIT WITH DOUBLE BUFFER STRUCTURE}             

1 is a repeating mode operation waveform diagram of a general timer.

2 is a block diagram of a timer circuit in accordance with the present invention.

3 is a block diagram illustrating an implementation of the timer control module of FIG.

4 is an operation waveform diagram of the timer circuit of FIG. 3.

* Explanation of symbols for the main parts of the drawings

120: timer control module

222: first base register

224: multiplexer

226: second base register

228: And Gate

229: comparator

TECHNICAL FIELD The present invention relates to electronic circuit design techniques, and more particularly to a timer circuit.

In general, the timer operates with one set time.

However, there are many application applications in the system, and these applications require timers having various setting times, thereby increasing the number of necessary timers.

However, there is a limit in terms of cost and chip area for increasing the number of timers. Therefore, a method of changing a set time for one timer is used.

In the case of a general timer, the timer must be reset to change the set time. A general timer has one base register therein, and since this base register is involved in both the set time change and the counter operation, it is impossible to change the set time in real time (see FIG. 1).

If you reset the timer to stop the operation and change the set time, it becomes difficult to control the system at the correct time interval in applications requiring sequential system control.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a timer circuit that can change a set time without a reset operation.

According to an aspect of the present invention for achieving the above technical problem, an interface means for performing interfacing with a system bus or an external module, and generates a timer initialization signal, a timer set time information signal, a manual load signal, an automatic load signal And counting means for performing counting control according to a setting time in response to a signal and a counting value output from the interface means, and counting means for performing counting corresponding to the setting time under control of the control means. And the control means comprises: first storage means for storing the timer set time information signal; Multiplexing means for selectively outputting the timer setting time information signal and the fed back current timer setting time information signal stored in the first storage means in response to the manual load signal, the auto load signal and the counting value detection signal; Second storage means for storing an output signal of the multiplexing means; And detection means for receiving the output signal of the second storage means and the counting value and outputting the counting value detection signal indicating whether the counting value has reached the set time.

The present invention applies a double buffer structure to change the set time of the timer in real time. Therefore, it is not necessary to increase the number of timers required for the system, and it is not necessary to reset the timer to change the timer setting time. Therefore, the system can be controlled at various and accurate time intervals in applications requiring sequential system control.

Hereinafter, preferred embodiments of the present invention will be introduced in order to enable those skilled in the art to more easily carry out the present invention.

1 is a block diagram of a timer circuit according to the present invention.

Referring to FIG. 1, the timer circuit 100 according to the present invention includes an interface module 110, a timer control module 120, and a counter module 120.

Here, the interface module 110 interfaces with a system bus or an external module and generates control signals such as a timer initialization signal, a timer setting time information signal, a manual load signal, and an automatic load signal.

The timer control module 120 controls the operation of the counter module 130 according to the set time in response to each control signal output from the interface module 110 and the counter value of the counter module 130.

In addition, the counter module 130 is controlled by the timer control module 120 and performs counting until the set time. On the other hand, the counter module 130 may be implemented as any type of counter, but preferably implemented as an up counter.                     

3 is a block diagram illustrating an implementation of the timer control module of FIG. 2.

Referring to FIG. 3, the timer control module 120 includes a first base register 222 for storing a timer setting time information signal, and a manual load signal and an end gate 228 output from the interface module 110. A multiplexer 224 for selectively outputting a timer set time information signal stored in the first base register 222 and a fed back current timer set time information signal in response to an output signal, and an output signal of the multiplexer 224. A counting value detection signal indicating whether the counting value has reached a set time by receiving the second base register 226 for storing, the output signal of the second base register 226 and the counting value output from the counter module 230. A comparator 229 for outputting a signal, and a counting value detection signal output from the comparator 229 and an end gate 22 for inputting an autoload signal output from the interface module 110. 8).

4 is an operation waveform diagram of the timer circuit of FIG. 3. Hereinafter, an operation of the timer circuit according to the present invention will be described with reference to the figure.

First, the timer set time information signal is transmitted to the timer control module 120 through the interface module 110 and stored in the first base register 222.

On the other hand, the value of the first base register 222 is when the counting operation corresponding to the set time in the counter module 130 (for example, the manual load signal is '0', the automatic load signal is '1', and gate When the output signal of 228 is '1', it is stored in the second base register 226.                     

When the timer module 130 is initialized to start the counting operation, the counter module 130 performs counting until the set time stored in the second base register 226 is reached. When the counter reaches the timer setting time, the operation ends (when the timer is in one-shot mode) or counting is repeated again (in the repeat mode).

In the case of changing the set time in the one-shot mode, a new timer set time information signal may be stored in the first base register 222 and the timer may be operated in the situation where the timer stops as in the first time.

On the other hand, when changing the set time in the repeat mode, first activate the autoload signal to '1', and then compares the counter value with the output value of the second base register 226 in which the current timer set time information is stored. Upon confirming that the set time has been reached, the counter value detection signal is activated to '1'.

Then, in starting counting again, if the auto load signal is '1', the output value of the first base register 222, in which the new set time value is stored, is loaded into the second base register 226 and counted up to the new set time. If the autoload signal is not '1', the set time stored in the first base register 226 is maintained.

In the present invention, since the double buffer structure consisting of the first base register 222 and the second base register 226 is used, the operation of changing the setting time and the operation of the counter module 130 are separated, and thus the new setting is performed. Changing the value of the first base register 222 when changing to time is independent of the operation of the counter module 130 operating based on the setting time of the second base register 226, so that the user may It is possible to operate stably even if the value of the first base register 222 is changed.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments are possible within the scope of the technical idea of the present invention.

For example, in the above-described embodiment, the case in which the AND gate 228 is used is described as an example. However, since the logic gate may vary depending on the activation level (high active, low active) of each signal, the logic gate may be replaced with another logic gate. Even if the present invention applies.

The above-described present invention enables to change the set time of the timer in real time, and thus, it is not necessary to increase the number of timers required for a system having various applications, and thus, cost and chip area reduction effects can be expected.

Claims (4)

Interface means for interfacing with a system bus or an external module, and generating a timer initialization signal, a timer set time information signal, a manual load signal, and an autoload signal, and setting in response to signals and counting values output from the interface means. Control means for performing counting control over time, and counting means for performing counting corresponding to the set time under control of the control means; The control means, First storage means for storing the timer set time information signal; Multiplexing means for selectively outputting the timer setting time information signal and the fed back current timer setting time information signal stored in the first storage means in response to the manual load signal, the auto load signal and the counting value detection signal; Second storage means for storing an output signal of the multiplexing means; And And a detection means for receiving the output signal of the second storage means and the counting value and outputting the counting value detection signal indicating whether the counting value has reached the set time. The method of claim 1, And a logic combiner for logically combining the autoload signal and the counting value detection signal. The method of claim 2, And the logic combination section comprises an end gate for inputting the autoload signal and the counting value detection signal. The method of claim 1, And said first and second storage means each comprise a base register.

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