KR100691008B1 - Entry device for test mode of memory device - Google Patents

Abstract

The present invention relates to a test mode entry device for controlling activation and deactivation of a test mode of a semiconductor device such as a memory device. According to the disclosed invention, the test mode entry device includes a test mode control unit, a plurality of address shift blocks, a test mode setting signal generation unit, a test mode latch unit, and a reset signal generation unit so that the mode register setting pulse signal The test mode setting signal is enabled as the number of consecutive actives.

Description

Entry device for test mode of memory device

1 is a block diagram of a test mode entry circuit according to the prior art;

2 is a view showing an operation waveform diagram of a conventional test mode entry circuit;

3 is a block diagram of a test mode entry circuit of a semiconductor device according to the present invention;

4 is a diagram illustrating a test mode control unit according to the present invention;

5A and 5B illustrate an example shift register in accordance with the present invention.

6 is a diagram illustrating a test mode setting signal generator according to the present invention;

7 illustrates a test mode latch unit in accordance with the present invention.

8 is a view showing a reset signal generator according to the present invention.

9A and 9B are operational waveform diagrams of a test mode entry circuit according to the present invention;

Explanation of symbols on the main parts of the drawings

200: test mode control unit 210, 220, 230: address shift block

240, latch portion 260: address decoding portion

270: reset signal generator

The present invention relates to a memory device, and more particularly, to a test mode entry device for controlling activation and deactivation of a test mode of a semiconductor device such as a memory device.

A typical semiconductor device has separate test circuits for testing in addition to the circuit portion that performs the inherent function of the semiconductor device, and also has a test mode entry circuit for entering or exiting the test mode. Doing.

That is, in the test mode of the semiconductor device, there are various test modes such as a mode for voltage regulation and a mode for compressing data, and the test mode entry circuit tests the semiconductor device to enter a specific mode among these test modes. Activate the mode. In addition, when the test is completed, the test mode entry circuit deactivates the test mode of the semiconductor device.

In this regard, Figure 1 shows a block diagram of a test mode entry circuit according to the prior art.

As shown, the test mode entry circuit according to the related art includes a test mode control unit 100, address shift blocks 110 to 130, a test mode setting signal generation unit 140, a test mode latch unit 150, and The address decoding unit 160 is provided.

The test mode control unit 100 receives the mode register setting pulse signal mrsp6 and the address signal add <7> output from the mode register setting unit (not shown), and thus the test mode entry signal tm_entry and the test mode. Output the escape signal tm_exit.

The address shift blocks 110 to 130 are composed of a plurality of shift registers shift_reg1 and shift_reg2. The address shift blocks 110 to 130 receive the address signals add <8>, add <9>, and add <10>, and are shifted signals. Outputs (add8_1 ~ 3, add9_1 ~ 3, add10_1 ~ 3). Here, the test mode entry signal tm_entry, which is an output signal of the test mode control unit 100, is used as a common clock of the shift registers shift_reg1 and shift_reg2, and the test mode exit signal tm_exit is a shift register shift_reg1. It is used as a common reset signal.

The test mode setting signal generator 140 is a decoding circuit composed of logic circuits, and receives the shifted signals add8_1 to 3, add9_1 to 3, and add10_1 to 3 from the address shift blocks 110 to 130, and combines them. The test mode setting signal tm_set is output.

The test mode latch unit 150 receives the test mode setting signal tm_set and the address combination signal tm_add output from the address decoding unit 160 to enable the test mode. In addition, the test mode latch unit 150 receives a test mode exit signal tm_exit output from the test mode control unit 100. When the test of the memory device is completed, the test mode latch unit 150 returns the memory device to a normal state.

Hereinafter, the operation of the conventional test mode entry circuit will be described with reference to FIG. 2. 2 is a view showing an operation waveform diagram of a conventional test mode entry circuit.

First, in the operation of the test mode controller 100, in order to enter the memory device into the test mode, the mode register setting pulse signal mrsp6 and the address signal add <7> are high level in synchronization with the external clock CLK. Must be entered. On the other hand, in order to exit the memory device from the test mode, the mode register setting pulse signal mrsp6 and the address signal add <7> must be input at the low level.

In addition, the conventional test mode input circuit 100 which performs the above operation is a means for preventing the memory device from entering the test mode due to disturbance such as noise, so that the address signal add <7> is high. The situation where the mode register setting pulse signal mrsp6 becomes high level while maintaining the level should be performed for three cycles. In each cycle, the address signals add <8>, add <9>, and add <10> are address shift blocks 110 to 130, where '(H, H, L), (L, H, H), (H, L, L) 'in order, and at the same time, when the address (add) for the desired test mode is input to the address decoding unit 160, the memory device enters the test mode.

More specifically, the test mode control unit 100, when the input setting pulse signal mrsp6 and the address signal add <7> are simultaneously enabled at the high level, the test mode control unit 100 may check the test mode entry signal tm_entry to the high level. Let it be.

The test mode entry signal tm_entry is input to the address shift blocks 110 to 130 and used as a common clock of the shift registers shift_reg1 and shift_reg2. Therefore, the address shift blocks 110 to 130 shift the input address signals add <8>, add <9>, and add <10> in three steps, respectively, as shown in the area 'A' of the figure. The same shift signal (add8_1 to 3, add9_1 to 3, add10_1 to 3) is transmitted to the test mode setting signal generator 140. Thereafter, the test mode setting signal generator 140 receiving the shift signals add8_1 to 3, add9_1 to 3, and add10_1 to 3 combines them, and the corresponding address signals add <8> and add <9 for three cycles. When>, add <10>) is input, the test mode setting signal tm_set enabled at the high level is output.

In conclusion, the test mode setting signal tm_set enabled at the high level and the address combination signal tm_add output from the address decoding unit 160 are input to the test mode latch unit 150 to test the memory device. Enter the mode.

As described above, in the address entry circuit according to the related art, when the address signals add <8>, add <9>, add <10> having a specific value are input in three cycles in synchronization with the external clock CLK, , Put the memory device in test mode. However, the address entry circuit according to the prior art tests the memory device if only three cycles are input, even if the address signals add <8>, add <9>, and add <10> having specific values are not continuously input. Enter the mode. Therefore, in the conventional address entry circuit, the address signals add <8>, add <9>, and add <10> have a specific value even in a normal operation of the memory device, that is, a normal operation state. When cycled, there is a problem of putting the memory device into the test mode.

Accordingly, the present invention was created to solve the problems inherent in the prior art as described above, and an object of the present invention is to switch to a test mode by a specific value of an address signal in a normal operation of a memory device. It is to provide a test mode entry device of the memory device to prevent the.

In order to achieve the above object, according to an aspect of the present invention, in the test mode entry device of the memory device, a mode register setting pulse signal and a test mode setting address are input, and the test mode setting address is enabled. A test mode control unit configured to output a test mode entrance signal at and to output a test mode exit signal when the test mode setting address is disabled; A plurality of address shift blocks outputting a signal shifted at least three times each using a plurality of address signals as the common clock; A test mode setting signal generator configured to enable and output a test mode setting signal when a value output from each address shift block matches a setting value; A test mode latch unit configured to receive the test mode setting signalized combined address, enable a test mode corresponding to the combined address, and return to a normal mode when the test mode escape signal is input; And providing a common reset signal of the plurality of address shift blocks in synchronization with the test mode escape signal, receiving an internal clock signal synchronized with an external clock, and providing the test mode entry signal at least as with the plurality of address shift blocks. And a reset signal generator for shifting three times or more to enhance the common reset signal of the plurality of address shift blocks in synchronization with the internal clock signal, thereby continuously operating the mode register setting pulse signal by the number of the address shift blocks. As a result, the test mode setting signal is enabled.

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(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a test mode entry circuit of a semiconductor device according to the present invention.

As shown, the test mode entry circuit according to the present invention includes a test mode control unit 200, address shift blocks 210 to 230, a test mode setting signal generator 240, a test mode latch unit 250, and an address. A decoding unit 260 and a reset signal generator 270.

Referring to FIG. 4, the configuration of the test mode controller 200 may include the mode register setting pulse signal mrsp6 and the address signal add <7 output from the mode register setting unit (not shown). And means 201 for outputting a test mode entry signal (tm_entry) by inputting > The NAND gate 202 which inputs the inverted signal of the address signal add <7> and the mode register setting pulse signal mrsp6, and the output signal and the power-up signal pwrup of the NAND gate 202 as inputs are tested. The NAND gate 203 outputs a mode escape signal tm_exit.

The address shift blocks 210 to 230 are composed of a plurality of shift registers shift_reg1 and shift_reg2. The address shift blocks 210 to 230 receive the address signals add <8>, add <9>, and add <10> and shift the signals ( add8_1 ~ 3, add9_1 ~ 3, add10_1 ~ 3). Here, the test mode entry signal tm_entry which is an output signal of the test mode control unit 200 is used as a common clock of the shift registers shift_reg1 and shift_reg2. For reference, an example of the shift register shift_reg1 is shown in FIG. 5A, and an example of the shift register shift_reg2 is shown in FIG. 5B.

Referring to the configuration of the test mode setting signal generator 240 with reference to FIG. 6, the test mode setting signal generator 240 is a decoding circuit composed of logic gates and includes an address signal (add <8>, add <9). a signal shifted once by > add < 10 > (add8_1, add9_1, add8_1); Two shifted signals (add8_2, add9_2, add8_2); And the three shifted signals add8_3, add9_3, and add8_3, and when these combinations match the set values, the test mode setting signal tm_set is enabled to a high level.

Referring to FIG. 7, the configuration of the test mode latch unit 250 includes a test mode setting latch unit 250 including a test mode setting signal tm_set and an address combination signal tm_add output from the address decoding unit 260. And a NAND latch 252 which receives an output signal of the NAND gate 251 and a test mode escape signal tm_exit. The test mode latch unit 250 having the above configuration receives the test mode setting signal tm_set and the address combination signal tm_add to enable the corresponding test mode. In addition, when the test mode escape signal tm_exit output from the test mode controller 200 is enabled to the high level, the test mode latch unit 250 returns the memory device to the normal state.

Referring to FIG. 8, the configuration of the reset signal generator 270 may include: a delay unit 271 that receives an internal clock clkp4 and outputs a delay after a predetermined time; An address shift block 272 for shifting and outputting the address signal add <7>; Ora means 273 for inputting an output signal of the delay unit 271, an output signal of the address shift block 272, and a test mode entry signal tm_entry; And a NAND gate 274 for outputting the reset signal rst by inputting the output signal of the OR means 273 and the inverted test mode escape signal tm_exit. Here, the address shift block 272 is configured in the same manner as the other address shift blocks 210, 220, and 230, and shifts the input signal three times and outputs it. In addition, the test mode entry signal tm_entry is used as a common clock of the shift register (not shown) provided in the address shift block 273, and the reset signal rst output through the final oracle means 274 is a shift register. Used as a common reset signal for. In addition, the internal clock clkp4 is for operating an internal circuit of the memory device and is a signal synchronized with the external clock.

Hereinafter, an operation of the test mode entry circuit according to the present invention will be described with reference to FIGS. 9A and 9B. 9A and 9B illustrate an operation waveform diagram of a test mode entry circuit according to the present invention.

In the test mode entry circuit according to the present invention, an address signal (add <8>, add <9>, add <10>) having a specific value must be inputted three cycles continuously in synchronization with an external clock CLK. Perform normal operation to enter test mode.

First, referring to FIG. 9A, when an address is continuously input, operation of a test mode entry circuit according to the present invention will be described.

 First, in the operation of the test mode controller 200, the mode register setting pulse signal mrsp6 and the address signal add <7> are high level in synchronization with the internal clock clkp4 in order to enter the memory device into the test mode. Must be entered. On the other hand, in order to exit the memory device from the test mode, the mode register setting pulse signal mrsp6 and the address signal add <7> must be input at the low level.

In addition, the test mode input circuit according to the present invention which performs the above operation is a means for preventing the memory device from entering the test mode in the normal operation, and the address signal add <7> is maintained at a high level. In this case, the situation in which the mode register setting pulse signal mrsp6 becomes high level must be continuously performed for three cycles. In each cycle, the address signals add <8>, add <9>, add <10> are input to the address shift blocks 210 to 230, and at the same time, the address signal add for the desired test mode is address decoded. When input to the unit 260, the memory device enters a specific test mode.

More specifically, the test mode control unit 200 sets the test mode entry signal tm_entry to a high level when the input setting pulse signal mrsp6 and the address signal add <7> are simultaneously enabled at a high level. Enable it.

The test mode entry signal tm_entry is input to the address shift blocks 210 to 230 and used as a common clock of the shift registers shift_reg1 and shift_reg2. Accordingly, the address shift blocks 210 to 230 shift the input address signals add <8>, add <9>, and add <10> in three steps, respectively, to the test mode setting signal generator 240. FIG. To pass. Thereafter, the test mode setting signal generation unit 240 combines the input signals to enable the test mode setting signal tm_set to a high level.

In conclusion, the test mode setting signal tm_set enabled at the high level and the address combination signal tm_add output from the address decoding unit 260 are input to the test mode latch unit 250 to test the memory device. Enter the mode.

Next, referring to FIG. 9B, when the address is not continuously input, the operation of the test mode entry circuit according to the present invention will be described.

As is well known, the test mode entry circuit according to the present invention has three cycles in which the mode register setting pulse signal mrsp6 becomes high level while the address signal add <7> is kept high level. Must be carried out continuously. However, if the test mode entry signal tm_entry is not enabled in the second cycle, as shown in the drawing, the reset signal generator 270 detects this, outputs a reset signal rst, and finally, the test mode setting signal ( tm_set) is disabled.

In other words, the reset signal generator 270 may shift the internal clock clkp4, the address signal add <7> three times through the address shift block 272, and the test mode entry signal tm_entry. When both are input at the low level, the reset signal rst which is a pulse signal is output. As a result, the reset signal rst initializes the address shift blocks 210, 220, 230, and 272 to disable the test mode setting signal, thereby preventing the memory device from being switched to the test mode.

As described above, the test mode entry circuit according to the present invention switches the memory device to the test mode only when an address signal for setting the test mode is continuously input in synchronization with an external clock. If the address signal for setting the test mode is not continuously input, by initializing the address shift block provided therein, it is possible to prevent the memory device from being switched to the test mode.

According to the above-described configuration of the present invention, as the memory device switches to the test mode only when the address signal for setting the test mode is continuously input, the memory device in the normal operation enters the test mode by the external address signal. It can prevent the conversion.

While the invention has been shown and described with reference to specific embodiments, the invention is not so limited, and it is to be understood that the invention is capable of various modifications without departing from the spirit or field of the invention as set forth in the claims below. It will be readily apparent to one of ordinary skill in the art that modifications and variations can be made.

Claims (3)

delete delete A mode register setting pulse signal and a test mode setting address are input, and a test mode entry signal is output when the test mode setting address is enabled, and a test mode exit signal is output when the test mode setting address is disabled. A test mode controller; A plurality of address shift blocks outputting a signal shifted at least three times each using a plurality of address signals as the common clock; A test mode setting signal generator configured to enable and output a test mode setting signal when a value output from each address shift block matches a setting value; A test mode latch unit configured to receive the test mode setting signalized combined address, enable a test mode corresponding to the combined address, and return to a normal mode when the test mode escape signal is input; And In synchronization with the test mode escape signal, a common reset signal of the plurality of address shift blocks is provided, an internal clock signal synchronized with an external clock is received, and the test mode entry signal is provided at least three times as with the plurality of address shift blocks. A reset signal generator for shifting abnormally to enhance the common reset signal of the plurality of address shift blocks in synchronization with the internal clock signal; And the test mode setting signal is enabled as the mode register setting pulse signal is continuously activated by the number of the address shift blocks.

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