KR20060076999A - Method for fabricating the gate oxide of semiconductor device - Google Patents

Method for fabricating the gate oxide of semiconductor device Download PDF

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KR20060076999A
KR20060076999A KR1020040115630A KR20040115630A KR20060076999A KR 20060076999 A KR20060076999 A KR 20060076999A KR 1020040115630 A KR1020040115630 A KR 1020040115630A KR 20040115630 A KR20040115630 A KR 20040115630A KR 20060076999 A KR20060076999 A KR 20060076999A
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oxide film
gate oxide
semiconductor device
gate
silicon
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KR100613098B1 (en
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김학동
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동부일렉트로닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02142—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides
    • H01L21/02148—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing silicon and at least one metal element, e.g. metal silicate based insulators or metal silicon oxynitrides the material containing hafnium, e.g. HfSiOx or HfSiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Abstract

본 발명은 반도체 소자의 게이트 산화막 제조 방법에 관한 것으로, 실리콘 기판 상에 불순물을 주입하여 웰을 형성하는 단계; 상기 실리콘 기판 상에 동시 증착 방법을 사용하여 하프늄과 실리콘 증착하는 단계 및 급속 열처리로 어닐링하는 단계로 이루어짐에 기술적 특징이 있고, 하프늄과 실리콘을 동시 증착하고, 급속 열처리로 증착된 필름을 NH3 분위기에서 어닐링하여 HfSiON을 형성함으로써 효과적으로 산화막의 두께가 증가되어 전류의 손실을 감소시키고, 소자의 특성을 향상시키는 효과가 있다.The present invention relates to a method of manufacturing a gate oxide film of a semiconductor device, comprising: forming a well by implanting impurities on a silicon substrate; It is a technical feature that consists of the step of depositing hafnium and silicon on the silicon substrate using a co-deposition method and the annealing by rapid heat treatment, the simultaneous deposition of hafnium and silicon, the film deposited by the rapid heat treatment NH 3 atmosphere By annealing at to form HfSiON, the thickness of the oxide film is effectively increased, thereby reducing the loss of current and improving the characteristics of the device.

하프늄, HfSiON, 게이트 산화막Hafnium, HfSiON, Gate Oxide

Description

반도체 소자의 게이트 산화막 제조 방법{Method for fabricating the gate oxide of semiconductor device} Method for fabricating the gate oxide film of a semiconductor device             

도 1a 및 도 1b는 종래의 폴리 실리콘 게이트 제조 방법을 나타내는 공정 단면도이다.1A and 1B are cross-sectional views illustrating a conventional polysilicon gate manufacturing method.

도 2a 내지 도 2c는 본 발명에 따른 게이트 산화막 제조 방법을 나타내는 공정 단면도이다.2A to 2C are cross-sectional views illustrating a method of manufacturing a gate oxide film according to the present invention.

본 발명은 반도체 소자의 게이트 산화막 제조 방법에 관한 것으로, 보다 자세하게는 하프늄과 실리콘을 동시에 증착하고, 급속 열처리 공정으로 어닐링하는 게이트 산화막에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a gate oxide film of a semiconductor device, and more particularly, to a gate oxide film which simultaneously deposits hafnium and silicon and anneals in a rapid heat treatment process.

일반적으로 모스형 반도체 소자는 금속-산화막-반도체의 콘덴서 구조를 사용하는 것으로, 금속 전극과 반도체 기판 사이에 인가된 바이어스에 의해서 반도체 기판 위의 산화막 바로 밑에 전류의 통로가 되어 야할 채널이 형성되고, 그것이 바 이어스의 값에 의해 제어되는 것이 기본 원리이다. 따라서, 금속 전극으로서 가장 기본적인 전극 재료인 알루미늄을 게이트 전극으로 사용해서 반도체 소자의 개발이 시도되었다.In general, the MOS type semiconductor device uses a capacitor structure of a metal-oxide film-semiconductor, and a channel to be a current path is formed directly under the oxide film on the semiconductor substrate by a bias applied between the metal electrode and the semiconductor substrate. The basic principle is that it is controlled by the value of the bias. Accordingly, development of a semiconductor device has been attempted using aluminum, which is the most basic electrode material, as a metal electrode as a gate electrode.

알루미늄 게이트의 경우에는 특히, 모스 트랜지스터의 소스/드레인 부분의 확산층을 형성한 다음 알루미늄 전극을 만들기 때문에, 알루미늄의 패턴을 접합하기 위한 글라스 마스크를 반도체 기판 상에 위치 조정할 때 오차분의 여유를 소스/드레인과 게이트 전극의 오버랩으로서 수취할 필요가 있다. In the case of an aluminum gate, in particular, since the diffusion layer of the source / drain portion of the MOS transistor is formed, and then an aluminum electrode is formed, a margin of error is provided when the glass mask for bonding the pattern of aluminum is positioned on the semiconductor substrate. It needs to be received as an overlap between the drain and the gate electrode.

상기 오버랩은 점유 패턴 면적을 증가시킴과 동시에 게이트 전극과 드레인 전극간의 궤환 용량을 증가시켜 회로의 스위칭 스피드에 중대한 영향을 미치며, 결과적으로 게이트 전극 자체의 면적이 증가되어 입력 용량을 증가시킴으로써 회로의 스위칭 스피드를 저하시킨다.The overlap increases the occupied pattern area and at the same time increases the feedback capacitance between the gate electrode and the drain electrode, which significantly affects the switching speed of the circuit. As a result, the area of the gate electrode itself is increased to increase the input capacitance, thereby switching the circuit. Decreases the speed

이에 대응하여 자기 정합 게이트 형성이 가능하도록 한 것이 실리콘 게이트 전극이다. 이것은 채널 부분의 마스킹은 게이트 전극 자체로부터 이루어지므로 마스크 정렬 오차를 고려할 필요가 전혀 없고, 게이트 전극과의 소스/드레인의 오버랩은 극히 적으며 확산층의 가로방향이 늘어난 것뿐이다. Correspondingly, the silicon gate electrode is capable of forming a self-matching gate. This masking of the channel portion is made from the gate electrode itself, so there is no need to consider the mask alignment error, the source / drain overlap with the gate electrode is extremely small and only the transverse direction of the diffusion layer is increased.

이 때문에 궤환 용량 및 게이트 용량 모두 대단히 적고, 회로의 스위칭 특성이 대폭적으로 향상된다. 그리고, 반도체 소자의 비트 라인(bit line) 등을 형성하기 위한 실리콘 게이트 기술은 게이트에 사용되고 있는 다결정 실리콘의 저항값을 저감하기 위해서 실리사이드를 형성하고 있다.For this reason, both the feedback capacitance and the gate capacitance are very small, and the switching characteristics of the circuit are greatly improved. The silicon gate technology for forming bit lines and the like of semiconductor devices forms silicides in order to reduce the resistance value of polycrystalline silicon used for the gate.

도 1a 및 도 1b는 종래의 폴리 실리콘 게이트 제조 방법을 나타내는 공정 단 면도이다. 먼저, 도 1a에 도시한 바와 같이, 실리콘 기판(1)를 열산화하여 게이트 영역의 유전체 역할을 하는 게이트 산화막(2)을 양질의 순수한 실리콘산화막(SiO2)의 얇은 막으로 열 성장시킨다. 1A and 1B are process steps illustrating a conventional polysilicon gate manufacturing method. First, as shown in FIG. 1A, the silicon substrate 1 is thermally oxidized to thermally grow the gate oxide film 2 serving as a dielectric of the gate region, into a thin film of high quality pure silicon oxide film SiO 2 .

그리고, 열 성장된 게이트 산화막(2) 상부에 반도체 소자의 비트 라인 등과 같은 게이트를 형성하기 위하여, 폴리 실리콘막(3)을 화학 기상 증착법(chemical vapor deposition ; CVD)에 의해 증착시킨다. 이때, 폴리 실리콘막(3)을 형성하기 위한 화학 기상 증착은 가열로나 급속 열처리 공정(rapid thermal processing) 장비에서 사일엔(SiH4) 가스를 공급하여 결정(grain) 형태로 성장된 폴리 실리콘막이 되도록 한다. Then, in order to form a gate such as a bit line of a semiconductor element on the thermally grown gate oxide film 2, the polysilicon film 3 is deposited by chemical vapor deposition (CVD). In this case, the chemical vapor deposition for forming the polysilicon film 3 may be a polysilicon film grown in a grain form by supplying SiH 4 gas in a heating furnace or rapid thermal processing equipment. do.

그리고, 이온 주입 공정에 의해 인(P)이나 비소(As) 등의 불순물을 주입하여 도핑 폴리 실리콘막(3)을 형성하고, 어닐링(annealing)하여 폴리 실리콘막(3)의 내부 저항을 감소시켜 폴리 실리콘 고유의 전기적 특성을 회복시킨다. 그 다음, 폴리 실리콘막(3)의 접촉 저항을 감소시키기 위하여, 폴리 실리콘막(3) 상부에 텅스텐막(4)을 증착하고, 어닐링하여 텅스텐 실리사이드(4)를 형성한다. 그 다음, 텅스텐 실리사이드(4) 상부에 포토레지스트(5)를 도포하고, 게이트 패턴의 마스크를 이용하여 포토레지스트(5)를 노광 현상함으로써, 게이트 형성을 위한 포토레지스트 패턴(5)을 형성한다.The dopant polysilicon film 3 is formed by implanting impurities such as phosphorus (P) and arsenic (As) by an ion implantation process, and then annealing to reduce the internal resistance of the polysilicon film 3. Restore the intrinsic electrical properties of polysilicon. Then, in order to reduce the contact resistance of the polysilicon film 3, a tungsten film 4 is deposited on the polysilicon film 3 and annealed to form the tungsten silicide 4. Next, the photoresist 5 is applied on the tungsten silicide 4 and the photoresist 5 is exposed to light using a mask of the gate pattern to form the photoresist pattern 5 for forming the gate.

그 다음, 도 1b에 도시한 바와 같이, 포토레지스트 패턴(5)을 마스크로 텅스텐 실리사이드(4), 폴리 실리콘막(3), 게이트 산화막(2)을 연속하여 식각한 후, 포 토레지스트 패턴(5)을 제거하여 폴리 실리콘 게이트를 완성한다.1B, the tungsten silicide 4, the polysilicon film 3, and the gate oxide film 2 are successively etched using the photoresist pattern 5 as a mask, and then the photoresist pattern ( 5) to complete the polysilicon gate.

상기와 같은 종래 기술은 소자가 집적화되고, 점점 단채널의 소자가 개발되면서 요구되는 게이트 산화막의 특성을 만족시키지 못하는 문제점이 있었다.The prior art as described above has a problem in that the device is not integrated and the short-channel device is being developed, which does not satisfy the characteristics of the gate oxide film required.

따라서, 본 발명은 상기와 같은 종래 기술의 제반 단점과 문제점을 해결하기 위한 것으로, 스퍼터링 방식으로 하프늄(Hafnium)과 실리콘을 동시 증착(Co-Sputtering)하고, 급속 열처리로 증착된 필름을 NH3 분위기에서 어닐링하여 HfSiON(Hafnium Silicate Oxide Nitride)을 형성하여 효과적으로 산화막의 두께가 증가할 수 있는 반도체 소자의 게이트 산화막 제조 방법을 제공함에 본 발명의 목적이 있다.
Accordingly, the present invention is to solve the above-mentioned disadvantages and problems of the prior art, co-sputtering hafnium and silicon in a sputtering method (Co-Sputtering), and the film deposited by rapid heat treatment is NH 3 atmosphere It is an object of the present invention to provide a method for manufacturing a gate oxide film of a semiconductor device that can be effectively annealed to form HfSiON (Hafnium Silicate Oxide Nitride) to increase the thickness of the oxide film.

본 발명의 상기 목적은 실리콘 기판 상에 불순물을 주입하여 웰을 형성하는 단계; 상기 실리콘 기판 상에 동시 증착 방법을 사용하여 하프늄과 실리콘 증착하는 단계 및 급속 열처리로 어닐링하는 단계를 포함하여 이루어진 반도체 소자의 게이트 산화막 제조 방법에 의해 달성된다.The object of the present invention is to form a well by implanting impurities on a silicon substrate; It is achieved by the method of manufacturing a gate oxide film of a semiconductor device comprising the step of depositing hafnium and silicon on the silicon substrate using a simultaneous deposition method and the annealing by rapid heat treatment.

본 발명의 상기 목적과 기술적 구성 및 그에 따른 작용효과에 관한 자세한 사항은 본 발명의 바람직한 실시예를 도시하고 있는 도면을 참조한 이하 상세한 설 명에 의해 보다 명확하게 이해될 것이다.Details of the above object and technical configuration and the effects thereof according to the present invention will be more clearly understood by the following detailed description with reference to the drawings showing preferred embodiments of the present invention.

도 2a 내지 도 2b는 본 발명에 따른 게이트 산화막 제조 방법을 나타내는 공정 단면도이다. 도 2a에 도시된 바와 같이, 실리콘 기판 상에 활성 영역에 p형 또는 n형 불순물을 주입하여 p형 또는 n형 웰(미도시)을 형성하고, STI(Shallow Trench Isolation) 방법을 이용하여 소자 분리막(미도시)을 형성한다.2A to 2B are cross-sectional views illustrating a method of manufacturing a gate oxide film according to the present invention. As shown in FIG. 2A, p-type or n-type wells are formed by implanting p-type or n-type impurities into an active region on a silicon substrate, and a device isolation layer is formed by using a shallow trench isolation (STI) method. (Not shown) is formed.

이후, 게이트 산화막을 형성하는데, 상기 게이트 산화막 제조 방법은 다음과 같다. 스퍼터를 이용한 동시 증착(Co-Sputtering) 방법을 사용하여 하프늄과 실리콘층(110)을 실리콘 기판(100) 상에 물리적인 스퍼터링 방법으로 증착한다. 상기 동시 스퍼터링 증착 방법은 상온에서 Ar 분위기로 진행하고, 진공은 400mTorr로 하며, 두께는 20Å~40Å로 증착한다.Thereafter, a gate oxide film is formed, and the method for manufacturing the gate oxide film is as follows. The hafnium and the silicon layer 110 are deposited on the silicon substrate 100 by a physical sputtering method using a co-sputtering method using sputtering. The simultaneous sputtering deposition method is carried out in an Ar atmosphere at room temperature, the vacuum is 400mTorr, the thickness is deposited in 20 ~ 40Å.

이후, 급속 열처리 방식으로 어닐링한다. 상기 급속 열처리 방식은 공정온도가 500℃~700℃이고, 공정시간은 10초~60초로 진행하는 동시에 HfSiO2 내에 질소(Nitrogen)를 주입하기 위해 NH3 분위기에서 급속 열처리 공정을 실시한다.Thereafter, annealing is performed by rapid heat treatment. The rapid thermal annealing method is a process temperature of 500 ℃ ~ 700 ℃, the processing time will be subjected to a rapid heat treatment step in a NH 3 atmosphere to inject nitrogen (Nitrogen) in the HfSiO 2 at the same time to proceed 10 seconds to 60 seconds.

이후, HfSiON(Hafnium Oxynitride)(120)을 산화막으로 폴리 실리콘 게이트를 증착한 후, 패터닝하고, 이후 일련의 반도체 공정을 거쳐 반도체 소자의 제조를 완료한다.Subsequently, a polysilicon gate is deposited on the HfSiON (Hafnium Oxynitride) 120 with an oxide film, and then patterned, and then a semiconductor device is manufactured through a series of semiconductor processes.

본 발명은 이상에서 살펴본 바와 같이 바람직한 실시예를 들어 도시하고 설명하였으나, 상기한 실시예에 한정되지 아니하며 본 발명의 정신을 벗어나지 않는 범위 내에서 당해 발명이 속하는 기술분야에서 통상의 지식을 가진 자에 의해 다양 한 변경과 수정이 가능할 것이다.Although the present invention has been shown and described with reference to the preferred embodiments as described above, it is not limited to the above embodiments and those skilled in the art without departing from the spirit of the present invention. Various changes and modifications will be possible.

따라서, 본 발명의 반도체 소자의 게이트 산화막 제조 방법은 하프늄과 실리콘을 동시 증착하고, 급속 열처리로 증착된 필름을 NH3 분위기에서 어닐링하여 HfSiON을 형성함으로써 효과적으로 산화막의 두께가 증가되어 전류의 손실을 감소시키고, 소자의 특성을 향상시키는 효과가 있다.Therefore, in the method of manufacturing a gate oxide film of the semiconductor device of the present invention, by simultaneously depositing hafnium and silicon and annealing the film deposited by rapid heat treatment in an NH 3 atmosphere to form HfSiON, the thickness of the oxide film is effectively increased to reduce current loss. It is effective to improve the characteristics of the device.

Claims (3)

반도체 소자의 게이트 산화막 제조 방법에 있어서,In the method of manufacturing a gate oxide film of a semiconductor device, 실리콘 기판 상에 불순물을 주입하여 웰을 형성하는 단계;Implanting impurities on the silicon substrate to form a well; 상기 실리콘 기판 상에 동시 증착 방법을 사용하여 하프늄과 실리콘 증착하는 단계; 및Depositing hafnium and silicon on the silicon substrate using a co-deposition method; And 급속 열처리로 어닐링하는 단계Annealing by Rapid Heat Treatment 를 포함하여 이루어짐을 특징으로 하는 반도체 소자의 게이트 산화막 제조 방법.Method of manufacturing a gate oxide film of a semiconductor device comprising a. 제 1항에 있어서,The method of claim 1, 상기 동시 증착 방법은 상온에서 Ar 분위기로 진행하고, 진공은 400mTorr, 두께는 20Å~40Å로 증착하는 것을 특징으로 하는 반도체 소자의 게이트 산화막 제조 방법.The simultaneous deposition method proceeds in an Ar atmosphere at room temperature, the vacuum is 400mTorr, the thickness of the gate oxide film manufacturing method of a semiconductor device, characterized in that the deposition to 20 ~ 40Å. 제 1항에 있어서,The method of claim 1, 상기 급속 열처리는 NH3 분위기에서 공정온도가 500℃~700℃, 공정시간은 10 초~60초로 진행하는 것을 특징으로 하는 반도체 소자의 게이트 산화막 제조 방법.The rapid heat treatment is a method of manufacturing a gate oxide film of a semiconductor device, characterized in that the process temperature in the NH 3 atmosphere 500 ℃ ~ 700 ℃, the process time proceeds from 10 seconds to 60 seconds.
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