KR20060075200A - Method of manufacturing a substrate for ips mode lcd and ips mode lcd using the method - Google Patents

Abstract

The present invention provides a process for forming a gate electrode, a gate pad, and a common electrode on a substrate (first process); Forming a gate insulating film and a semiconductor layer in order over the substrate including the gate electrode, the gate pad, and the common electrode (second step); Etching the gate insulating layer and the semiconductor layer over the gate pad to expose the gate pad and simultaneously etching the gate insulating layer and the semiconductor layer around the common electrode; Forming an etch stopper on the semiconductor layer above the gate electrode (fourth step); Forming a transparent metal layer and an opaque metal layer in order on the entire surface of the substrate including the etch stopper (a fifth step); Etching the transparent metal layer and the opaque metal layer on the etch stopper to form a source electrode and a drain electrode, and simultaneously etching the semiconductor layer, the transparent metal layer, and the opaque metal layer on the peripheral area of the gate pad and the common electrode. fair); And forming a pixel electrode and a pad electrode made of a transparent metal by removing an opaque metal layer other than the source electrode and the drain electrode (seventh step), and a substrate forming method for an IPS mode liquid crystal display device and the method The present invention relates to an IPS mode liquid crystal display device.

IPS, Etch Stopper

Description

Method of manufacturing a substrate for IPS mode LCD and IPS mode LCD using the method}

1 is a plan view of one pixel of a substrate for a conventional IPS mode liquid crystal display device.

FIG. 2 is a cross-sectional view of the I-I line of FIG. 1.

3 is a plan view of one pixel of a substrate for an IPS mode liquid crystal display according to an exemplary embodiment of the present invention.

4A to 4J are cross-sectional views of the I-I line of FIG. 3.

5A and 5B are cross-sectional views illustrating a method of forming a photoresist pattern using a diffraction mask.

6A and 6B are cross-sectional views illustrating a method of forming a photoresist pattern using a diffraction mask.

<Description of Signs of Major Parts of Drawing>

100: substrate 200: gate wiring

220: gate pad 240: gate electrode

300: common wiring 320: common electrode

430: semiconductor layer 450: etch stopper                 

460 and 470 photoresist 490 diffraction mask

540: source electrode 560: drain electrode

550: transparent metal layer 555: opaque metal layer

550a: pad electrode 550b: pixel electrode

The present invention relates to a liquid crystal display device, and more particularly to an IPS mode liquid crystal display device.

Ultra-thin flat panel displays with a display screen thickness of only a few centimeters (cm). Among them, liquid crystal displays have low operating voltages, which consume less power and can be used as portable devices. Applications range from monitors to spacecraft to aircraft.

The liquid crystal display device includes a lower substrate, an upper substrate, and a liquid crystal layer formed between the two substrates, and the arrangement of the liquid crystal layers is adjusted according to whether an electric field is applied, and thus the transmission of light is controlled to display an image.

Such a liquid crystal display device has a problem that the viewing angle is narrow. As a solution to this problem, a multi-domain liquid crystal display device for dividing domains, a vertically aligned (VA) mode liquid crystal display device, and an IPS (In-Plane Switcing) mode liquid crystal display device Devices and the like have emerged.                         

Among them, the IPS mode liquid crystal display device drives the liquid crystal through a transverse electric field generated between two electrodes formed horizontally with respect to each other.

FIG. 1 is a plan view of one pixel of a conventional IPS mode liquid crystal display substrate, and FIG. 2 is a cross-sectional view of the I-I line of FIG.

As can be seen in FIG. 1, a plurality of gate wirings 20 are formed on the substrate 10 in a horizontal direction, and gate pads 22 are formed at ends of the gate wirings 20.

A plurality of data lines 50 are formed to intersect the gate line 20 to define a pixel area, and a data pad 52 is formed at an end of the data line 50.

The thin film transistor T is formed at the intersection of the gate wiring 20 and the data wiring 50. The thin film transistor T includes a gate electrode 24 extending from the gate wiring 20, a semiconductor layer 43, a source electrode 54 extending from the data wiring 50, and the source electrode 54. The drain electrode 56 is formed to be spaced apart from each other.

In the pixel region, a pixel electrode 70 connected to the drain electrode 56 is formed, and a common electrode 32 arranged in parallel with the pixel electrode 70 extends from the common wiring 30. .

In addition, pad electrodes 70a made of a transparent metal are formed on the gate pad 22 and the data pad 52 so that the pads 22 and 52 can be connected to the driving circuit unit.

Referring to FIG. 2, the gate pad 22 and the gate electrode 24 are formed on the substrate 10, and the common electrode 32 is formed on the same layer.

The gate insulating film 40 is formed on the entire surface of the substrate 10 including the above components.

The semiconductor layer 43 is formed on the gate insulating film 40.

A source electrode 54 extending from the data line 50 and a drain electrode 56 spaced apart from the source electrode 54 are formed on the semiconductor layer 43.

A protective film 60 is formed on the entire surface of the substrate including the above components.

In addition, the pixel electrode 70 is formed to be connected to the drain electrode 56 through the contact hole of the passivation layer 60, and the pad is connected to the gate pad 22 through the contact hole of the passivation layer 60. The electrode 70a is formed.

The conventional IPS mode liquid crystal display substrate for the substrate requires a total of five mask processes.

First, a mask process is required to pattern the gate wiring 20, the gate pad 22, the gate electrode 24, the common wiring 30, and the common electrode 32, which are first formed on the substrate 10. ,

Second, one mask process is required to pattern the semiconductor layer 43,

Third, one mask process is required to pattern the data line 50, the data pad 52, the source electrode 54, and the drain electrode 56.

Fourth, one mask process is required to form a contact hole in the protective layer 60,

Fifth, one mask process is required to pattern the pixel electrode 70 in the pixel region and to pattern the pad electrode 70a connected to the gate pad 22 and the data pad 52.

As described above, the conventional IPS mode liquid crystal display substrate is completed through a total of five mask processes. In general, the mask process requires a light irradiation and developing process, and thus, the process is complicated and takes a long process time. And due to the light irradiation device there is a problem that the manufacturing cost rises.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of forming a substrate for an IPS mode liquid crystal display device to reduce the process time by reducing the mask process and to reduce the manufacturing cost.

In order to achieve the above object, the present invention provides a method of forming a gate electrode, a gate pad, and a common electrode on a substrate (first step); Forming a gate insulating film and a semiconductor layer in order over the substrate including the gate electrode, the gate pad, and the common electrode (second step); Etching the gate insulating film and the semiconductor layer on the gate pad to expose the gate pad and simultaneously etching the gate insulating film and the semiconductor layer around the common electrode; Forming an etch stopper on the semiconductor layer above the gate electrode (fourth step); Forming a transparent metal layer and an opaque metal layer in order on the entire surface of the substrate including the etch stopper (a fifth step); Etching the transparent metal layer and the opaque metal layer on the etch stopper to form a source electrode and a drain electrode, and simultaneously etching the semiconductor layer, the transparent metal layer, and the opaque metal layer on the peripheral area of the gate pad and the common electrode. fair); And forming a pixel electrode and a pad electrode made of a transparent metal by removing an opaque metal layer other than the source electrode and the drain electrode (seventh step), and a substrate forming method for an IPS mode liquid crystal display device and the method An IPS mode liquid crystal display device is provided.

As described above, the present invention provides a method capable of reducing the mask process by applying an etch stopper.

Here, it is preferable to further include a step of forming a photoresist pattern using a diffraction mask on the semiconductor layer after the second process, and ashing the photoresist pattern after the third process, because the diffraction mask This is because when the photoresist pattern using is applied, the third and fourth processes may be performed in one diffraction mask process without an additional mask process.

In addition, it is preferable to further include a step of forming a photoresist pattern using a diffraction mask on the opaque metal layer after the fifth process, and ashing the photoresist pattern after the sixth process. This is because the sixth and seventh processes may be performed in one diffraction mask process without using an additional mask process when the photoresist pattern using the photoresist pattern is applied.

In addition, in the fifth step, it is preferable to further include a step of forming an ohmic contact layer before the transparent metal layer and the opaque metal layer are sequentially formed on the entire surface of the substrate including the etch stopper. In addition, when forming the ohmic contact layer, it is preferable to further form a metal layer therebetween in order to improve the contact resistance between the ohmic contact layer and the transparent metal.

The present invention also provides an IPS mode liquid crystal display device manufactured by the above method.

As described above, the present invention provides a method of reducing the conventional five mask processes to three mask processes by using an etch stopper and a diffraction mask. Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings. Let's explain.

3 is a plan view of one pixel of the substrate for an IPS mode liquid crystal display according to the exemplary embodiment of the present invention, and FIGS. 4A to 4J are cross-sectional views of the I-I line of FIG. 3.

First, as shown in FIG. 4A, the gate electrode 240, the gate pad 220, and the common electrode 320 are formed on the substrate 100. As can be seen in FIG. 3, the gate electrode 240 extends from the gate wiring 200, the gate pad 220 is formed at the end of the gate wiring 200, and the common electrode 320 is a common wiring. It is extended from 300.

Thereafter, as shown in FIG. 6B, the gate insulating film 400 and the semiconductor layer 430 are sequentially formed on the entire surface of the substrate 100 including the gate electrode 240, the gate pad 220, and the common electrode 320. .                     

Thereafter, as shown in FIG. 6C, an etch stopper material 450 is formed on the semiconductor layer 430, and a photoresist pattern 460 is formed thereon using a diffraction mask.

A method of forming the photoresist pattern 460 is shown in detail in FIGS. 5A and 5B.

First, as shown in FIG. 5A, a photoresist layer 460 is formed on the etch stopper material 450, a diffraction mask 490 is positioned on the photoresist layer 460, and then irradiated with light. The diffraction mask 490 includes a region 490a through which light is transmitted, a region 490b through which light is blocked, and a region 490c through which only part of the light is transmitted. Thereafter, as shown in FIG. 5B, the photoresist pattern 460 is completed. At the time of development, all of the photoresist layer through which light is transmitted are removed, and the photoresist layer from which light is blocked remains as it is, and only a part of the photoresist layer through which light is partially transmitted is removed. Accordingly, the photoresist pattern 460 having the structure as shown in FIG. 4C is formed.

The etch stopper material 450 may be formed of a nitride film.

Thereafter, as shown in FIG. 4D, the gate insulating layer 400, the semiconductor layer 430, and the etch stopper material 450 on the gate pad 220 are etched to expose the gate pad 220.

In addition, while exposing the gate pad 220, the gate insulating film 400, the semiconductor layer 430, and the etch stopper material 450 around the common electrode 320 may be etched to be formed in a later process. The pixel electrode formation region is prepared.

Thereafter, the photoresist pattern 460 is ashed as shown in FIG. 4E. When the ashing process is performed, the photoresist pattern 460 in the region other than the region in which the gate electrode 240 is formed, which is a region where light is not transmitted, is removed.

Thereafter, as shown in FIG. 4F, the etch stopper material is etched using the photoresist pattern 460 as a mask, and then the photoresist pattern 460 is removed to form the semiconductor layer 430 on the gate electrode 240. The etch stopper 450 is completed.

4C to 4F, the gate insulating layer 400 and the semiconductor layer 430 are etched on the gate pad 220 to expose the gate pad 220 and at the same time, the gate insulating layer around the common electrode 320. 400 and the semiconductor layer 430 are etched to prepare a pixel electrode formation region, and an etching stopper 450 is formed on the semiconductor layer 430 on the gate electrode 240. After using the two etching process was performed. Although not shown, the gate pad 220 may be exposed by the general mask and the etching process, and the pixel electrode formation region may be prepared, and the etch stopper 450 may be formed by the general mask and the etching process. However, it is more preferable to use a diffraction mask as shown in Figs. 4C to 4F because the mask can be reduced.

Thereafter, as shown in FIG. 4G, the transparent metal layer 550 and the opaque metal layer 555 are sequentially formed on the entire surface of the substrate including the etch stopper 450, and the photoresist pattern 470 is formed on the opaque metal layer 555. do.

The transparent metal layer 550 is preferably made of ITO, and the opaque metal layer 555 may be aluminum, silver, copper, nickel, or the like used as a conventional electrode.

Although not shown, it is preferable to first form an ohmic contact layer on the entire surface of the substrate including the etch stopper 450 before forming the transparent metal 550.

In addition, when the ohmic contact layer is formed, it is preferable to further form a metal layer therebetween in order to improve contact resistance between the ohmic contact layer and the transparent metal 550.

The method of forming the photoresist pattern 470 is illustrated in detail in FIGS. 6A and 6B.

First, as shown in FIG. 6A, the photoresist layer 470 is formed on the opaque metal layer 555, the diffraction mask 490 is positioned on the photoresist layer 470, and then irradiated with light. The diffraction mask 490 includes a region 490a through which light is transmitted, a region 490b through which light is blocked, and a region 490c through which only part of the light is transmitted. Thereafter, as shown in FIG. 6B, the photoresist pattern 470 is completed. At the time of development, all of the photoresist layer through which light is transmitted are removed, and the photoresist layer from which light is blocked remains as it is, and only a part of the photoresist layer through which light is partially transmitted is removed. Accordingly, the photoresist pattern 470 having the structure as shown in FIG. 4G is formed.

Thereafter, as shown in FIG. 4H, the transparent metal layer 550 and the opaque metal layer 555 on the etch stopper 450 are etched using the photoresist pattern 470 as a mask, and the gate pad 220 is etched. The semiconductor layer 430, the transparent metal layer 550, and the opaque metal layer 555 of the peripheral region and the upper region of the common electrode 320 are etched.

Here, only the transparent metal layer 550 and the opaque metal layer 555 are etched on the etch stopper 450 by the action of the etch stopper 450, but the etch stopper is disposed on the peripheral area of the gate pad 220 and the common electrode 320. Since it is not formed, the semiconductor layer 430 is also etched together with the transparent metal layer 550 and the opaque metal layer 555.

By the above process, the source electrode 540 and the drain electrode 560 formed of the transparent metal layer 550 and the opaque metal layer 555 are formed to the left and right of the etch stopper 450.

Meanwhile, when the ohmic contact layer and the metal layer are formed below the transparent metal layer 550 in FIG. 4G, the ohmic contact layer and the metal layer will also be etched by the etching process in FIG. 4H.

Thereafter, as shown in FIG. 4I, the photoresist pattern 470 is ashed. When the ashing process is performed, the photoresist pattern 470 in a region other than the source electrode 540 and the drain electrode 560 forming region, which is not transmitted through light irradiation, is removed.

Thereafter, as shown in FIG. 4J, the opaque metal layer 555 is removed in a region other than the region where the source electrode 540 and the drain electrode 560 are formed by using the ashed photoresist pattern 470 as a mask. Thus, a pixel electrode 550b made of a transparent metal is formed, and a pad electrode 550a made of a transparent metal is formed.

After the process of FIG. 4F, the source electrode 540, the drain electrode 560, the pixel electrode 550b, and the pad electrode 550a may be formed in two etching processes after using the diffraction mask once as shown in FIGS. 4G to 4J. As described above, it may be formed by using a general mask twice. However, it is more preferable to use a diffraction mask as shown in FIGS. 6G to 6J because the mask can be reduced.

As described above, when the substrate for the IPS mode liquid crystal display device is formed in the same manner as in FIGS. 4A to 4J, the mask process is reduced to three times.                     

That is, one mask process is required to form the gate electrode 240, the gate pad 220, and the common electrode 320 in FIG. 4A, and one mask process is required to form the photoresist pattern 460 of FIG. 4C. When the photoresist pattern 470 of FIG. 4G is formed, a single mask process is required.

The present invention also provides an IPS mode liquid crystal display device manufactured by the above method.

3 and 4J, the IPS mode liquid crystal display device according to the present invention includes a substrate 100; A gate wiring 200 and a data wiring 500 formed on the substrate 100 to cross each other to define a pixel area; A thin film transistor formed at an intersection point of the gate line 200 and the data line 500; And a pixel electrode 550b and a common electrode 320 formed in the pixel region.

In this case, the thin film transistor includes a gate electrode 240, a semiconductor layer 430, an etch stopper 450, and a source electrode 540 and a drain electrode 560 in this order. Here, the source electrode 540 and the drain electrode 560 are composed of a transparent metal 550 and an opaque metal 555 stacked in this order.

In addition, the pixel electrode 550b is connected to the drain electrode 560 of the thin film transistor and is made of a transparent metal.

 The transparent metal layer 550 is preferably made of ITO, and the opaque metal layer 555 may be aluminum, silver, copper, nickel, or the like used as a conventional electrode.                     

Although not shown, an ohmic contact layer may be further formed below the source electrode 540 and the drain electrode 560. In addition, when the ohmic contact layer is formed, a metal layer may be further formed therebetween to improve contact resistance between the ohmic contact layer, the source electrode 540, and the drain electrode 560.

In addition, the common electrode 320 extends from the common wiring 300 and is arranged in parallel with the pixel electrode 550b to induce a transverse electric field together with the pixel electrode 550b.

In addition, a gate pad 220 is formed at an end of the gate line 200, and a data pad 520 is formed at an end of the data line 500. In this case, a pad metal 550a made of a transparent metal is formed on the gate pad 220 and the data pad 520.

According to the present invention by the above configuration, by using the etch stopper and the diffraction mask, the present invention does not require a protective film forming process and can reduce the conventional five mask processes to three mask processes, shortening the process time and reducing the manufacturing cost This reduces productivity.

Claims (11)

Forming a gate electrode, a gate pad, and a common electrode on the substrate (first process); Forming a gate insulating film and a semiconductor layer in order over the substrate including the gate electrode, the gate pad, and the common electrode (second step); Etching the gate insulating layer and the semiconductor layer over the gate pad to expose the gate pad and simultaneously etching the gate insulating layer and the semiconductor layer around the common electrode; Forming an etch stopper on the semiconductor layer above the gate electrode (fourth step); Forming a transparent metal layer and an opaque metal layer in order on the entire surface of the substrate including the etch stopper (a fifth step); Etching the transparent metal layer and the opaque metal layer on the etch stopper to form a source electrode and a drain electrode, and simultaneously etching the semiconductor layer, the transparent metal layer, and the opaque metal layer on the peripheral area of the gate pad and the common electrode. fair); And And forming a pixel electrode and a pad electrode made of a transparent metal by removing an opaque metal layer other than the source electrode and the drain electrode (seventh step). The method of claim 1, After the second process, a photoresist pattern using a diffraction mask is formed on the semiconductor layer, And ashing the photoresist pattern after the third step. The method of claim 1, After the fifth process, a photoresist pattern using a diffraction mask is formed on the opaque metal layer, And ashing the photoresist pattern after the sixth step. The method according to any one of claims 1 to 3, And forming an ohmic contact layer prior to the step of forming the transparent metal layer and the opaque metal layer in order on the entire surface of the substrate including the etch stopper. The method of claim 4, wherein And forming a metal layer between the ohmic contact layer and the transparent metal layer. The method according to any one of claims 1 to 3, The transparent metal layer is a substrate forming method for the IPS mode liquid crystal display device, characterized in that made of ITO. Board; Gate and data lines formed to cross each other on the substrate; A thin film transistor formed at an intersection point of the gate line and the data line, the thin film transistor having a gate electrode, a semiconductor layer, an etch stopper, and a source electrode and a drain electrode sequentially formed; A pixel electrode connected to the drain electrode of the thin film transistor; And It includes a common electrode formed in parallel with the pixel electrode, The source electrode and the drain electrode are formed by stacking transparent metal and opaque metal in order, and the pixel electrode is made of a transparent metal. The method of claim 7, wherein And an ohmic contact layer is formed under the source electrode and the drain electrode. The method of claim 8, And forming a metal layer between the ohmic contact layer, the source electrode, and the drain electrode. The method of claim 7, wherein A gate pad is formed at the end of the gate wiring line, The data pad is formed at the end of the data line, And a pad electrode made of a transparent metal is connected to the gate pad and the data pad. The method according to claim 7 or 10, IPS mode liquid crystal display device, characterized in that the transparent metal is ITO.

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