KR20060074144A - Stack package - Google Patents

Abstract

The present invention relates to a stack package, and more particularly, to a stack package in which two packages are physically and electrically stably stacked by improving the structure of the package. According to the invention there is provided a stack package comprising: a first semiconductor chip comprising a bonding pad; A first lead attached to an upper portion of the first semiconductor chip and electrically connected to a bonding pad of the first semiconductor chip by a first bonding wire; A second semiconductor chip attached to the first lead and including a bonding pad; A second lead attached to an upper portion of the second semiconductor chip and electrically connected to a bonding pad of the second semiconductor chip by a second bonding wire; A second encapsulant molding the second lead upper region including the second bonding wire; A third bonding wire electrically connecting the second lead and the first lead; And a third encapsulant for molding upper and lower regions of the first and second leads including the third bonding wire and the first semiconductor chip.

Description

Stack package

1 is a cross-sectional view showing a conventional stack package.

2 to 7 are cross-sectional views illustrating a stack package according to the present invention.

8 is a cross-sectional view illustrating a stack package according to another embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

1,11,31,41,71,81: semiconductor chip 2,12,32,42,72,82: bonding pad

3,13,33,43,73,83,92: adhesive 4,7,14,17,34,44,74,84,96: lead

5,15,35,45,47,75,85,94,95: bonding wire

6,16,46,48,76,86,93: Encapsulant 10,20: Package

91: die paddle

The present invention relates to a stack package, and more particularly, to a stack package in which two packages are physically and electrically stably stacked by improving the structure of the package.

Recently, as the miniaturization of electric and electronic products and high performance is required, various technologies for providing high capacity semiconductor modules have been researched and developed. A method for providing a high-capacity semiconductor module may include increasing the capacity of a memory chip, that is, high integration of the memory chip, which may be realized by integrating a larger number of cells in a limited space of a semiconductor chip. Can be. However, such high integration of the memory chip requires a high level of technology and a lot of development time, such as requiring a fine fine line width.

Accordingly, a stack technology has been proposed as another method for providing a high capacity semiconductor module, and such a stack package is a method of stacking two or more semiconductor chips in one package, or a stack of two or more packages. It is manufactured through.

1 is a cross-sectional view showing a conventional stack package manufactured by stacking two packages.

In the conventional stack package, the first package 10 and the second package 20, which are manufactured through individual processes, are disposed above and below, and the lead frame drawn out to the outside of each package 10 and 20 is formed. The outer leads 7 and 17 are arranged on a coaxial line and interconnected with ones having the same function. In the first package 10 and the second package 20, the semiconductor chips 1 and 11 having the bonding pads 2 and 12 are formed of the inner lead 4, 14) is attached. In addition, the bonding pads 2, 12 of the semiconductor chips 1, 11 are electrically connected to the inner leads 4, 14 by the bonding wires 5, 15, and the bonding wires 5, 15 and the semiconductor chip. The upper and lower regions of the inner leads 4, 14 including (1, 11) are molded by the encapsulants 6,16.                         

In the conventional stack package, two packages 10 and 20 are unstablely stacked on each other, and the outer leads 7 and 17 of the two stacked packages 10 and 20 are unstablely connected to each other. As a result, the outer leads 7 and 17 may be shorted, or bent and broken even in the small shaking of the two packages 10 and 20. In addition, the conventional stack package has a maximum thickness of 2.0 mm or more, thereby limiting the thinning of the package.

Accordingly, the present invention was created to solve the problems inherent in the stack package according to the prior art as described above, and an object of the present invention is that two packages are physically and electrically stably stacked, and the thickness of the package is reduced. It provides a stack package that can accomplish this.

In order to achieve the above object, according to one aspect of the invention, there is provided a stack package comprising: a first semiconductor chip comprising a bonding pad; A first lead attached to an upper portion of the first semiconductor chip and electrically connected to a bonding pad of the first semiconductor chip by a first bonding wire; A second semiconductor chip attached to the first lead and including a bonding pad; A second lead attached to an upper portion of the second semiconductor chip and electrically connected to a bonding pad of the second semiconductor chip by a second bonding wire; A second encapsulant molding the second lead upper region including the second bonding wire; A third bonding wire electrically connecting the second lead and the first lead; And a third encapsulant for molding upper and lower regions of the first and second leads including the third bonding wire and the first semiconductor chip.

According to another aspect of the invention, a stack package is provided, the package comprising: a first semiconductor chip comprising a bonding pad; A first lead attached to an upper portion of the first semiconductor chip and electrically connected to a bonding pad of the first semiconductor chip by a first bonding wire; A first encapsulant molding the first lead upper region including the first bonding wire; A die paddle attached to an upper portion of the first encapsulant; A second semiconductor chip attached over the die paddle; A second lead attached to an upper portion of the second semiconductor chip and electrically connected to a bonding pad of the second semiconductor chip by a second bonding wire; A second encapsulant molding the second lead upper region including the second bonding wire; A third lead spaced apart from the first and second leads and electrically connected to the first and second leads by third and fourth bonding wires; And a third encapsulant for molding the upper and lower regions of the third lead including the third and fourth bonding wires and the first and second leads.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a cross-sectional view illustrating a stack package according to the present invention.

In the stack package according to the present invention, the second semiconductor chip 41 is attached to the upper portion of the first lead 34 to which the first semiconductor chip 31 is attached via the adhesive 33. The attached second lead 44 is attached. In other words, the first semiconductor chip 31 having the bonding pads 32 is attached to the upper portion of the first lead 34 by the adhesive 33, and is bonded to the bonding pads 32 of the first semiconductor chip 31. The first leads 34 are electrically interconnected by first bonding wires 35. The second semiconductor chip 41 is attached to the upper portion of the first lead 34 electrically connected to the first semiconductor chip 31 by the bonding wire 35. The second lead 44 is attached to the upper portion of the second semiconductor chip 41 by the adhesive 43, and the bonding pad 42 and the second lead of the second semiconductor chip 41 are bonded by the bonding wire 45. 44 are electrically interconnected. An upper region of the second lead 44 including the bonding wire 45 electrically connecting the second semiconductor chip 41 and the second lead 44 is molded by the encapsulant 46.

When the second lead 44 having the second semiconductor chip 41 attached thereto is stacked on the first lead 34 having the first semiconductor chip 31 attached thereto, the first lead 34 and the first lead 34 may be stacked. The two leads 44 are electrically interconnected by bonding wires 47. That is, the first semiconductor chip 31 and the second semiconductor chip 41 are electrically connected to each other. The upper and lower regions of the first and second leads 34 and 44 including the bonding wires 47 and the first semiconductor chip 31 are molded by the encapsulant 48.

In the stack package having the structure as described above, the second lead 44 having the second semiconductor chip 41 attached thereto is attached to the first lead 34 having the first semiconductor chip 31 attached thereto. The first lead 34 and the second lead 44 are electrically connected to each other by a bonding wire 47. In addition, the bonding wire 47 is molded by the encapsulant 48. Accordingly, the stack package of the present invention reduces the distance between the first lead 34 and the second lead 44 and stably stacks the first lead 34 and the second lead 44. In addition, in the stack package of the present invention, the bonding wires 47 electrically connected to each other are molded by the encapsulant 48, so that the bonding wires 47 stably connect the first leads 34 and the second leads 44. Perform the connection.

Hereinafter, a manufacturing process of the stack package according to the present invention will be described with reference to FIGS. 3 to 7.

Referring to FIG. 3, the second lead 44 is attached to the upper portion of the second semiconductor chip 41 having the bonding pads 42 through an adhesive 43, and then the second semiconductor chip 41 is attached to the second semiconductor chip 41. The second lead 44 is wire bonded. That is, the bonding pads 42 and the second leads 44 of the second semiconductor chip 41 are electrically connected to each other by the bonding wires 45. Then, the upper and lower regions of the second lead 44 including the bonding wire 45 and the second semiconductor chip 41 are molded with the encapsulant 46.

Subsequently, referring to FIG. 4, upper and lower ends of the second lead 44 and the second semiconductor chip 41 are ground by grinding the upper and lower regions of the second lead 44 molded with the encapsulant 46. Allow the bottom of to be exposed. Then, plating is performed on the area A to be wire bonded at both ends of the upper end of the second lead 44. That is, plating is performed on the area A to be wire bonded of the second lead 44 in order to provide a stable electrical connection between the device to be wire bonded and the second lead 44.

Meanwhile, referring to FIG. 5, the first lead 34 is attached to the upper portion of the first semiconductor chip 31 having the bonding pads 32 through an adhesive 34, and the first semiconductor chip 31 is attached thereto. And wire bonding the first lead 34. The bonding pads 42 of the first semiconductor chip 31 are electrically interconnected with the first leads 34 by the bonding wires 35.

Next, referring to FIG. 6, the second lead 44 in which a wire bonding region A is plated on the first lead 34 electrically connected to the first semiconductor chip 31 by the bonding wire 35. Attach). In other words, the lower portion of the second semiconductor chip 41 exposed by grinding is attached to the wire bonded first lead 34. Subsequently, the plated portion of the second lead 44 and the first lead 34 are wire bonded. That is, the first lead 34 is electrically interconnected with the second lead 44 by the bonding wire 47.

Next, referring to FIG. 7, upper and lower regions of the first lead 34 including the bonding wire 47, the second lead 44, and the first semiconductor chip 31 are molded with the encapsulant 48. . Thereafter, the trimming and forming process, which is a well-known subsequent process, is performed to complete the manufacture of the stack package according to the present invention.

8 is a cross-sectional view illustrating a stack package according to another embodiment of the present invention.

In the stack package according to another embodiment of the present invention, the second semiconductor chip 41 having the second lead 44 attached thereto is attached to the first lead 34 having the first semiconductor chip 31 attached thereto. Unlike the embodiment, the first lead 74 and the second lead 84 to which the first semiconductor chip 71 and the second semiconductor chip 81 are attached are attached to the die paddle 91. In other words, the first lead 74 is attached to the upper portion of the first semiconductor chip 71 having the bonding pads 72 by the adhesive 73, and the first semiconductor chip 71 and the first lead 74 are attached to each other. ) Is electrically connected by the bonding wire 75. An area of the bonding wire 75 of the first lead 74 is molded by the encapsulant 76. The die paddle 91 is attached to the top of the first lead 74 molded with the encapsulant 76 by an adhesive 92.

The second semiconductor chip 81 is attached to the upper portion of the die paddle 91 to which the first lead 74 including the first semiconductor chip 71 is attached. The second lead 84 is attached to the upper portion of the second semiconductor chip 81 having the bonding pad 82 by an adhesive 83, and the second semiconductor chip 81 and the second lead 84 are bonded. It is electrically connected by wire 85. The area of the bonding wire 85 of the second lead 84 is molded by the encapsulant 86. Thus, two semiconductor chips 71 and 81 are stacked on the upper and lower portions of the die pad 91. The first and second leads 74 and 84, which are physically and electrically connected to the two semiconductor chips 71 and 81, are connected to the first and second leads 74 and 84 by bonding wires 94 and 95. It is then electrically connected to the third lead 96 arranged. That is, the first semiconductor chip 71 and the second semiconductor chip 81 are electrically connected to each other. The upper and lower regions of the third lead 96 including the first and second leads 74 and 84 and the bonding wires 94 and 95 are molded by the encapsulant 93.

A stack package having such a structure can also implement the same effects as in the previous embodiment.

According to the configuration of the present invention as described above, the two packages are stably stacked, it is possible to electrically connect the two packages by the sealing agent. As a result, the reliability of the package can be secured, and the package can be made thinner.                     

While the invention has been shown and described with reference to specific embodiments, the invention is not so limited, and it is to be understood that the invention is capable of various modifications without departing from the spirit or field of the invention as set forth in the claims below. It will be readily apparent to one of ordinary skill in the art that modifications and variations can be made.

Claims (2)

A first semiconductor chip including a bonding pad; A first lead attached to an upper portion of the first semiconductor chip and electrically connected to a bonding pad of the first semiconductor chip by a first bonding wire; A second semiconductor chip attached to the first lead and including a bonding pad; A second lead attached to an upper portion of the second semiconductor chip and electrically connected to a bonding pad of the second semiconductor chip by a second bonding wire; A second encapsulant molding the second lead upper region including the second bonding wire; A third bonding wire electrically connecting the second lead and the first lead; And And a third encapsulant for molding upper and lower regions of the first and second leads including the third bonding wire and the first semiconductor chip. A first semiconductor chip including a bonding pad; A first lead attached to an upper portion of the first semiconductor chip and electrically connected to a bonding pad of the first semiconductor chip by a first bonding wire; A first encapsulant molding the first lead upper region including the first bonding wire; A die paddle attached to an upper portion of the first encapsulant; A second semiconductor chip attached over the die paddle; A second lead attached to an upper portion of the second semiconductor chip and electrically connected to a bonding pad of the second semiconductor chip by a second bonding wire; A second encapsulant molding the second lead upper region including the second bonding wire; A third lead spaced apart from the first and second leads and electrically connected to the first and second leads by third and fourth bonding wires; And And a third encapsulant for molding the upper and lower regions of the third lead including the third and fourth bonding wires and the first and second leads.

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