KR20060073426A - Fast fourier transform processor in ofdm system and transform method thereof - Google Patents

Abstract

The present invention relates to a fast Fourier transform processor and its conversion method in an orthogonal frequency division multiplexing system.

The fast Fourier transform processor of the present invention receives the specified data, performs a first butterfly operation, and then performs a first operation based on the first butterfly calculated data and performs a second butterfly operation. The second butterfly operation is performed based on the second butterfly operation data, and then the third butterfly operation is performed. Thereafter, after performing the third operation based on the variable input multiplication based on the third butterfly calculated data, the first butterfly operation is repeatedly performed.

알고리즘을 이용하는 고속 푸리에 변환 프로세서는 하드웨어 비용 및 전력 소모를 줄이며, 특히 트위들 팩터 생성에 관한 하드웨어의 면적을 효율적으로 감소시킬 수 있는 효과가 있다. 또한, Radix-

알고리즘에 사용에 따른 연산 속도의 증가로 인하여 MIMO Detecor 및 등화기의 신호 처리 시간이 발생되어 모뎀의 성능을 향상시키는 효과가 있다.According to the invention, Radix-

Fast Fourier transform processors using algorithms reduce hardware cost and power consumption, and can effectively reduce the area of hardware, particularly with regard to tween factor generation. In addition, Radix-

Due to the increase in the computational speed according to the algorithm, the signal processing time of the MIMO Detecor and the equalizer is generated, thereby improving the performance of the modem.

Fast Fourier Transform, FFT, Butterfly Arithmetic, OFDM, RADIX, DIF

Description

Fast Fourier Transform Processor in Orthogonal Frequency Division Multiplexing System and Its Transformation Method {FAST FOURIER TRANSFORM PROCESSOR IN OFDM SYSTEM AND TRANSFORM METHOD THEREOF}

알고리즘을 사용한 FFT 내부 신호 흐름도이다. 1 is a Radix- according to the prior art.

FFT internal signal flow using the algorithm.

2 is an input data processing timing diagram of an FFT processor using a DIT method according to the prior art.

3 is a block diagram of a receiver using a general OFDM scheme.

알고리즘을 이용한 FFT 프로세서의 세부구성도이다.4 is a Radix- according to an embodiment of the present invention.

Detailed diagram of FFT processor using algorithm.

알고리즘을 이용한 FFT 프로세서의 내부 신호 흐름도이다.5 is a Radix- according to an embodiment of the present invention.

Internal signal flow diagram of an FFT processor using an algorithm.

6 is a block diagram of input data processing timing of an FFT processor using a DIF scheme according to an embodiment of the present invention.

7 is a flowchart illustrating a detailed operation method of a DIF FFT processor according to an embodiment of the present invention.

The present invention relates to a fast Fourier transform (FFT) processor in an orthogonal frequency division multiplexing communication system, and more particularly, orthogonal frequency division multiplexing (hereinafter referred to as "OFDM") communication system. The present invention relates to a fast Fourier transform processor using a DIF (Decimation In Frequency (DIF)) method and a conversion method thereof.

With the development of digital communication technology, the need and demand for a technology capable of transmitting high-capacity data at high speeds have risen, so that orthogonal frequency division multiplexing (OFDM) communication technology, which is one of high-speed communication technologies, has become common.

OFDM converts serial data to be transmitted into parallel data and transmits each parallel data on a plurality of subcarriers, and there is orthogonality between the subcarriers. For this reason, the bandwidth used is significantly reduced compared to frequency division multiplexing (FDM). In addition, since the length of the symbol is increased, it has a strong characteristic in the multipath fading channel.

Although many oscillators and filters are required to implement an OFDM communication system, they can be replaced by an inverse fast fourier transformer (IFFT) and an FFT.

FFT is a design technique having a large weight in a communication system using an OFDM scheme, and a block using a large portion of the power consumption of the communication system. Therefore, in designing an FFT, a technique for efficiently reducing circuit size and power plays an important role in efficiently implementing an entire communication system.

There are many ways to implement FFT, but there are typical ways of using memory and pipeline.

In the memory-using method, a single Radix-r processor is used to read and process r input values stored in the memory one by one, and then store them in the memory repeatedly. The number of operations to be processed is (N / r) logrN.

Where N represents the length to be FFTed. This method of using memory has the advantage of low cost and low power consumption in hardware, but has a disadvantage of slow processing speed compared to the pipeline method. Therefore, this structure is suitable for applications where there is a margin in terms of FFT processing time. Such applications include digital audio broadcasting (DAB).

On the other hand, in the pipeline implementation, multiple Radix-r processors are arranged in series, and a buffer is inserted between the processors, so that each processor processes the processor simultaneously. At this time, the number of operations used in the pipeline is the same as the method using the memory.

Thus, this structure is suitable for applications requiring short FFT processing time. Such application fields include WLAN and most wireless communication systems that are currently being standardized.

A conventional FFT processor processing method includes a "Fast Fourier Transform Processor capable of reducing the size of a memory" disclosed in Korean Patent Application No. 10-2002-0074419. This conventional technique generally uses a tween factor generator consisting of an N / 16 + 1 word size memory, an address generator, a multiplexer, and a control block for the N / 2 words of memory for the number N of data to be FFTed. The present invention discloses an FFT processor implemented with an efficient area in hardware implementation.

방법으로, 수학적인 정의는 수학식 1과 같다.The technique used in this conventional FFT implementation is Radix-

In a way, the mathematical definition is equal to equation (1).

는 트위들 팩터를 의미한다. 또한, H(k)는 수학식 2와 같다.here

Means the tween factor. In addition, H (k) is the same as the equation (2).

Here, x (n) is data input to the FFT.

알고리즘을 사용한 FFT 내부 신호 흐름도이다. 1 is a Radix- according to the prior art.

FFT internal signal flow using the algorithm.

알고리즘을 사용하는 경우, 트위들 팩터를 입력으로 받아 동작하는 곱셈기(40)가 3개가 존재하며 각각의 트위들 팩터는 제어부(30)의 제어에 의해 생성된다.As shown in FIG. 1, the input data passes through the butterfly operator 20 and then flows by the controller 30 to the memory 10 or to the butterfly operator 20 connected to the next stage of the memory. The 128-point FFT takes seven of these butterfly operations. After passing through the butterfly calculation unit 20, the real part and the imaginary part are exchanged, or the multiplication of the tweed factor is performed. Radix-

In the case of using the algorithm, there are three multipliers 40 which operate by receiving a tween factor as an input, and each tweed factor is generated by the control of the controller 30.

The FFT operation can be divided into two types, a DIT (Decimation In Time) method and a DIF (Decimation In Frequency) method. In the DIT method, the result values of the FFT processor are rearranged in a bit reverse RAM and processed. In the DIF method, the FFT processor waits for a signal to be processed at a time and processes the FFT operation.

2 is an input data processing timing diagram of an FFT processor using a DIT method according to the prior art.

As shown in FIG. 2, when the DIT method according to the related art is used, when the fourth OFDM symbol starts to accumulate in the input buffer 50 inside the FFT processor, the FFT processor operation data is output to the MIMO detector. .

Since the DIT method according to the prior art realigns the result values of the FFT processor, a problem occurs that the processing speed becomes slow when the number of points of the FFT processor is large or when the signal processing delay of the FFT processor should be short. .

의 알고리즘을 이용하여 구현한 FFT 프로세서는 하드웨어적으로 곱셈기의 면적이 85%정도를 점유하여 하드웨어상 장치의 크기가 커지는 문제점이 발생한다. In addition, conventional RADIX-

In the FFT processor implemented using the algorithm of the hardware, the area of the multiplier occupies about 85% in hardware, causing a problem in that the size of the device on the hardware increases.

Accordingly, an object of the present invention to solve the above problems is to provide a fast Fourier transform (FFT) processor and a conversion method that can increase the processing speed and reduce the hardware size.

A fast Fourier transform (FFT) processor according to an aspect of the present invention for solving the above technical problem,

A Fast Fourier Transform Processor of Decimation In Frequency (DIF) Method in Orthogonal Frequency Division Multiplexing System,

연산을 수행하는 버터플라이 연산기; 상기 버터플라이 연산기의 특정 연산에 따라 곱셈 연산을 수행하는 다수의 곱셈기; 상기 다수의 곱셈기의 연산을 위한 특정 주소를 갖는 다수의 트위들 팩터를 저장하는 트위들 팩터 저장부; 및 데이터 흐름에 관한 제어를 하며, 상 기 입력버퍼로부터 전달 받은 데이터에 기초하여 상기 트위들 팩터 저장부의 트위들 팩터값을 읽어 상기 다수의 곱셈기로 제공하는 메모리 제어신호 생성부를 포함한다.An input buffer that receives a plurality of data and stores the data sequentially; Radix- using a tween factor based on the data stored in the input buffer

A butterfly calculator for performing operations; A plurality of multipliers for performing multiplication operations according to a specific operation of the butterfly operator; A tweet factor storage unit for storing a plurality of tweet factors having specific addresses for the operation of the plurality of multipliers; And a memory control signal generation unit configured to control data flow and read a tweet factor value of the tweet factor storage unit based on the data received from the input buffer and provide the plurality of multipliers to the multiplier.

A fast Fourier transform (FFT) method according to another aspect of the present invention,

A fast Fourier transform method according to the DIF (Decimation In Frequency) method in an orthogonal frequency division multiplexing system,

a) receiving specific data to perform a first butterfly operation; b) performing a specified first operation based on the first butterfly calculated data, and performing a second butterfly operation based on a result of the first operation; c) performing a specified second operation using a fixed input value based on the second butterfly calculated data, and performing a third butterfly operation based on the result of the second operation; And d) performing a variable input multiplication operation on the third butterfly-operated data to perform a specified third operation, until the fast Fourier transform on the specific data is completed. d) repeating the steps.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted for simplicity of explanation, and like reference numerals designate like parts throughout the specification.

Throughout the specification, when a part is said to "include" a certain component, it means that it can further include other components, except to exclude other components unless otherwise stated.

을 이용한 DIF방식의 FFT 프로세서 및 그 동작 방법에 대하여 도면을 참고로 하여 상세하게 설명한다.Now Radix- in an OFDM system according to an embodiment of the present invention

A DIF type FFT processor and an operation method thereof will be described in detail with reference to the accompanying drawings.

3 is a block diagram of a receiver using a general OFDM scheme.

As shown in FIG. 3, a commonly used OFDM receiver includes a reception front end block 100, an FFT processor 200, a MIMO detector 300, a reception data processing block 400, and an equalizer 500. Include.

In general, the signal received through the antenna is input to the FFT processor 200 through the Rx Front End Blocks 100. The FFT processor 200 performs an FFT operation based on the input signal and transmits the result value to the MIMO detector (Multiple-Input, Multiple-Output Detector) 300.

The MIMO detector 300 separates the input signal, performs multiple processing, and transmits the received signal to the received data processing block 400.

At this time, the FFT processor 200 is operated by the DIF method so that the data stored in the input buffer is stored in the memory in the normal order and outputted in the reverse order from the memory after the FFT operation is completed.

The equalizer 500 compensates for the signal of the FFT processor 200 to compensate for the rapidly increasing intersymbol interference during high speed transmission.

In the above, the signal transmission of the receiver of the OFDM method generally used has been described. In general, the OFDM method has high frequency efficiency, and can compensate for the rapidly increasing symbol-to-symbol interference during high-speed transmission with a simple single tap equalizer. Since the FFT can be implemented at high speed, it is used as a transmission method for high-speed data wireless communication. Lose.

알고리즘을 사용하여 FFT연산을 수행하는 FFT 프로세서의 세부구성에 대해 설명한다.Next is Radix- according to an embodiment of the present invention.

The detailed configuration of the FFT processor that performs the FFT operation using the algorithm will be described.

알고리즘을 이용한 FFT 프로세서의 세부 구성을 도시한 블록도이다.4 is a Radix- according to an embodiment of the present invention.

A block diagram showing a detailed configuration of an FFT processor using an algorithm.

알고리즘을 이용한 FFT 프로세서로써, 입력버퍼(250), RAM(270), 버터플라이(BF)연산기(260), 트위들 팩터 저장부(280), 가변 입력 곱셈기(240), 고정 입력 곱셈기(230), 어드레스 컨트롤러(210)를 포함한다.As shown in Fig. 4, the present invention relates to Radix-.

As an FFT processor using an algorithm, an input buffer 250, a RAM 270, a butterfly (BF) operator 260, a tweed factor storage unit 280, a variable input multiplier 240, a fixed input multiplier 230 And an address controller 210.

The input buffer 250 receives N data and stores the data sequentially.

The data stored in the input buffer 250 is stored in the memory (RAM) 270 in the normal order, and is output from the memory (RAM) 270 in the reverse bit sequence after the FFT operation is completed.

The address controller 210 generates input / output address values of the memory (RAM) 270 and the butterfly operator 260.

의 알고리즘을 이용한 연산 처리를 한다.The butterfly operator 260 reads the data from the input buffer 250 one by one and radix-

Computation processing using the algorithm of.

The RAM 270 stores data input through the butterfly operator 260.

The tweed factor storage unit 280 provides data of an address corresponding to a data value stored in the memory control signal generator 295 at the request of the memory control signal generator 295.

In this case, the tweed factor storage unit 280 may include a first tweed factor storage unit (not shown) that stores 16 FFT point values and a second tweed factor storage unit (not shown) that can store 128 FFT point values. Not included).

The memory control signal generator 295 controls all data flows in the FFT processor 200, and based on the data received from the input buffer 250, the tween factor value of the tweed factor storage unit 280. It is read and provided to the variable input multiplier 240.

The fixed input multiplier 230 is a multiplier having a fixed input value as an input, and is implemented by solving in shift and add form, and multiplies the output value of the butterfly operator 260 based on the fixed input value. Do it.

The variable input multiplier 240 multiplies the output value of the butterfly operator 260 based on the tween factor received from the memory control signal generator 280.

알고리즘을 이용한 FFT 프로세서 내부의 신호 흐름도이다.5 is a Radix- according to an embodiment of the present invention.

A signal flow diagram inside an FFT processor using an algorithm.

알고리즘에 의한 신호 처리를 하게 된다.As shown in FIG. 5, the FFT processor 200 uses Radix− based on sequential data input from the input buffer 250.

Signal processing is performed by an algorithm.

The input data is stored in the memory (RAM) 270-1 by the memory control signal generator 295 through an operation by the first butterfly calculator 260-1 and at the same time, a second butterfly calculator 260-2. Input for operation by). In the case of the 128-point FFT, the butterfly operation is performed seven times, and after performing the butterfly operation in the butterfly operator 260, the real part and the imaginary part are exchanged or multiplied by the tween factor. .

At this time, the operation of exchanging the real part and the imaginary part exchanges a value stored in the memory control value generator 295 corresponding to Real and Imaginary, and then converts the value converted into Imaginary. Refers to an operation to sign-convert and store.

알고리즘을 사용하는 경우에 FFT프로세서(200)는 트위들 팩터를 입력으로 받아 동작하는 가변 입력 곱셈기(240)를 2개가 포함한다. Radix-

In the case of using an algorithm, the FFT processor 200 includes two variable input multipliers 240 that operate by receiving a tween factor as an input.

In addition, the two fixed input multipliers 230 have one fixed input value, and are implemented by solving in the form of Shift And Add to obtain a significant gain over the prior art in terms of hardware cost and power consumption.

알고리즘에 대한 수학적인 정의는 수학식 3과 같다.Radix-

The mathematical definition of the algorithm is shown in Equation 3.

는 트위들 팩터를 의미한다. 또한, T(k)는 수학식 4와 같다.here,

Means the tween factor. In addition, T (k) is the same as the equation (4).

Here, H (n) is data input to the FFT processor.

알고리즘은 Radix-

알고리즘을 수학적으로 한번 더 해석하여 하드웨어 구조를 최적화하여 준다.As shown in Equations 3 and 4 above, Radix-

The algorithm is Radix-

The algorithm is interpreted mathematically once more to optimize the hardware structure.

6 is a block diagram of input data processing timing of an FFT processor using a DIF scheme according to an embodiment of the present invention.

을 이용하는DIF방식의 FFT프로세서(200)는 내부의 입력 버퍼(250)에 세 번째 OFDM 심볼이 쌓이 기 시작할 때 MIMO 디텍터(300)로 FFT 연산이 끝난 데이터를 출력한다.As shown in Figure 6, Radix- according to an embodiment of the present invention.

The FFT processor 200 using the DIF method outputs data after the FFT operation is completed to the MIMO detector 300 when the third OFDM symbol starts to accumulate in the internal input buffer 250.

Since the FFT operation completion time point of the FFT input data is increased by 1 OFDM symbol, the time required for the MIMO detector 300 and the equalizer 500 to process the signal is generated, thereby improving the performance of the modem.

Hereinafter, a detailed operation method of a DIF FFT processor according to an embodiment of the present invention will be described in detail with reference to FIG. 7.

First, the input buffer 250 of the FFT processor 200 according to the embodiment of the present invention receives the input data from the reception front end block 100 (S100).

At this time, 64 points corresponding to half of the number of FFT points among the received input data are stored in the RAM 270 and are sequentially transmitted to the butterfly operator 260.

알고리즘에 기초한 연산처리를 하여 메모리 제어신호 생성부(295)로 전송한다(S101).Next, the butterfly operator 260 radix-transmits the received data.

An algorithm-based arithmetic processing is performed and transmitted to the memory control signal generator 295 (S101).

Subsequently, the memory control signal generator 295 performs a -j operation based on the input data stored in the RAM 270 (S102), and transmits the result value to the butterfly operator 260.

알고리즘에 의한 연산을 한 후 연산된 결과 값을 RAM(270)에 저장한다(S103).The butterfly operator 260 generates Radix- based on the input data.

After the calculation by the algorithm, the calculated result is stored in the RAM 270 (S103).

In this case, 32 points, which are half of the input data, are stored in the RAM 270 as input data transmitted to the butterfly operator 260 for the butterfly operation.

Next, the fixed input multiplier 230 multiplies the calculated result by the fixed input value and transmits the result to the next butterfly operator 260 (S104).

Sixteen points, which are half of the input data, of the input data transmitted to the butterfly operator 260 is stored in the RAM 270.

알고리즘에 의한 연산을 한 후 연산된 결과 값을 RAM(270)에 저장한다.The butterfly operator 260 then uses Radix- based on the input data.

After the calculation by the algorithm, the calculated result is stored in the RAM 270.

Subsequently, the variable input multiplier 240 multiplies the calculated result value by a tween factor, which is a variable input value, and transmits the result to the butterfly operator 260.

Here, the tweet factor is a plurality of specific values stored in the first and second tweet factor factor storages (not shown), and is determined by the memory control call generator 295.

In addition, eight points, which are half of the input data sent to the butterfly operator 260, are stored in the RAM 270.

알고리즘에 의한 연산을 한 후 연산된 결과 값을 RAM(270)에 저장한다.The butterfly operator 260 then uses Radix- based on the input data.

After the calculation by the algorithm, the calculated result is stored in the RAM 270.

Then, the memory control signal generator 295 performs a -j operation based on the input data stored in the RAM 270 (S108), and transmits the result value to the butterfly operator 260.

알고리즘에 의한 연산을 한 후 연산된 결과 값을 RAM(270)에 저장한다.Subsequently, the butterfly operator 260 generates Radix- based on the input data.

After the calculation by the algorithm, the calculated result is stored in the RAM 270.

At this time, four points, which are half of the input data transmitted to the butterfly operator 260, are stored in the RAM 270.

알고리즘에 의한 연산을 한 후 연산된 결과 값을 RAM(270)에 저장한다.The butterfly operator 260 then uses Radix- based on the input data.

After the calculation by the algorithm, the calculated result is stored in the RAM 270.

The fixed input multiplier 230 then multiplies the calculated result by a fixed input value and transmits the result to the butterfly operator 260.

At this time, two points, which are half of the input data transmitted to the butterfly operator 230, are stored in the RAM 270.

알고리즘에 의한 연산을 한 후 연산된 결과 값을 RAM(270)에 저장한다.Next, the butterfly operator 230 uses Radix- based on the input data.

After the calculation by the algorithm, the calculated result is stored in the RAM 270.

In addition, the variable input multiplier 240 multiplies the calculated result value by a tweed factor which is a variable input value and transmits the result to the butterfly operator 260.

Here, the tweet factor is a plurality of specific values stored in the first and second tweet factor factor storages, and is determined by the memory control signal generator 295.

At this time, one point, which is half of the input data transmitted to the butterfly operator 260, is stored in the RAM 270.

알고리즘에 의한 연산을 한 후 연산된 결과 값을 RAM(207)에 저장하고, 연산된 결과 값을 MIMO 디텍터(300)로 전송함으로써, 본 발명의 실시예에 따른 DIF방식의 FFT 처리가 완료된다.Next, the butterfly operator 260 generates Radix- based on the input data.

After the calculation by the algorithm, the calculated result value is stored in the RAM 207, and the calculated result value is transmitted to the MIMO detector 300, thereby completing the FFT processing of the DIF method according to the embodiment of the present invention.

Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited thereto, and various other changes and modifications are possible.

을 이용한 DIF방식의 FFT 프로세서는 Radix-

알고리즘을 수학적으로 한번 더 해석한 Radix-

알고리즘을 이용하여 하드웨어 비용 및 전력 소모를 줄이며, 특히 트위들 팩터 생성에 관한 하드웨어의 면적을 효율적으로 감소시킬 수 있는 효과가 있다.According to the invention, Radix-

The DIF FFT processor using Radix-

Radix- One More Mathematical Interpretation of Algorithms

Algorithms can be used to reduce hardware cost and power consumption, and in particular, to effectively reduce the area of hardware related to the tween factor generation.

알고리즘에 사용에 따른 연산 속도의 증가로 인하여 MIMO 디텍터 및 등화기가 모뎀 성능 향상을 위한 신호 처리에 사용할 시간이 발생하는 효과가 있다.In addition, Radix-

Due to the increase in the computational speed according to the algorithm, the MIMO detector and equalizer takes time to be used for signal processing to improve modem performance.

Claims (10)

In a fast Fourier transform processor of the DIF (Decimation In Frequency) method in an orthogonal frequency division multiplexing system, An input buffer for receiving and storing a plurality of data; Radix- using a tween factor based on the data stored in the input buffer

A butterfly calculator for performing operations; A plurality of multipliers for performing multiplication operations according to a specific operation of the butterfly operator; A tweet factor storage unit for storing a plurality of tweet factors having specific addresses for the operation of the plurality of multipliers; And A memory control signal generation unit which controls data flow and reads the tween factor value of the tweed factor storage unit based on the data received from the input buffer and provides the plurality of multipliers to the multipliers. Fast Fourier transform processor including. The method of claim 1, A first storage unit which stores data calculated by the butterfly operator; And An address controller configured to generate input / output address values of the first storage unit and the butterfly operator Fast Fourier transform processor further comprising. The method of claim 2, The plurality of multipliers, A fixed input multiplier for calculating using a specific constant fixed according to a specific operation of the butterfly operator; And Variable input multiplier for calculating using a tween factor according to a specific operation of the butterfly operator Fast Fourier transform processor including. The method according to claim 2 or 3, And a complex operation performed by the memory control signal generator is a -j operation. The method of claim 4, wherein Radix-

The operation is

here,

Is the tweed factor,

Is the relation

   Here, H (n) is data input to the fast Fourier transform processor. Fast Fourier Transform Processor. The method of claim 4, wherein The -j operation is a fast Fourier transform processor, characterized in that for converting the value corresponding to the real value and the imaginary value stored in the first storage unit, the sign converted to the imaginary value to be stored in the first storage unit . The method of claim 3, And said fixed input multiplier is implemented in shift and add form. In the fast Fourier transform method according to the DIF (Decimation In Frequency) method in an orthogonal frequency division multiplexing system, a) receiving specific data to perform a first butterfly operation; b) performing a specified first operation based on the first butterfly calculated data, and performing a second butterfly operation based on a result of the first operation; c) performing a specified second operation using a fixed input value based on the second butterfly calculated data, and performing a third butterfly operation based on the result of the second operation; And d) performing a variable input multiplication operation on the third butterfly operation data to perform a specified third operation Including, Repeating steps a) to d) until the fast Fourier transform on the specific data is completed; A fast Fourier transform method, characterized in that. The method of claim 8, The butterfly operation is Radix-

A fast Fourier transform method, characterized in that the operation. The method of claim 9, The specified first operation is a -j operation, The specified second operation is a fixed multiplication operation by a specific integer, The specified third operation is a variable multiplication operation using a tween factor. A fast Fourier transform method, characterized in that.

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