CN100585583C - 3780 point discrete Fourier transform processor - Google Patents

Abstract

The invention discloses a novel 3780 points DFT processor, which relates to a digital television terrestrial broadcasting system. The processor has one of the following two structures, of which the first structure comprises 140 27 points DFT processors, a complex multiplier, a subscript mapping processor and 27 140 points DFT processors in turn; the second structure comprises the 27 140 points DFT processors, the complex multiplier, the subscript mapping processor and the 140 27 points DFT processors. As for input information including channel impulse response (CIR) vector, the 3780 points DFT processor with the first structure also comprises pruning algorithm to remove the redundant operation in the processor related to zero element in CIR vector. Compared with the prior art, the 3780 points DFT processor provided by the invention effectively reduces the multiplication operation quantity and system power dissipation. Moreover, the invention further reduces the multiplication and addition operation quantity of the processor by pruning algorithm according to the natural characteristics of the CIR vector.

Description

The sharp leaf transformation processor of 3780 point discrete Fouriers

Technical field

(Discrete Fourier Transform, DFT) processor relate in particular to a kind of 3780 DFT processors that are used for digital tv ground broadcasting to the present invention relates to a kind of discrete Fourier transform.

Background technology

In the standard of the digital tv ground broadcasting that recent China announces, a kind of 3780 DFT processors that can be applicable to OFDM (OFDM) modulation system and demodulation mode have been adopted, consult document [1]: State Standard of the People's Republic of China GB 20600-2006: " digital television ground broadcast transmission system frame structure, chnnel coding and modulation ", in August, 2006.Problem as realization aspects such as calculation of complex, power consumption are big appears easily in the DFT processor of (as 3780 points) of counting greatly, and wherein in the power consumption broad aspect, the DFT processor of counting greatly generally can take most of power consumption of total system.Therefore, count greatly effective implementation of DFT processor seems important to the exploitation of system.

Clearly, composite number 3780 is not 2 integral number power, but the product of two or more integers.Like this, reducing DFT processor operations quantitative aspects, decomposition algorithm is a kind of effective and efficient manner.For example: if N (counting)=RQ, a N point DFT processor can be expressed as the synthetic of synthesizing of R Q point DFT processor or Q R point DFT processor so, and the implementation of this decomposition can effectively reduce the operand of processor.If N has a plurality of factors (N=3780 belongs to this kind), then this N point DFT processor can be realized by the DFT processor cascade of each factor point of N.Compare with the algorithm that based on N is 2 integral number power, adopt the N point DFT processor of decomposition algorithm to need comparatively complicated subscript mapping processing.However, if the factor that decomposes is relatively prime in twos, (prime factor algorithm PFA) can be used to reduce the required multiply operation of DFT processor to prime factor algorithm.

The mode that composite number 3780 is resolved into less integer has a lot, and Fig. 1 is exactly the structured flowchart that existing a kind of 3780 DFT processors resolve into less integral point DFT processor.3780 DFT processors shown in Figure 1 can be consulted document [2]: No. the 01140060.9th, Chinese patent, the day for announcing: on August 13rd, 2003 and [3]: " Z.-X.Yang; Y.-P.Hu, C.-Y.Pan, and L.Yang; " Design of a 3780-pointIFFT processor for TDS-OFDM; " IEEE Trans.Broadcasting, vol.48, no.1, pp.57-61, March 2002. ".These 3780 DFT at first are broken down into 63 DFT 1 ' and 60 DFT 2 ', and wherein 63 DFT 1 ' further are broken down into 7 DFT and 9 DFT, because 7 and 9 is relatively prime, can adopt PFA to carry out the subscript mapping and handle.Similarly, 60 DFT 2 ' can be broken down into and 15 DFT 3 ' at 4, and since 4 and 15 relatively prime, also can adopt PFA to carry out the subscript mapping and handle.15 DFT further resolve into and 5 DFT at 3, because 3 and 5 is relatively prime, PFA is used for the subscript mapping once more to be handled.

Small point (3 points, 4 points, 5 points, 7 points, 9 points) DFT processor can adopt Wei Nuogela Fourier Tranform algorithm (Winograd Fourier transform algorithm, WFTA) realize, adopt the DFT processor of WFTA all to abbreviate " WFTA processor " as among Fig. 1.WFTA is made up of three parts, is respectively: the preceding addition module that interweaves, multiplier module and after the addition module that interweaves.When the WFTA processor is realized, at first carry out all additive operations that interweaves, carry out all multiplyings then, carry out the additive operation that interweaves after all at last.Adopt WFTA a plurality of small point DFT processors can be nested together, thereby reduce required multiplying.

Set x:=[x (0), x (1) ..., x (N-1)] ^TAnd X:=[X (0), X (1) ..., X (N-1)] ^TBe respectively the N dimension input column vector and the N dimension output column vector of N point DFT processor, wherein superscript T represents transposition.Definition W _M=exp (j2 π/M), the transformation matrix of M point DF.T processor is expressed as follows:

$W_M=\left[\begin{array}{cccc}{W}_M^0& {\mathrm{<figure-callout\; id="0"\; label="W\; M"\; filenames="C2007101598220018H1.png,C2007101598220019H2.png"\; state="\{\{state\}\}">W</figure-callout>}}_M^{}& ...& W_M^0\\ W_M^0& {\mathrm{<figure-callout\; id="1"\; label="W\; M"\; filenames="C2007101598220015H2.png,C2007101598220018H1.png"\; state="\{\{state\}\}">W</figure-callout>}}_M^{}& ...& W_M^{M-1}\\ .& .& & .\\ .& .& ...& .\\ .& .& & .\\ W_M^0& W_M^{M-1}& ...& W_M^{(M-1)(M-1)}\end{array}\right]$

For 5 DFT processors (N=5), the mathematic(al) representation of WFTA is:

X＝W _Nx＝CBAx (1)

Wherein $A=\left[\begin{array}{ccccc}1& 1& 1& 1& 1\\ 0& 1& 1& 1& 1\\ 0& 1& -1& 1& -1\\ 0& 1& 0& -1& 0\\ 0& 0& 1& 0& -1\\ 0& 1& 1& -1& -1\end{array}\right],$ Be used for input signal is carried out additive operation (addition module interweaves before the correspondence); B is a diagonal matrix, and corresponding to the multiplying module, the element on this diagonal matrix is [1, (0.5 cos (2 θ)+cos (θ))-1,0.5 (cos (2 θ)-cos (θ)), sin (2 θ)-sin (θ), sin (2 θ)-sin (θ), sin (θ)], θ=2 π/5 here; $C=\left[\begin{array}{cccccc}1& 0& 0& 0& 0& 0\\ 1& 1& -1& 0& -j& -\mathrm{<figure-callout\; id="1"\; label="j"\; filenames="C2007101598220015H2.png,C2007101598220018H1.png"\; state="\{\{state\}\}">j</figure-callout>}\\ 1& 1& 1& -j& 0& -\mathrm{<figure-callout\; id="1"\; label="j"\; filenames="C2007101598220015H2.png,C2007101598220018H1.png"\; state="\{\{state\}\}">j</figure-callout>}\\ 1& 1& -1& 0& \mathrm{<figure-callout\; id="1"\; label="j\; j"\; filenames="C2007101598220015H2.png,C2007101598220018H1.png"\; state="\{\{state\}\}">j</figure-callout>}& j\\ 1& 1& 1& j& 0& j\end{array}\right],$ Corresponding to after the additive operation module that interweaves.Natch, the above-mentioned DFT processor that also can be extended to other odd prime number points at the WFTA of 5 DFT processors.

The implementation of 3780 DFT processors that Fig. 1 describes has some advantages, and for example: utilize PFA that dimension DFT is converted into multidimensional DFT, the conversion of each dimension is independent of each other independently of one another; This DFT processor does not adopt fast fourier transform (the fast Fourier transforms of based structures (as base 3, base 2 etc.), FFT), that adopt is the high efficiency WFTA of small point, so in the conversion process of different dimensional, do not relate to the problem that multiplies each other with twiddle factor, thereby reduced operand.And the cost of for this reason paying is higher hardware realization inconsistency.When 3780 DFT processors shown in Figure 1 being carried out the hardware realization, 3780 processing procedures need be decomposed into 5 different submodules (9 points, 7 points, 5 points, and 3 points) at 4 and carry out, and these 5 submodules realize that circuit are diverse.Therefore, realizing validity with regard to hardware, though this mode is feasible, is not optimized method.In addition, 3780 DFT processors of above-mentioned document [2] description reckon without the diversity of input signal types.Such as, receiving end in the digital tv ground broadcasting that China announces, the input vector of 3780 DFT processors comprises that not only length is 3780 OFDM data vector, also can comprise channel impulse response (channel impulse response, CIR) vector.Each element of data vector is any value in a certain scope, is zero but the CIR vector has many elements.In this case, can simplify input vector is that the DFT processing procedure of CIR vector is to reach the purpose of saving system power dissipation.But 3780 DFT processors that disclose in the existing document reckon without the characteristic of CIR input vector.Therefore, need provide a kind of 3780 new DFT processors, to take into full account the diversity of required information converting type.

Summary of the invention

In view of this, the technical problem to be solved in the present invention provides a kind of sharp leaf transformation processor of 3780 point discrete Fouriers that can reduce operand and save power consumption.

For solving the problems of the technologies described above, the invention provides the sharp leaf transformation processor of a kind of 3780 new point discrete Fouriers.The sharp leaf transformation processor of this 3780 point discrete Fourier has one of following two kinds of structures, first kind of structure comprises 140 27 sharp leaf transformation processors of point discrete Fourier, complex multiplier, subscript mapping processor, 27 sharp leaf transformation processors of 140 point discrete Fouriers successively, the parallel setting of the sharp leaf transformation processor of described 140 27 point discrete Fouriers also is connected with described complex multiplier respectively, described complex multiplier is connected with described subscript mapping processor, and the parallel setting of the sharp leaf transformation processor of described 27 140 point discrete Fouriers also is connected with described subscript mapping processor respectively; Second kind of structure comprises 27 140 sharp leaf transformation processors of point discrete Fourier, complex multiplier, subscript mapping processor, 140 sharp leaf transformation processors of 27 point discrete Fouriers successively, the parallel setting of the sharp leaf transformation processor of described 27 140 point discrete Fouriers also is connected with described complex multiplier respectively, described complex multiplier is connected with described subscript mapping processor, and the parallel setting of the sharp leaf transformation processor of described 140 27 point discrete Fouriers also is connected with described subscript mapping processor respectively.

For the input information that comprises channel impulse response (CIR) vector, the sharp leaf transformation processor structure of this 3780 point discrete Fourier is first kind of structure, it comprises that also algorithm process is pruned in utilization to 140 the 27 sharp leaf transformation processors of point discrete Fourier, prune by pruning the algorithm pair computing relevant, remove redundant operation with the neutral element in the CIR vector.

Compare prior art, the sharp leaf transformation processor of 3780 point discrete Fouriers provided by the invention is realized by the sharp leaf transformation processor of 140 27 point discrete Fouriers of cascade and 27 the 140 sharp leaf transformation processors of point discrete Fourier, effectively reduce the multiply operation quantity in the implementation procedure, effectively lowered the power consumption of system; According to the inherent characteristic of CIR vector,, further reduced multiplication and the amount of addition operations of processor by pruning algorithm.

Description of drawings

Fig. 1 is the structured flowchart of existing 3780 DFT processors.

Fig. 2 is that the digital tv ground broadcasting receiving end relates to the process flow diagram that 3780 DFT handle.

Fig. 3 is the structured flowchart of 3780 DFT processors of the present invention embodiment 1.

Fig. 4 is the structured flowchart of 3780 DFT processors of the present invention embodiment 2.

Fig. 5 a is the structured flowchart of basic 3-27 point fft processor.

Fig. 5 b is base 3 butterfly diagrams that are used for two inputs, three outputs of basic 3-27 point fft processor.

Fig. 6 is the structured flowchart of 140 WFTA processors.

Fig. 7 is the concrete operations synoptic diagram of 3780 DFT processors shown in Figure 3.

Fig. 8 is the concrete operations synoptic diagram of 3780 DFT processors shown in Figure 4.

Fig. 9 is that basic 3-27 point fft processor shown in Fig. 5 a is by the structured flowchart after pruning.

Embodiment

Embodiment to 3780 DFT processors provided by the invention is described below in conjunction with accompanying drawing, in the hope of further understanding purpose of the present invention, specific structural features and advantage.

Before describing 3780 DFT processors provided by the invention, at first the required condition that possesses of employed 3780 DFT processors in the digital tv ground broadcasting standard of China's announcement is explained.Fig. 2 uses 3780 process flow diagrams that the DFT processor is handled input signal for described system receiving terminal, and wherein input signal is made up of a series of continuous signal frame.Each signal frame has the signal sampling point of fixed number and is made up of two parts.The first of signal frame is a frame synchronization, it by be used to carry out receiver synchronously and the pseudo noise of channel estimating (pseudo noise, PN) sequence cyclic-extension forms; The second portion of signal frame is a frame, and it is that 3780 data vector constitutes by length.After receiving k signal frame, utilize the PN sequence in the frame synchronization to calculate the CIR vector that obtains the respective signal frame: h _k=[h _k(0), h _k(1) ..., h _k(N-1)] ^TSet x _k=[x _k(0), x _k(1) ..., x _k(N-1)] ^TData vector (i.e. the frame of k signal frame) for k signal frame receiving.In 3780 DFT processors of described data vector and CIR vector input correspondence, processing procedure is as follows:

X _k＝DFT(x _k)＝W _Nx _k (2)

H _k＝DFT(h _k)＝W _Nh _k (3)

X wherein _k=[X _k(0), X _k(1) ..., X _k(N-1)] ^T, H _k=[H _k(0), H _k(1) ..., H _k(N-1)] ^TSignal after the conversion inputs in the frequency domain equalizer 1, carries out isostatic compensation to received signal, the signal Y after the output compensation _k=[Y _k(0), Y _k(1) ..., Y _k(N-1)] ^T, wherein:

$Y_k\left(n\right)=\frac{X_k\left(n\right)}{H_k\left(n\right)},n=\mathrm{0,1},...,N-1---\left(4\right)$

Set N _sFor the maximum multipath under the multidiameter fading channel environment postpones diffusion, it is with the signal sampling unit of being spaced apart.In the receiving end of the digital tv ground broadcasting standard that China announces, N _sSize is limited by the PN sequence length in each signal frame.From document [1] as can be known, General N _s＜512.Set two positive integers: L _pAnd L _n, and satisfy following condition: L _p+ L _n≤ N _s, in conjunction with document [4]: the content that discloses in " No. the 200410003480.3rd, Chinese patent application, open day is on October 5th, 2005 " as can be known, CIR vector h _kHave following two characteristic A and B:

Characteristic A:h _kMiddle h _k(L _p) to h _k(N-L _n-1) be zero, that is to say, for m=0,1 ..., N-L _p-L _n-1, h _k(L _p+ m)=0.

Characteristic B:[h _k(0), h _k(1) ..., h _k(L _p-1)] and [h _k(N-L _n), h _k(N-L _n+ 1) ..., h _k(N-1)] major part in also is a neutral element.

The CIR vector is one of them the input vector of two 3780 DFT processors of system receiving terminal, because the CIR vector has above-mentioned characteristic A and B, so the present invention is directed to the above-mentioned inherent feature of CIR vector a kind of 3780 new DFT processors have been proposed, can effectively reduce the operand in the implementation procedure, reduce system power dissipation, specifically describe as after chat pattern I, II.

Different with 60 * 63 (perhaps 63 * 60) is olation of mentioning in the document [2] is that 3780 DFT processors provided by the invention are with composite number 3780 factorizes 27 and 140.3780 DFT processors 2124,2421 of the present invention are realized by 140 27 DFT processors 21 (representing 140 27 parallel DFT processors) and 27 140 DFT processors 24 (representing 27 140 parallel DFT processors) of cascade.Different with the precedence of 27 140 DFT processors 24 according to 140 27 DFT processors 21,3780 DFT processors provided by the invention have Fig. 3 and two kinds of embodiment shown in Figure 4.27 DFT processor adopting that relate among the present invention basic 3-fast fourier transform (fast Fourier transform, FFT) algorithm is so all be called in the drawings with in the subsequent descriptions: basic 3-27 point fft processor.140 DFT processor adopting WFTA that the present invention relates to realize, thus in the drawings be called " WFTA processor " in the subsequent descriptions.See also Fig. 3,3780 DFT processors 2124 in the example 1 comprise 140 basic 3-27 point fft processors 21, complex multiplier 22,23,27 140 WFTA processors 24 of subscript mapping processor successively.See also Fig. 4,3780 DFT processors 2421 in the example 2 comprise 27 140 WFTA processors 24, complex multiplier 22,23,140 basic 3-27 point fft processors 21 of subscript mapping processor successively.

Need to prove, 27 DFT processors that the present invention relates to can adopt any type of basic 3-FFT algorithm, but what adopt in the embodiment of the invention is document [5]: " Y.Suzuki, T.Sone, and K.Kido; " A new FFT algorithm of radix 3,6, and 12, " IEEE Trans.Acoust.; Speech; SignalProcessing, vol.ASSP-34, no.2; pp.380-383; April 1986. " the basic 3-FFT algorithm mentioned, shown in Fig. 5 a, this is in routine (1 because of this base 3-FFT algorithm, j) carry out on the complex plane, and required addition and multiply operation are lacked than other forms of algorithm.Suppose that input vector is x, output vector is X, and the mathematic(al) representation of basic 3-N point fft algorithm is:

$X\left(l\right)=\underset{n=0}{\overset{N-1}{\mathrm{\&Sigma;}}}x\left(n\right)W^{-\mathrm{nl}}=\underset{n=0}{\overset{N/3-1}{\mathrm{\&Sigma;}}}x\left(3n\right)W^{-3\mathrm{nl}}+\left(\underset{n=0}{\overset{N/3-1}{\mathrm{\&Sigma;}}}x(3n+1)W^{-3\mathrm{nl}}\right)W^{-l}+\left(\underset{n=0}{\overset{N/3-1}{\mathrm{\&Sigma;}}}x(3n+2)W^{-3(n+1)l}\right)W^l---\left(5\right)$

Wherein W=exp (j2 π/N), l=0,1 ..., N-1.Definition $A\left(l\right)=\underset{n=0}{\overset{N/3-1}{\mathrm{\&Sigma;}}}x\left(3n\right)W^{-3\mathrm{nl}},$ $B\left(l\right)=\underset{n=0}{\overset{N/3-1}{\mathrm{\&Sigma;}}}x(3n+1)W^{-3\mathrm{nl}},$ $C\left(l\right)=x(N-1)+\underset{n=1}{\overset{N/3-1}{\mathrm{\&Sigma;}}}x(3n-1)W^{-3\mathrm{nl}},$ Formula (5) can be expressed as:

X(m)＝A(m)+B(m)W ^m+C(m)W ^m (6)

X(m+N/3)＝A(m)+B(m)W ^mμ ^*+C(m)W ^mμ (7)

X(m+2N/3)＝A(m)+B(m)W ^mμ+C(m)W ^mμ ^* (8)

Wherein superscript * represents complex conjugate, $\mathrm{\&mu;}=-\frac{1}{2}+\frac{\sqrt{3}}{2}j,$ m＝0，1，...，N/3-1。According to above-mentioned algorithm, each value of corresponding m all forms two inputs and three base 3 butterfly diagrams of exporting shown in Fig. 5 b.Hence one can see that, and for the N point DFT processor that adopts basic 3-FFT algorithm, real multiplications operation and real number add operation that implementation procedure needs are respectively:

Thus, for basic 3-27 point fft processor (N=27), implementation procedure then needs 164 real multiplications operations and 380 real number add operations.

That 140 DFT processor adopting is WFTA in the embodiment of the invention.As previously mentioned, a N point DFT processor can be counted the DFT processor by the several dots of cascade and realize, in fact, N point DFT can be counted Kronecker that long-pending (Kronecker product) expression of DFT by several dots, for example: if N has factor N ₁, N ₂And N ₃, the matrix W of N point DFT _NCan be decomposed into:

$W_N={\mathrm{<figure-callout\; id="1"\; label="W\; N"\; filenames="C2007101598220015H2.png,C2007101598220018H1.png"\; state="\{\{state\}\}">W</figure-callout>}}_{N_{}}\&CircleTimes;{\mathrm{<figure-callout\; id="2"\; label="W\; N"\; filenames="C2007101598220018H1.png,C2007101598220019H2.png"\; state="\{\{state\}\}">W</figure-callout>}}_{N_{}}\&CircleTimes;W_{N_3}---\left(9\right)$

Wherein Be respectively N ₁, N ₂, N ₃Point DFT matrix,

Expression Kronecker that integrating.Shown in the formula (1), small point DFT can be decomposed into CBA as described above, and the matrix representation of three small point DFT processors after the decomposition is as follows:

${\mathrm{<figure-callout\; id="1"\; label="W\; N"\; filenames="C2007101598220015H2.png,C2007101598220018H1.png"\; state="\{\{state\}\}">W</figure-callout>}}_{N_{}}=C_1{B}_1{A}_1$ ${\mathrm{<figure-callout\; id="2"\; label="W\; N"\; filenames="C2007101598220018H1.png,C2007101598220019H2.png"\; state="\{\{state\}\}">W</figure-callout>}}_{N_{}}=C_2{B}_2{A}_2$ ${\mathrm{<figure-callout\; id="3"\; label="W\; N"\; filenames="C2007101598220018H1.png,C2007101598220021H1.png"\; state="\{\{state\}\}">W</figure-callout>}}_{N_{}}=C_3{B}_3{A}_3---\left(10\right)$

With formula (10) substitution formula (9), N point DFT matrix W _NCan be expressed as:

$W_N=\left(C_1{B}_1{A}_1\right)\&CircleTimes;\left(C_2{B}_2{A}_2\right)\&CircleTimes;\left(C_3{B}_3{A}_3\right)$

$=({\mathrm{<figure-callout\; id="1"\; label="C"\; filenames="C2007101598220015H2.png,C2007101598220018H1.png"\; state="\{\{state\}\}">C</figure-callout>}}_1\&CircleTimes;{\mathrm{<figure-callout\; id="2"\; label="C"\; filenames="C2007101598220018H1.png,C2007101598220019H2.png"\; state="\{\{state\}\}">C</figure-callout>}}_2\&CircleTimes;C_3)({\mathrm{<figure-callout\; id="1"\; label="B"\; filenames="C2007101598220015H2.png,C2007101598220018H1.png"\; state="\{\{state\}\}">B</figure-callout>}}_1\&CircleTimes;{\mathrm{<figure-callout\; id="2"\; label="B"\; filenames="C2007101598220018H1.png,C2007101598220019H2.png"\; state="\{\{state\}\}">B</figure-callout>}}_2\&CircleTimes;B_3)(A_1\&CircleTimes;A_2\&CircleTimes;A_3)---\left(11\right)$

Observe formula (10) and (11) as can be known, the algorithm of the DFT processor of counting greatly has identical form promptly with the algorithm of small point DFT processor: $X=\mathrm{CBAx}(A=A_1\&CircleTimes;A_2\&CircleTimes;A_3,B=B_1\&CircleTimes;B_2\&CircleTimes;B_3,C=$ $C_1\&CircleTimes;C_2\&CircleTimes;C_3);$ That is to say, adopt nested mode, the inside of can the multiply operation that processor is all incorporating algorithm into.The described processing procedure of incorporating into: at first carry out the additive operation that interweaves before all modules of processor, carry out multiply operation then, additive operation interweaves after carrying out at last.With 140 WFTA processors (N=140) is example, consults Fig. 6, N=140, and it has factor: N ₁=4, N ₂=5, N ₃=7.The adder unit 33 that interweaves behind adder unit 31, multiplication unit 32 and one interweaves before these 140 WFTA processors comprise one.The adder unit 31 that wherein before interweaves only carry out 7 and 5 DFT processors before the additive operation that interweaves; The adder unit 33 that then interweaves carry out 5 points, 7 and 4 DFT processors after the additive operation that interweaves.The multiply operation of supposing plural number need realize by 3 real multiplications operations and 3 real number add operations, operation of the real multiplications of 140 WFTA processors and real number add operation are respectively 424 and 3224 so, as document [6]: " C.S.Burrus; " Efficient Fourier transform and convolution algorithms; " in Advanced Topics in Signal Processing, J.S.Lim and A.V.Oppenheim, Eds., Prentice Hall, Englewood Cliffs, NJ, 1988. " shown in.

Based on N=RQ, the N point DFT that is realized by Q R point DFT and R Q point DFT cascade can be expressed as on mathematics:

$X(m_{1}R+m_2)=\underset{{\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="C2007101598220015H2.png,C2007101598220018H1.png"\; state="\{\{state\}\}">n</figure-callout>}}_1=0}{\overset{Q-1}{\mathrm{\&Sigma;}}}\left[\left(\underset{{\mathrm{<figure-callout\; id="2"\; label="n"\; filenames="C2007101598220018H1.png,C2007101598220019H2.png"\; state="\{\{state\}\}">n</figure-callout>}}_2=0}{\overset{R-1}{\mathrm{\&Sigma;}}}x({\mathrm{<figure-callout\; id="1"\; label="n"\; filenames="C2007101598220015H2.png,C2007101598220018H1.png"\; state="\{\{state\}\}">n</figure-callout>}}_1+Q{n}_2)W_R^{m_2{n}_2}\right)W_N^{m_2{n}_1}\right]W_Q^{m_1{n}_1}---\left(12\right)$

Here,

Expression R point DFT;

Expression twiddle factor complex multiplier (twiddle multiplication device);

Expression Q point DFT processor; M wherein ₁=0,1 ..., Q-1, m ₂=0,1 ..., R-1.

Analyze formula (12) as can be known, the twiddle multiplication device of N point DFT processor is used for the output signal of R point DFT processor is rotated operation.The specific implementation process of 3780 DFT processor two embodiment provided by the invention as shown in Figure 7 and Figure 8.The corresponding embodiment of the invention 1 of Fig. 7 (R=27, Q=140); The corresponding embodiments of the invention 2 of Fig. 8 (Q=27, R=140).Remove negligible multiply operation and (as multiply by 1 or-1, amount to 175), suppose that 3 real multiplications operations of each complex multiplication action need and 3 real number add operations realize that the twiddle multiplication device of 3780 DFT processors of the present invention needs 10815 real multiplications/add operations to realize (seeing Table 1).

Table 13780 a DFT processor action required operand

As shown in table 1, the realization of 3780 DFT processors of the present invention need amount to 45223 real multiplications operations and 151063 real number add operations, compares with the data that document [3] is announced, has saved the operation of 11% real multiplications, has increased by 8% real number add operation.Because multiply operation is than the hardware implementation complexity height of add operation, power consumption is also big, is easier to the hardware realization so 3780 DFT processors that the present invention proposes are compared prior art.

Further, if the input vector of 3780 DFT processors that the present invention proposes is CIR vector h _k, advantage so of the present invention will be more obvious, below further analyze description at implementation pattern I, the II of two kinds of embodiment of 3780 DFT processors of corresponding the present invention.

Pattern I:R=27, Q=140

In pattern I, carry out 140 all 27 basic 3-FFT processors earlier.The front is to CIR vector h _kInherent characteristic A, B introduce, according to characteristic A as can be known, CIR vector h _kIn have only preceding L _pWith back L _nIndividual element is a nonzero element, and other all are neutral elements.As previously mentioned, L _p+ L _n≤ N _s＜512, and h _kThe first element h _k(0) corresponding with the main channel path, therefore, in actual applications can be in conjunction with reasonable assumption L _p≤ 420 and L _n≤ 140.This shows that the CIR vector has a lot of neutral elements.In this case, the many operations in the basic 3-27 point fft processor are redundant, and the operation of these redundancies can be easy to adopt pruning algorithm (pruning algorithms) to remove.

In conjunction with formula (12), specifically, the corresponding n of preceding 420 elements of CIR input vector ₂=0,1,2 and n ₁=0,1 ..., 139, the corresponding n of last 140 elements ₂=26, n ₁=0,1 ...., 139.As can be seen from Figure 7, in 140 the input vector of each 27 point processor to have only preceding 3 elements and last element be nonzero element.In view of this, after algorithm was pruned in employing, Fig. 5 can be represented that the implementation procedure of basic 3-27 point fft processor shown in Figure 9 only needs 88 real multiplications operations and 164 real number add operations by the Fig. 9 after pruning.

Select a step ground, according to the characteristic B of CIR vector, 4 input data shown in Figure 9 also may be neutral element, and therefore, implementation procedure shown in Figure 9 can also further be pruned.Under extreme case, that is: 4 input data all are neutral elements, and so described basic 3-27 point fft processor will stop its all operations, and the rotary manipulation of the device of twiddle multiplication as shown in Figure 7 subsequently also becomes unnecessary.

Inherent characteristic according to the CIR input vector adopts the concrete diminishbb operation amount of pruning algorithm to be decided by its residing channel condition.In digital tv ground broadcasting, can suppose reliably that maximum 30 are are effectively received and dispatched the path, that is to say, the input information of 3780 DFT processors has 30 nonzero elements at most, the result is that to have the operation of 110 basic 3-27 point fft processors at least in 140 basic 3-27 point fft processors shown in Figure 7 be redundant, can wholely be removed.

Below be in a conservative estimation of being done aspect the saving operation amount to processor of the present invention.Suppose and have only 15 27 fft processors to have the non-zero input vector, and each 27 fft processor has 2 non-zero input values.Further the operation carried out of each 27 DFT processor of supposition is half of pruning preprocessor shown in Figure 9, and this is because if the non-zero input value changes to 4 from 2, can further adopt to prune algorithm and simplify the operation.Under above-mentioned assumed conditions, 3780 DFT processors of the present invention embodiment 1 needs 13267 real multiplications operations and 89437 real number add operations altogether, and is as shown in table 2.That is to say,,, can save 71% real multiplications operation and 41% add operation by adopt pruning algorithm if input signal is the CIR vector.

Table 2 part is input as 3780 DFT processor action required numbers of nonzero element

Pattern II:R=140, Q=27

Under pattern II, at first carry out 140 WFTA processors.As can be seen from Figure 6, the phase one of 140 WFTA processor execution is the additive operations that interweave before carrying out, and this is handled and adopts irregular structure, so generally can not adopt the pruning algorithm.Certainly, the those of ordinary skill of industry can adopt other can reduce the method for operation amount as everyone knows, as document [7]: the conversion decomposition method that disclose " March 1993. for H.V.Sorensen and C.S.Burrus; " Efficientcomputation of the DFT with only a subset of input or output points " IEEE Trans.Signal Processing.; vol.41; no.3, pp.1184-1200 ".

Being understandable that foregoing description only is the specific descriptions to the specific embodiment of the invention, is not to any qualification of the present invention.To those skilled in the art, can be equal to replacement or change according to technical scheme of the present invention and inventive concept thereof, and all these changes or replacement all should belong to the protection domain of appending claims of the present invention.

Claims (8)

1. the sharp leaf transformation processor of a point discrete Fourier, it is characterized in that, the sharp leaf transformation processor of this 3780 point discrete Fourier has one of following two kinds of structures, first kind of structure comprises 140 the 27 sharp leaf transformation processors of point discrete Fourier successively, complex multiplier, the subscript mapping processor, 27 the 140 sharp leaf transformation processors of point discrete Fourier, the parallel setting of the sharp leaf transformation processor of described 140 27 point discrete Fouriers also is connected with described complex multiplier respectively, described complex multiplier is connected with described subscript mapping processor, and the parallel setting of the sharp leaf transformation processor of described 27 140 point discrete Fouriers also is connected with described subscript mapping processor respectively; Second structure comprises the sharp leaf transformation processor of 27 140 point discrete Fouriers, complex multiplier, subscript mapping processor, 140 sharp leaf transformation processors of 27 point discrete Fouriers successively, the parallel setting of the sharp leaf transformation processor of described 27 140 point discrete Fouriers also is connected with described complex multiplier respectively, described complex multiplier is connected with described subscript mapping processor, and the parallel setting of the sharp leaf transformation processor of described 140 27 point discrete Fouriers also is connected with described subscript mapping processor respectively.

2. the sharp leaf transformation processor of 3780 point discrete Fouriers as claimed in claim 1 is characterized in that: the sharp leaf transformation processor of described each 27 point discrete Fourier is the basic 3-27 point fft processor that adopts basic 3-fast fourier transform algorithm (FFT).

3. the sharp leaf transformation processor of 3780 point discrete Fouriers as claimed in claim 2 is characterized in that: what described basic 3-27 point fft processor adopted is the butterfly computation of two inputs, three outputs.

4. the sharp leaf transformation processor of 3780 point discrete Fouriers as claimed in claim 1 is characterized in that: the sharp leaf transformation processor of described 140 point discrete Fouriers is 140 WFTA processors that adopt Wei Nuogela Fourier Tranform algorithm (WFTA).

5. the sharp leaf transformation processor of 3780 point discrete Fouriers as claimed in claim 4, it is characterized in that: described 140 WFTA processors are decomposed into 4 points, 5 points, 7 WFTA processors.

6. the sharp leaf transformation processor of 3780 point discrete Fouriers as claimed in claim 5, it is characterized in that: the adder unit that interweaves before described 140 WFTA processors comprise, multiplication unit and after the adder unit that interweaves, the adder unit that wherein before interweaves carry out 7 and 5 WFTA processors before the additive operation that interweaves, the adder unit that then interweaves carry out 4 points, 5 points, 7 WFTA processors after the additive operation that interweaves.

7. the sharp leaf transformation processor of 3780 point discrete Fouriers as claimed in claim 1, it is characterized in that: described complex multiplier is the twiddle multiplication device that comprises twiddle factor, and it is used for the output signal of 140 27 sharp leaf transformation processors of point discrete Fourier or 27 the 140 sharp leaf transformation processors of point discrete Fourier is rotated operation.

8. the sharp leaf transformation processor of 3780 point discrete Fouriers as claimed in claim 1, it is characterized in that: the sharp leaf transformation processor structure of this 3780 point discrete Fourier is first kind of structure, for the input information that comprises the channel impulse response vector, the sharp leaf transformation processor of this 3780 point discrete Fourier also comprises to be handled 140 the 27 sharp leaf transformation processor of point discrete Fourier utilization pruning algorithms.

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