KR101554667B1 - Fast fourier transform processor - Google Patents

Fast fourier transform processor Download PDF

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KR101554667B1
KR101554667B1 KR1020150056735A KR20150056735A KR101554667B1 KR 101554667 B1 KR101554667 B1 KR 101554667B1 KR 1020150056735 A KR1020150056735 A KR 1020150056735A KR 20150056735 A KR20150056735 A KR 20150056735A KR 101554667 B1 KR101554667 B1 KR 101554667B1
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radix
processing unit
output
butterfly
complex multipliers
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KR1020150056735A
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Korean (ko)
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선우명훈
신성경
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아주대학교산학협력단
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/26—Systems using multi-frequency codes
    • H04L27/2601—Multicarrier modulation systems
    • H04L27/2626—Arrangements specific to the transmitter only
    • H04L27/2627—Modulators
    • H04L27/2634—Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation
    • H04L27/2636—Inverse fast Fourier transform [IFFT] or inverse discrete Fourier transform [IDFT] modulators in combination with other circuits for modulation with FFT or DFT modulators, e.g. standard single-carrier frequency-division multiple access [SC-FDMA] transmitter or DFT spread orthogonal frequency division multiplexing [DFT-SOFDM]

Abstract

Disclosed is a fast Fourier transform processor using multi-stage processors composed of multiple butterflies, multiple delay units, multiple commutators, multiple constant complex multipliers and multiple complex multipliers. The fast Fourier transform processor according to an embodiment of the present invention comprises: a first-stage processor including a first butterfly of a radix-m having m input terminals (m is an even number) and multiple constant complex multipliers connected to some of output terminals of the first butterfly, wherein the odd-numbered output terminals are connected via a first path and the even-numbered output terminals are connected via a second path; and a second-stage processor including a second butterfly of a radix-m/2 located in the first path, multiple constant complex multipliers located in the first path, a third butterfly of a radix-m/2 located in the second path and multiple complex multipliers located in the second path.

Description

[0001] FAST FOURIER TRANSFORM PROCESSOR [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fast Fourier transform apparatus, and more particularly, to a fast Fourier transform (FFT) processor supporting multipoint for a MIMO-OFDM (Multiple-Input Multiple-Output Orthogonal Frequency Division Multiplexing) system.

The Orthogonal Frequency Division Multiplexing (OFDM) transmission scheme has a strong advantage in a multi-path fading channel environment in a manner suitable for high-speed data transmission in a wireless channel. Therefore, in IEEE 802.11n, WLAN, IEEE 802.16e mobile WiMax, 4G system, etc., OFDM system is used for high-speed data transmission in multipath channel. The OFDM system is implemented using a Discrete Fourier Transform (DFT), and a Fast Fourier Transform Processor (hereinafter, referred to as an FFT processor) is used to reduce the amount of computation in hardware design. However, since the FFT processor is the most complicated module in the OFDM system, it is required to design an optimized FFT processor for a low area implementation.

Meanwhile, as the demand for high-speed data transmission increases, a multiple-input multiple-output (MIMO) system using multiple antennas at the transmitting and receiving end has been actively studied. MIMO systems are attracting attention as a solution to frequency resource limitation as a technology that can increase the communication capacity while using the same bandwidth.

Therefore, MIMO-OFDM technology combining MIMO and OFDM is attracting attention as a key technology for high-speed data transmission. However, such a MIMO-OFDM system has a problem of complicating the hardware because it has a plurality of data paths. In particular, the MIMO-OFDM system implements the FFT processor in parallel with the number of data paths. Since the FFT processor is one of the most complex blocks of the hardware implementing the MIMO-OFDM system, The number of data passes is increased in proportion to the number of data passes.

Therefore, in order to solve such a problem that the MIMO-OFDM system becomes complicated by implementing the FFT processor in parallel by the number of data passes, it is necessary to use a single FFT processor having a multi-path delay commutator (MDC) A method of reducing the complexity by simultaneously processing passes is proposed. In the case of a MIMO-OFDM system in which k data streams are input, utilizing a raidx-k MDC (RkMDC) structure rather than implementing k raidx-2 SDF (R2SDF) Efficient. In addition, mixed-radix MDC (MRMDC) structure has been confirmed to be more efficient in terms of area utilization by further reducing the number of non-simple multiply operations than RkMDC structure using only raidx-k.

Recently, a hardware optimization study using MRMDC structure is being carried out, and a hardware optimization study using a radix-8, a radix-8, and a radix-2 algorithm has been carried out to support 64-point and 128- An FFT processor architecture is being used in 8-channel MIMO-OFDM systems.

However, the recently ratified 5G WiFi standard requires a 64-point and 128-point FFT operation as well as a 256-point FFT operation based on an 8-channel MIMO-OFDM system.

As a related art, there is Korean Patent Registration No. 10-1332850 entitled " Fast Fourier Transform Device and Method for MIMO Multiplexing / Multiplexing System, Date: Nov. 19, 2013).

An object of the present invention is to provide a fast Fourier transform apparatus having low complexity and low area.

According to an aspect of the present invention, there is provided a fast Fourier transform apparatus using a multi-stage processing unit including a plurality of butterflies, a plurality of delay units, a plurality of commutators, a plurality of constant complex multipliers, and a plurality of complex multipliers, (Radix-m, m is an even number) with m input stages and a plurality of constant complex multipliers connected to a part of the output ends of the first butterfly, A first end processing unit connected to the first path and connected to the even-numbered output end through a second path; And a plurality of constant complex multipliers located in the first pass, a third butterfly having a radix-m / 2 located in the second pass, And a second termination section including a plurality of complex multipliers located in the second path.

Preferably, the fast Fourier transform apparatus according to the embodiment of the present invention is constituted by a multi-stage intermediate processing section including a plurality of fourth butterflies with a radix-m / 4, A selection processing unit for selecting an intermediate processing unit to which the output of the second termination unit passes; And a plurality of constant complex multipliers selectively connected to a plurality of input ends of each of the plurality of fifth butterflys, respectively, and a third end processing section including a plurality of fifth butterflies having a base-m / 4 and a plurality of constant complex multipliers And the constant complex multiplier selectively connected to a plurality of input ends of the plurality of fifth butterfly outputs a signal that does not need to be multiplied by a twiddle factor or an input terminal to which a signal multiplied by a twiddle factor 1 is inputted, Can be connected to an input terminal.

Preferably, the selection processing unit may comprise two stages of intermediate processing units including four fourth butterflies of the odd number-2.

Preferably, the intermediate processing unit is connected to each of the two output terminals of each of the four fourth butterflies, and outputs eight muxes for selecting one of signals of the input terminal of the intermediate processing unit and one of the signals of the butterfly output terminal .

Preferably, the intermediate processing unit includes four commutators connected to each of the four fourth butterflies; And eight delays selectively connected to one of the two inputs and the two outputs of each of the four commutators.

Preferably, the selection processing unit may forward the output of the second end processing unit to the third end processing unit without going through the intermediate processing unit when the FFT unit performs 64-point calculation.

Preferably, when the FFT unit performs the 128-point operation, the selection processing unit may pass the output of the second end processing unit to one end of the intermediate processing unit and then forward the output to the third end processing unit have.

Preferably, in the case where the FFT unit performs the 256-point operation, the selection processing unit may pass the output of the second end processing unit to all of the two stages of the intermediate processing unit and then transmit the output to the third end processing unit have.

Advantageously, said third end processing portion comprises four fifth butterflies of an odd number-2; Four constant complex multipliers coupled to one of the plurality of inputs of each of the four fifth butterflies; And four muxes connected to an output terminal of each of the four constant complex multipliers to select and output one of a signal at an input terminal and a signal at an output terminal of the corresponding complex multiplier.

Preferably, the third end processing section includes four commutators connected to each of the four fifth butterflies; And eight delays selectively connected to one of the two inputs and the two outputs of each of the four commutators.

Advantageously, said first end treatment comprises a first butterfly having a radix of -8; And seven constant complex multipliers coupled to the output of the first butterfly.

Advantageously, a plurality of constant complex multipliers located in said first pass compute a 128-point twiddle factor, and a plurality of complex multipliers located in said second pass may compute a 256-point twiddle factor .

Advantageously, said second end processing portion is a second butterfly having a radix-4 located in said first pass; Four constant complex multipliers located in the first pass and coupled to the second butterfly output stage; A third butterfly having a radix-4 located in the second pass; And four complex multipliers located in the second pass and coupled to the third butterfly output stage.

Advantageously, the second termination section comprises: a plurality of first delay elements located in the first pass and coupled to the second butterfly input; A first commutator located at the first path and coupled to the inputs of the plurality of first delay units; A plurality of second delays located in the first pass and coupled to an input of the first commutator; A plurality of third delays located in the second pass and coupled to the third butterfly input; A second commutator located at the second pass and coupled to the inputs of the plurality of third delay units; And a plurality of fourth delay elements located in the second path and connected to the input terminal of the second commutator.

According to an embodiment of the present invention, hardware complexity of a fast Fourier transform apparatus can be reduced, and a fast Fourier transform apparatus can be implemented with a small area.

According to another embodiment of the present invention, there is an advantage in that various point operations can be selectively performed using one FFT apparatus by selectively passing the multi-stage butterflies.

1 is a schematic block diagram of a fast Fourier transform apparatus according to an embodiment of the present invention.
FIG. 2A is a diagram illustrating a connection structure between a Radix-8 processor and a Radix-4 processor according to an embodiment of the present invention.
FIG. 2B is a diagram illustrating a connection structure between a conventional Radix-8 processor and a Radix-4 processor.
FIG. 3A is a diagram illustrating an exponent value of a twiddle factor applied in a Radix-4 processor according to an exemplary embodiment of the present invention. Referring to FIG.
FIG. 3B is a diagram illustrating an exponent value of a twiddle factor applied in a conventional Radix-4 processor.
4 is a diagram for explaining the operation of a selection processing unit including a first Radix-2 processing unit and a second Radix-2 processing unit according to an embodiment of the present invention.
FIG. 5A is a diagram illustrating a third Radix-2 processor according to an embodiment of the present invention. Referring to FIG.
5B is a diagram illustrating a conventional third Radix-2 processing unit.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that the invention is not intended to be limited to the particular embodiments, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

The terms first, second, A, B, etc. may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component. And / or < / RTI > includes any combination of a plurality of related listed items or any of a plurality of related listed items.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In the present application, the terms "comprises" or "having" and the like are used to specify that there is a feature, a number, a step, an operation, an element, a component or a combination thereof described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings. Throughout the specification and claims, where a section includes a constituent, it does not exclude other elements unless specifically stated otherwise, but may include other elements.

1 is a schematic block diagram of a Fast Fourier Transform (FFT) apparatus in accordance with an embodiment of the present invention.

1 illustrates an example of a Fast Fourier Transform (FFT) apparatus that provides 256 channel operations of eight channels, in which time-base signals

Figure 112015039274218-pat00001
,
Figure 112015039274218-pat00002
,
Figure 112015039274218-pat00003
,
Figure 112015039274218-pat00004
,
Figure 112015039274218-pat00005
,
Figure 112015039274218-pat00006
,
Figure 112015039274218-pat00007
,
Figure 112015039274218-pat00008
(A) to frequency-axis signals (
Figure 112015039274218-pat00009
,
Figure 112015039274218-pat00010
,
Figure 112015039274218-pat00011
,
Figure 112015039274218-pat00012
,
Figure 112015039274218-pat00013
,
Figure 112015039274218-pat00014
,
Figure 112015039274218-pat00015
,
Figure 112015039274218-pat00016
) ≪ / RTI > (B).

1, a fast Fourier transform apparatus 100 according to an embodiment of the present invention includes an input memory 110, a first address generator 120, a Radix-8 processor (stage 1) 130, a Radix- 2 processing unit (stage 3) 150, a second Radix-2 processing unit (stage 4) 160, a third Radix-2 processing unit (stage 5) 170 An output memory 180, and a second address generator 190.

The input memory 110 receives the time-base signals (< RTI ID = 0.0 >

Figure 112015039274218-pat00017
,
Figure 112015039274218-pat00018
,
Figure 112015039274218-pat00019
,
Figure 112015039274218-pat00020
,
Figure 112015039274218-pat00021
,
Figure 112015039274218-pat00022
,
Figure 112015039274218-pat00023
,
Figure 112015039274218-pat00024
) (A) is temporarily stored. For this purpose, the input memory 110 may store the time-base signals (< RTI ID = 0.0 >
Figure 112015039274218-pat00025
,
Figure 112015039274218-pat00026
,
Figure 112015039274218-pat00027
,
Figure 112015039274218-pat00028
,
Figure 112015039274218-pat00029
,
Figure 112015039274218-pat00030
,
Figure 112015039274218-pat00031
,
Figure 112015039274218-pat00032
(A), and transfers it to the Radix-8 processor 130.

The fast Fourier transform apparatus 100 according to an embodiment of the present invention can vary the computation point by selecting three Radix-2 processing units 150 to 170. [ That is, if only one Radix-2 processing unit operates among the three Radix-2 processing units 150 to 170, a 64-point FFT operation will be performed. If only two Radix- Point FFT operation if all three Radix-2 processors 150-170 are operating. At this time, the processor selection information for selecting a processor to perform an operation among the three Radix-2 processors 150 to 170 is determined according to the performance of the entire system, and can be determined under the control of a system controller (not shown) .

Preferably, among the three Radix-2 processors 150 to 170, the third Radix-2 processor 170 essentially operates and the first Radix-2 processor 150 and the second Radix-2 processor 160 May optionally perform an operation.

In this case, the first Radix-2 processor 150 and the second Radix-2 processor 160 may be referred to as an intermediate processor. In one embodiment of the present invention, the Radix-2 processor 150 ) And the second Radix-2 processing unit 160 may be collectively referred to as a selection processing unit. The operation of the selection processing unit will be described later with reference to Fig.

The output memory 180 converts the frequency-axis signals (

Figure 112015039274218-pat00033
,
Figure 112015039274218-pat00034
,
Figure 112015039274218-pat00035
,
Figure 112015039274218-pat00036
,
Figure 112015039274218-pat00037
,
Figure 112015039274218-pat00038
,
Figure 112015039274218-pat00039
,
Figure 112015039274218-pat00040
) ≪ / RTI > (B). To this end, the output memory 180 outputs the frequency-axis signals (
Figure 112015039274218-pat00041
,
Figure 112015039274218-pat00042
,
Figure 112015039274218-pat00043
,
Figure 112015039274218-pat00044
,
Figure 112015039274218-pat00045
,
Figure 112015039274218-pat00046
,
Figure 112015039274218-pat00047
,
Figure 112015039274218-pat00048
) (B) is temporarily stored and output.

The relationship between the time-base signals and the frequency-axis signals can be defined as in Equation (1).

Figure 112015039274218-pat00049

X (n) represents a time-base signal, n is a time index having an integer value from 0 to N-1, k is a frequency index from 0 to N-1 , ≪ / RTI >

Figure 112015039274218-pat00050
Represents an operation variable for expressing the butterfly operation value and the twiddle factor.

Equation (1) can be expressed as Equation (2) corresponding to the five processing units of FIG. 1 of the present invention.

Figure 112015039274218-pat00051

In this case, k 1 = 0, 1, ..., 7, k 2 = 0, 1, 2, 3, k 3 , k 4 , k 5 = 0, 1, and n 1 = 0, 1,. ..., 7, n 2 = 0, 1, 2, 3, and n 3 , n 4 , n 5 = 0,

Referring to Equation 2, the frequency domain signal x (k) is x (k 1 + 8k 2 + 32k 3 + 64k 4 + 128k 5) is represented by the time-base signal x (n) is x (32n 1 + 8n 2 + 4n 3 + 2n 4 + n 5 ), and the calculation variable

Figure 112015039274218-pat00052
The butterfly operation value of the stage 1 generated in the Radix-8 processor 130 of the stage 1
Figure 112015039274218-pat00053
And stage 1 twiddle factor
Figure 112015039274218-pat00054
, The stage 2 butterfly operation value generated in the Radix-4 processor 140 of the stage 2
Figure 112015039274218-pat00055
And stage 2 twiddle factor
Figure 112015039274218-pat00056
, The stage 3 butterfly operation value generated in the first Radix-2 processor 150 of the stage 3
Figure 112015039274218-pat00057
And stage 3 twiddle factor
Figure 112015039274218-pat00058
, The stage 4 butterfly computation value generated in the second Radix-2 processor 160 of the stage 4
Figure 112015039274218-pat00059
And stage 4 twiddle factor
Figure 112015039274218-pat00060
, The stage 5 butterfly computation value generated in the third Radix-2 processing unit 170 of the stage 5
Figure 112015039274218-pat00061
. ≪ / RTI >

According to Equation (2), the stage 1 twiddle factor

Figure 112015039274218-pat00062
Point twiddle factor, the Radix-8 processor 130 needs a multiplier capable of 32-point twiddle factor calculation, and the stage 2 twiddle factor
Figure 112015039274218-pat00063
Point twiddle factor, the Radix-4 processor 140 requires a multiplier capable of performing a 256-point twiddle factor operation, and the stage 3 twiddle factor
Figure 112015039274218-pat00064
Point twiddle factor, the first Radix-2 processor 150 needs a multiplier capable of 4-point twiddle factor calculation, and the stage 4 twiddle factor
Figure 112015039274218-pat00065
It is known that the second Radix-2 processor 160 requires a multiplier capable of performing 8-point twiddle factor calculations since it is an 8-point-twiddle factor.

FIG. 2A is a diagram illustrating a connection structure between a Radix-8 processor and a Radix-4 processor according to an embodiment of the present invention.

2A, the Radix-8 processor 130 includes a Radix-8 butterfly 131 and seven constant complex multipliers 132 connected to output terminals of the Radix-8 butterfly 131. The Radix- ).

In this case, the Radix-8 butterfly 131 has eight output stages. The k 1 values of the data output from the first output stage to the eighth output stage in the downward direction are 0, 1, 2, 3, 4 , 5, 6, and 7, respectively. The output terminals of the Radix-8 butterfly 131 are connected to the upper 4 stages of the stage 2 through the constant complex multiplier 132 and the 7 output stages of the Radix-8 butterfly 131 are connected to the Radix- 4 output terminal is connected to the delay units 147 at the upper end of the Radix-4 processing unit 140 of the stage 2 through four paths (first path) and the odd- And is connected to the delay units 147 at the lower end of the Radix-4 processing unit 140.

The Radix-4 processor 140 includes a first Radix-4 butterfly 141, a second Radix-4 butterfly 142, four constant complex multipliers 143, four complex multipliers 143, A multiplier 144, a first commutator 145 and a second commutator 146 and a plurality of retarders 147 and 148. [

The plurality of delay units 147 arranged at the input terminal of the Radix-4 processing unit 140 delay the signals output from the Radix-8 processing unit 130 for a predetermined delay time, And the second communicators 145 and 146, respectively.

At this time, the signals through the upper four paths are transmitted to the first communicator 145, and the signals through the lower four paths are transmitted to the second communicator 146.

Each of the first and second commutators 145 and 146 stores and switches the input signals. For example, the first commutator 145 may include delays (2 delays, 4 delays and 6 delays) adjacent the input of the first one of the plurality of delayers 147 (12 delay units, 8 delay units) adjacent to the output terminal of the first communicator 145, and a delay unit for delaying the output signals of the Radix-8 processing unit 130, And a fourth delay line) or an output line directly connected to the first Radix-4 butterfly 141. In this case,

A plurality of delay units 148 arranged in multiple stages at the output ends of the first and second commutators 145 and 146 are connected to the output terminals of the first and second commutators 145 and 146, 4 butterfly 141 and the second Radix-4 butterfly 142 for a predetermined delay time.

In this case, the output signal of the first communicator 145 is transmitted to the first Radix-4 butterfly 141, and the output signal of the second communicator 146 is transmitted to the second Radix-4 butterfly 142 do.

The first Radix-4 butterfly 141 and the second Radix-4 butterfly 142 perform a butterfly operation based on the input signals to the first Radix-4 butterfly 141 and the second Radix-4 butterfly 142, K 2 values of data output from the first output terminal to the fourth output terminal in each of the second Radix-4 butterfly 142 have values of 0, 1, 2, 3, and 4, respectively.

The first Radix-4 butterfly 141 and the second Radix-4 butterfly 142 output the output signal to four constant complex multipliers 143 or four complex multipliers 144 connected to the first Radix-4 butterfly 141 and the second Radix-4 butterfly 142.

At this time, the first Radix-4 butterfly 141 transfers the output signal to the four constant complex multipliers 143, and the second Radix-4 butterfly 142 outputs the output signal to the four complex multipliers 144 The four radix-4 butterfly 142 is connected to the output of the first Radix-4 butterfly 141. The four constant complex multipliers 143 are constant complex multipliers for computing a 128-point twiddle factor, The four complex multipliers 144 connected to the output of the multiplier 144 are complex multipliers that operate on the 256-point twiddle factor.

Hereinafter, the difference between the prior art and the fast Fourier transformer structure of the present invention will be described with reference to FIG. 2B.

FIG. 2B is a diagram illustrating a connection structure between a conventional Radix-8 processor and a Radix-4 processor.

Referring to FIG. 2B, the upper four output stages of the eight output stages of the Radix-8 processor 10 are connected to the delay devices at the upper end of the Radix-4 processor 20 through four paths at the upper stage, And is connected to the delay units at the lower end of the Radix-4 processing unit 20. [

In FIG. 2B, the Radix-4 butterfly on the upper part of the Radix-4 processor 20 and the Radix-4 butterfly on the lower part are connected to the 8 complex multipliers.

2A and FIG. 2B, in FIG. 2A, the odd-numbered output terminals and the even-numbered output terminals of the Radix-8 butterfly 131 are connected to the Radix-4 processor of the stage 2 2, the upper four output terminals and the lower four output terminals of the Radix-8 processor 10 are connected to the Radix-4 processor 20 via the upper four paths and the lower four paths, respectively .

In FIG. 2A, four constant complex multipliers 143 are connected to the output terminal of the first Radix-4 butterfly 141 at the upper end of the Radix-4 processor 140. In FIG. 2B, 4 complex multipliers are connected to the output of the Radix-4 butterfly. Here, the constant complex multiplier connected to the output terminal of the first Radix-4 butterfly 141 at the upper end of the Radix-4 processor 140 is a constant complex multiplier for calculating a 128-point twiddle factor.

In principle, the first Radix-4 butterfly 141 at the top of the Radix-4 processor 140 of FIG. 2A and the Radix-4 butterfly at the top of the Radix-4 processor 20 of FIG. A multiplier for computing a 256-point twiddle factor must be connected to the output of the multiplier. However, even if a multiplier for computing a 128-point twiddle factor is connected to a first Radix-4 butterfly 141 instead of a multiplier for calculating a 256-point twiddle factor, a multiplier for calculating a 256- So that the constant complex multiplier 143 can be connected to the output terminal of the first Radix-4 butterfly 141 instead of the complex multiplier.

If a multiplier for computing a 256-point twiddle factor needs to be connected to the first Radix-4 butterfly 141, a constant complex multiplier can not be connected to the first Radix-4 butterfly 141, and a complex multiplier Should be connected. This is because the structure of the constant complex multiplier becomes excessively complicated when the 256-point twiddle factor is calculated by the constant complex multiplier.

Thus, in the present invention, even if a multiplier for computing a 128-point twiddle factor is connected instead of a multiplier for computing a 256-point twiddle factor to the first Radix-4 butterfly 141, a 256-point twiddle factor is calculated The reason why the multipliers can perform the same function is that odd-numbered output terminals of the Radix-8 butterfly 131 of FIG. 2A are connected to the Radix-4 processor 140 of the stage 2 via the upper four paths.

This will be described in detail as follows.

When the odd-numbered output terminals of the Radix-8 butterfly 131 of FIG. 2A are connected to the Radix-4 processing unit 140 of the stage 2 via the upper four paths, the first Radix- The stage 2 twiddle factor, which is the twiddle factor to be multiplied at the output stage of the butterfly 141,

Figure 112015039274218-pat00066
The index value (4n 3 + 2n 4 + n 5) (k 1 + 8k 2) in is only have an even value.

At this time, the stage 2 twiddle factor

Figure 112015039274218-pat00067
Is expressed by the following equation
Figure 112015039274218-pat00068
(3) " (3) "

Figure 112015039274218-pat00069

In Equation (3), the stage 2 twiddle factor

Figure 112015039274218-pat00070
Index value in the (4n 3 + 2n 4 + n 5) (k 1 + 8k 2) is when to have an even number of values, on the right-hand side term of Equation 3 (4n 3 + 2n 4 + n 5) (k 1 + 8k 2 ) can be regarded as including the number 2, so that the number 2 can divide 256 by about 256, which is equivalent to calculating the 128 twiddle factor.

That is, in the present invention, by having (k 1 + 8k 2 ) have an even value, the stage 2 twiddle factor

Figure 112015039274218-pat00071
Index value (4n 3 + 2n 4 + n 5) of the (k 1 + 8k 2) is created to have an even number of values, which enables the stage 2 twiddle factor
Figure 112015039274218-pat00072
It is possible to use a constant complex multiplier for calculating 128 points instead of a complex multiplier for calculating 256 points.

More specifically, since (k 1 + 8k 2 ) has 8k 2 even values, letting k 1 have an even number (4n 3 + 2n 4 + n 5 ) (k 1 + 8k 2 ) The k 1 values of the data output from the first, third, fifth and seventh output ports of the Radix-8 butterfly 131 are 0, 2, 4, and 6 as described above. 4 butterfly 141 of FIG. 2A by connecting the odd-numbered output terminals of the Radix-8 butterfly 131 to the Radix-4 processing unit 140 of the stage 2 via the upper four paths, Quot; twiddle factor " to be multiplied to the output of the < / RTI > Accordingly, instead of the complex multiplier for calculating 256 points in the Radix-4 butterfly 141, a constant complex multiplier for calculating 128 points can be connected.

As a result, the Radix-4 processor 140 of FIG. 2A includes four constant complex multipliers and four complex multipliers, and the Radix-4 processor 20 of FIG. 2B includes eight complex multipliers, The area occupied by the Radix-4 processing unit 140 of FIG. 2B becomes smaller than the area occupied by the Radix-4 processing unit 20 of FIG. 2B. This is because the area occupied by the constant complex multiplier is smaller than the area occupied by the complex multiplier.

Hereinafter, the exponential values of twiddle factors applied to the present invention and the conventional Radix-4 processors 140 and 20 will be described with reference to FIGS. 3A and 3B. FIG.

FIG. 3A is a diagram illustrating an exponent value of a twiddle factor applied in a Radix-4 processor according to an exemplary embodiment of the present invention. Referring to FIG.

Referring to FIG. 3A, paths 1 through 4 (connected to the odd-numbered output terminals of the Radix-8 butterfly 131) according to 32 cycles are connected to output terminals of the first Radix-4 butterfly 141 according to the present invention And the paths of paths 5 through 8 (connected to the even output terminals of the Radix-8 butterfly 131) are represented by the exponent values of the second Radix-4 butterfly The output values of the twiddle factor to be multiplied by the output of the multiplier 142 are shown.

In FIG. 3A, in the paths 5 to 8, the exponent values of the twiddle factors are mixed with the even and odd values, but the exponent values of the twiddle factors shown in the passes 1 to 4 are all even values.

FIG. 3B is a diagram illustrating an exponent value of a twiddle factor applied in a conventional Radix-4 processor.

3B, the exponent values of the twiddle factor to be multiplied to the output terminal of the Radix-4 butterfly on the upper part of the conventional Radix-4 processor 20 are shown in passes 1 to 4 according to 32 cycles, Paths 5 to 8 show the exponent values of the twiddle factor to be multiplied by the output of the Radix-4 butterfly at the lower end of the conventional Radix-4 processor 20. The values of the twiddle factor It can be seen that all of the exponents are mixed with even and odd numbers.

As shown in FIGS. 3A and 3B, depending on whether the exponent value of the twiddle factor of the paths 1 to 4 includes only the even value or both the even value and the odd value, the upper part of the Radix- A plurality of constant complex multipliers may be coupled to the output terminal of the first Radix-4 butterfly 141 and a plurality of complex multipliers may be connected to the output terminal of the Radix- May be combined.

4 is a diagram for explaining the operation of a selection processing unit including a first Radix-2 processing unit and a second Radix-2 processing unit according to an embodiment of the present invention.

Referring to FIG. 4, the first Radix-2 processor 150 and the second Radix-2 processor 160 are illustrated. The first Radix-2 processor 150 and the second Radix- Collectively referred to as a selection processor.

Hereinafter, the first Radix-2 processor 150 and the second Radix-2 processor 160 will be described with reference to FIG.

First, the first Radix-2 processing unit 150 includes four Radix-2 butterflies 151, four commutators 152, a plurality of delay units 153 and 154, .

Delayers 153 arranged in one of the plurality of input terminals of the communlators 152 delay signals output through the Radix-4 processor 140 for a predetermined delay time and deliver the delayed signals.

Each of the commutators 152 has a plurality of input stages, one of which is connected to the delay unit 153 to delay the signals output from the Radix-4 processing unit 140, 4 processing unit 140 without delay, stores the signals, and then switches the signals.

For example, the communicators 152 temporarily store the signal output from the Radix-4 processor 140 through the delay unit 153 and the signal through the delay unit 153, The output line connected to the delay unit 154 of the output stage or the output line directly connected to the Radix-2 butterfly 151 may be switched.

Delayers 154 disposed at one of the plurality of outputs of the commutators 152 respectively delay the output signals of the commutators 152 and transmit them to the Radix-2 butterflies 151.

The four Radix-2 butterflies 151 include two output stages. The k 3 values of the data output from the first output terminal and the second output terminal have values of 0 and 1, respectively.

At this time, one of the two output terminals of each of the four Radix-2 butterflies 151 is connected to the mux and the other is connected to the constant complex multiplier that multiplies -j. At this time, the constant complex multiplier for multiplying-j is a stage 3 twiddle factor

Figure 112015039274218-pat00073
.

The eight muxes select one of the signals transmitted from the four Radix-2 butterflies 151 or the signal transmitted directly from the Radix-4 processor 140, and transmit the signals to the next stage. At this time, the selection processing unit may determine processing unit selection information for selecting a Radix processing unit to perform an operation among the first Radix-2 processing unit 150 and the second Radix-2 processing unit 160 according to the performance of the entire system. The processing unit can be determined under the control of the system control unit.

For example, when performing a 64-point or 128-point FFT operation, the selection processing unit selects a signal directly transmitted from the Radix-4 processing unit 140 by the mux of the first Radix-2 processing unit 150, The processor selection information can be determined.

Next, the second Radix-2 processing unit 160 includes four Radix-2 butterflies 161, four commutators 162, a plurality of delay units 163 and 164, eight Includes muxes.

The delay units 163 disposed in one of the plurality of input terminals of the communicators 162 receive signals output from the Radix-4 processing unit 140 or the first Radix- Delayed for a period of time.

If the operation of the first Radix-2 processor 150 is selected through the selection processor, the delays 163 receive the signals output through the first Radix-2 processor 150 as inputs, The delay units 162 receive the output signal of the Radix-4 processing unit 140 as an input.

Each of the commutators 162 has a plurality of inputs and one of the inputs is connected to the delays 163 to receive the output of the delays 163 and the other input is connected to the Radix- Receives the signal output from the first radix-2 processing unit 140 or the first Radix-2 processing unit 150 without delay, stores the signals, and then switches the signals. For example, the commutators 162 temporarily store the output signal of the delay unit 163 and the signal not passing through the delay unit 163, and output the delayed signal to the delay unit 164 And can be switched to output to either the connected output line or the output line directly connected to the Radix-2 butterflies 161. [

Delayers 164 respectively disposed at one of the plurality of outputs of the commutators 162 delay the output signals of the commutators 162 and transmit them to the Radix-2 butterflies 161. [

The four Radix-2 butterflies 161 include two input terminals and two output terminals, and the k 4 values of the data output from the first output terminal and the second output terminal have values of 0 and 1, respectively.

At this time, one of the two input ports of each of the four Radix-2 butterflies 161 receives the delayed signal via the delay units 164, and the other receives the delayed signal output from the commutators 162 Receives the signal as input without delay. In addition, the four Radix-2 butterflies 161 include two output stages, and two output stages are all connected to the mux.

The eight muxes select one of the signals transmitted from the four Radix-2 butterflies 161 or the signal transmitted directly from the first Radix-2 processor 150, and transmit the signal to the next stage 170.

The selection processing unit does not select any one of the first Radix-2 processing unit 150 and the second Radix-2 processing unit 160 illustrated in FIG. 4, selects only one or both of them, An operation point can be determined.

For example, if the selection processing unit does not select any of the first Radix-2 processing unit 150 and the second Radix-2 processing unit 160 shown in FIG. 4, the Fast Fourier Transform will perform a 64- If only one of them is selected, the Fast Fourier Transform will perform a 128-point operation, and if both are selected, the Fast Fourier Transform will perform a 256-point operation.

The second Radix-2 processor 160 of FIG. 4 includes a stage 4 twiddle factor

Figure 112015039274218-pat00074
The second Radix-2 processing unit 170 of FIG. 5A does not include a multiplier for generating the second Radix-
Figure 112015039274218-pat00075
And a constant complex multiplier 172 for generating a constant complex multiplier.

However, in another embodiment, the third Radix-2 processing unit 170 of FIG. 5A is composed of only four Radix-2 butterflies 171, and the second Radix-2 processing unit 160 of FIG. May be configured to include four constant complex multipliers 172, commutators 173, a plurality of delayers 174 and 175, and four muxes 176.

FIG. 5A is a diagram illustrating a third Radix-2 processor according to an embodiment of the present invention. Referring to FIG.

Referring to FIG. 5A, the third Radix-2 processor 170 includes four Radix-2 butterflies 171, four constant complex multipliers 172, commutators 173, Delays 174 and 175, and four muxes 176. [

The delay units 174 disposed at one of the plurality of input terminals of the communicators 173 delay signals output through the second Radix-2 processing unit 160 for a predetermined delay time and transmit the delayed signals.

One of the commutators 173 has a plurality of inputs, one of which is connected to the delay 174 to receive the output of the delays 174 as inputs and the other one of which is connected to the Radix-4 processor 140, The first Radix-2 processor 150, and the first Radix-2 processor 150 without delay, stores the signals, and outputs the signals. At this time, the type of the signal to be input to the remaining one input terminal may be determined by the processing unit selection information of the selection processing unit.

Delayers 175 disposed in one of the plurality of output terminals of the commutators 173 delay the output signals of the commutators 173 and transmit them to the Radix-2 butterflies 171.

The four constant complex multipliers 172 are coupled to the stage 4 twiddle factor

Figure 112015039274218-pat00076
And delays 175 of the plurality of output terminals of the commutators 173 are connected to the remaining output terminals that are not connected. Particularly, only the input terminal except for the input terminal to which the signal multiplied by the twiddle factor 1 is input is not required to multiply the twiddle factor among the plurality of input terminals of the Radix-2 butterfly 171, the constant complex multiplier . 5A, the input terminal of the upper end of the Radix-2 butterfly 171 is connected to the delay 175, and the input terminal of the lower end of the Radix-2 butterfly 171 is connected to the constant complex multiplier 178 via the muxes 176. [ A multiplier is not required to be connected to the input terminal of the upper part of the Radix-2 butterfly 171 because a signal that does not need to be multiplied by the twiddle factor or a signal obtained by multiplying the twiddle factor 1 is input. From the viewpoints of the commutators 173, the commutators 173 output a signal that does not need to be multiplied by the twiddle factor or a signal that requires a delay among the signals whose twiddle factor value is 1, And outputs a signal that is not outputted to the output terminal of the complex multiplier 172.

The four muxes 176 are coupled to the output of each of the four constant complex multipliers 172 to select and output one of the output stage signal and the input stage signal of the corresponding complex multipliers 172.

Each of the Radix-2 butterflies 171 performs a butterfly operation based on the input signals inputted thereto, and the k 5 values of the data output from the first output terminal and the second output terminal have values of 0 and 1, respectively do.

Meanwhile, as described above, the third Radix-2 processing unit 170 must be necessarily selected even if it operates at any of the 64-point, 128-point, and 256-point FFT operations.

5B is a diagram illustrating a conventional third Radix-2 processing unit.

5B, the output signal of the previous stage is multiplied by eight constant complex multipliers 32 and then multiplied by the Radix-2 butterflies (delay elements 34 and 35) and the commutators 33 31).

5A and FIG. 5B, in FIG. 5A, by changing the order of the multiplication operation so that the output signal of the preceding stage passes through the delayers 174 and 175 and the commutators 173 and then performs a multiplication operation, The third Radix-2 processor 170 includes the four constant complex multipliers 172. [ Accordingly, the third Radix-2 processor 170 can be implemented with a smaller area than the Radix-2 processor 30 of FIG. 5B including the eight constant complex multipliers 32. FIG.

This is because, if the operation sequence is changed, the data is sorted so that only the odd-numbered passes of the communicators 173 require a multiplication operation and only the odd-numbered passes pass data that does not require a multiplication operation.

The fast Fourier transform apparatus 100 according to an embodiment of the present invention includes five stages of Radix processing units 130, 140, 150, 160, and 170. However, this is an example of the most efficient method, The present invention is not limited to this and can be configured as a Radix processing unit with more or fewer stages than five stages.

The above-described embodiments of the present invention can be embodied in a general-purpose digital computer that can be embodied as a program that can be executed by a computer and operates the program using a computer-readable recording medium.

The computer readable recording medium includes a magnetic storage medium (e.g., ROM, floppy disk, hard disk, etc.), optical reading medium (e.g., CD ROM, DVD, etc.).

The present invention has been described with reference to the preferred embodiments.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the present invention is defined by the appended claims rather than by the foregoing description, and all differences within the scope of equivalents thereof should be construed as being included in the present invention.

Claims (14)

A fast Fourier transform apparatus using a multi-stage processing unit including a plurality of butterflies, a plurality of delay units, a plurality of commutators, a plurality of constant complex multipliers, and a plurality of complex multipliers,
a plurality of constant complex multipliers coupled to some of the output stages of the first butterfly, wherein the odd-numbered output stages comprise a first butterfly having m inputs (Radix-m, m being an even number) A first end processing unit connected to one path and an even end output connected to a second path; And
A second butterfly having an odd number of m / 2 located on the first path, a plurality of constant complex multipliers located on the first path, a third butterfly having a odd number of m / 2 located on the second path, And a second end processing section including a plurality of complex multipliers located in a second path.
The method according to claim 1,
A selection processing unit for selecting an intermediate processing unit to which an output of the second end processing unit is to be passed according to an operation level of the fast Fourier transform apparatus, the intermediate processing unit including a plurality of fourth butterflies having a radix-m / ; And
Further comprising a third end processing unit including a plurality of fifth butterflies having a base-m / 4 and a plurality of constant complex multipliers selectively connected to a plurality of input ends in each of the plurality of fifth butterflies, ,
Wherein the constant complex multiplier selectively connected to one of the plurality of input terminals of the plurality of fifth butterflies includes a first multiplier for multiplying a signal that does not need to be multiplied by the twiddle factor or an input for inputting a signal multiplied by the twiddle factor 1 And an output terminal connected to the input terminal of the high-speed Fourier transformer.
3. The method of claim 2,
The selection processing unit
And an intermediate processing unit including four fourth butterflies of a radix-2 and a radix-2 is composed of two stages.
The method of claim 3,
The intermediate processing unit
Further comprising eight muxes connected to each of the two output terminals of each of the four fourth butterflies to select and output one of a signal at the input of the intermediate processing unit and a signal at the corresponding butterfly output terminal, Conversion device.
5. The method of claim 4,
The intermediate processing unit
Four commutators connected to each of the four fourth butterflies; And
Further comprising eight delay elements selectively connected to one of two input terminals and two output terminals of each of the four commutators.
The method of claim 3,
The selection processing unit
Wherein the fast Fourier transform unit transfers the output of the second end processing unit to the third end processing unit without going through the intermediate processing unit when performing the 64-point calculation.
The method of claim 3,
The selection processing unit
Wherein when the fast Fourier transform apparatus performs a 128-point operation, the output of the second end processing unit is passed to one end of the intermediate processing unit and then transmitted to the third end processing unit. .
The method of claim 3,
The selection processing unit
Wherein when the FFT unit performs a 256-point operation, the FFT unit passes the output of the second end processing unit to both ends of the intermediate processing unit and then transfers the output to the third end processing unit. .
3. The method of claim 2,
The third-
Four fifth butterflies with a radix of -2;
Four constant complex multipliers coupled to one of the plurality of inputs of each of the four fifth butterflies; And
And four muxes connected to an output terminal of each of the four constant complex multipliers to select and output one of a signal at an input terminal and a signal at an output terminal of the corresponding complex multiplier.
10. The method of claim 9,
The third-
Four commutators connected to each of the four fifth butterflies; And
Further comprising eight delay elements selectively connected to one of two input terminals and two output terminals of each of the four commutators.
The method according to claim 1,
The first end-
A first butterfly with a radix of -8; And
And seven constant complex multipliers connected to the output of the first butterfly.
The method according to claim 1,
Wherein the plurality of constant complex multipliers located in the first pass are constant complex multipliers for computing a 128-point twiddle factor,
And a plurality of complex multipliers located in the second path are complex multipliers for calculating a 256-point twiddle factor.
The method according to claim 1,
The second end processing unit
A second butterfly having a radix-4 located in the first pass;
Four constant complex multipliers located in the first pass and coupled to the second butterfly output stage;
A third butterfly having a radix-4 located in the second pass;
And four complex multipliers located in the second path and connected to the third butterfly output stage.
14. The method of claim 13,
The second end processing unit
A plurality of first delays located in the first pass and coupled to the second butterfly input;
A first commutator located at the first path and coupled to the inputs of the plurality of first delay units;
A plurality of second delays located in the first pass and coupled to an input of the first commutator;
A plurality of third delays located in the second pass and coupled to the third butterfly input;
A second commutator located at the second pass and coupled to the inputs of the plurality of third delay units;
And a plurality of fourth delay units located in the second path and connected to an input of the second commutator.
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