KR20060073189A - Method for forming cu metal line of semiconductor device - Google Patents

Method for forming cu metal line of semiconductor device Download PDF

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KR20060073189A
KR20060073189A KR1020040112060A KR20040112060A KR20060073189A KR 20060073189 A KR20060073189 A KR 20060073189A KR 1020040112060 A KR1020040112060 A KR 1020040112060A KR 20040112060 A KR20040112060 A KR 20040112060A KR 20060073189 A KR20060073189 A KR 20060073189A
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forming
copper
wiring
trench
copper wiring
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KR1020040112060A
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Korean (ko)
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이준우
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동부일렉트로닉스 주식회사
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Priority to KR1020040112060A priority Critical patent/KR20060073189A/en
Priority to US11/319,341 priority patent/US20060138670A1/en
Publication of KR20060073189A publication Critical patent/KR20060073189A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76849—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned on top of the main fill metal
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76867—Barrier, adhesion or liner layers characterized by methods of formation other than PVD, CVD or deposition from a liquids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

본 발명은 스트레스 마이그레이션으로 발생하는 힐록(hillock)과 보이드(void)를 개선하여 배선의 신뢰성을 향상시키도록 한 반도체 소자의 구리(Cu)배선 형성방법에 관한 것으로서, 반도체 기판의 표면내에 소정깊이를 갖는 트랜치를 형성하는 단계와, 상기 트랜치를 포함한 반도체 기판의 전면에 베리어 금속막을 형성하는 단계와, 상기 베리어 금속막상에 구리 박막을 형성하는 단계와, 상기 구리 박막의 전면에 평탄화 공정을 진행하여 상기 트랜치의 내부에 구리배선을 형성하는 단계와, 상기 구리배선을 질소 분위기에서 열처리하는 단계와, 상기 열처리된 구리배선에 수소화규소 분위기에서 실리사이드화하여 상기 구리배선의 표면에 실리사이드막을 형성하는 단계를 포함하여 형성함을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming copper (Cu) wiring of a semiconductor device to improve the reliability of wiring by improving hilllock and void caused by stress migration. Forming a trench having a trench, forming a barrier metal film on the entire surface of the semiconductor substrate including the trench, forming a copper thin film on the barrier metal film, and planarizing the entire surface of the copper thin film. Forming a copper wiring inside the trench, heat-treating the copper wiring in a nitrogen atmosphere, and silicideizing the heat-treated copper wiring in a silicon hydride atmosphere to form a silicide film on the surface of the copper wiring. It is characterized by forming.

구리배선, 실리사이드화, CMP Copper wiring, silicided, CMP

Description

반도체 소자의 구리배선 형성방법{method for forming Cu metal line of semiconductor device}Method for forming Cu metal line of semiconductor device

도 1a 내지 도 1d는 본 발명에 의한 반도체 소자의 구리배선 형성방법을 나타낸 공정단면도1A to 1D are cross-sectional views illustrating a method of forming copper wirings of a semiconductor device according to the present invention.

도면의 주요 부분에 대한 설명Description of the main parts of the drawing

31 : 반도체 기판 32 : 트랜치31 semiconductor substrate 32 trench

33 : 베리어 금속막 34 : 구리 박막33: barrier metal film 34: copper thin film

35 : 구리배선 36 : 실리사이드막35 copper wiring 36 silicide film

본 발명은 반도체 소자의 금속배선에 관한 것으로서, 특히 배선의 신뢰성을 향상시키도록 한 반도체 소자의 구리배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metal wiring of semiconductor devices, and more particularly to a method for forming copper wiring in semiconductor devices to improve the reliability of wiring.

일반적으로, 반도체 소자의 금속배선으로 널리 사용하는 금속으로 알루미늄(Al), 알루미늄 합금 및 텅스텐(W) 등이 있다. Generally, metals widely used as metal wirings of semiconductor devices include aluminum (Al), aluminum alloys, and tungsten (W).

그러나, 이러한 금속들은 반도체 소자가 고집적화됨에 따라 낮은 융점과 높은 비저항으로 인하여 초고집적 반도체 소자에 더 이상 적용이 어렵게 되었다. However, these metals are no longer applicable to ultra-high density semiconductor devices due to the low melting point and high resistivity as semiconductor devices are highly integrated.

따라서, 금속배선의 대체 재료에 대한 개발 필요성이 대두되고 있는 실정이다. 대체 재료로 전도성이 우수한 물질인 구리(Cu), 금(Au), 은(Ag), 코발트(Co), 크롬(Cr), 니켈(Ni) 등이 있으며, 이러한 물질들 중 비저항이 작고, 일렉트로 마이그레이션(electro migration ; EM)과 스트레스 마이그레이션(stress migration; SM) 등의 신뢰성이 우수하며, 생산원가가 저렴한 구리 및 구리 합금이 널리 적용되고 있는 추세이다.Therefore, there is a need for development of alternative materials for metal wiring. Alternative materials include copper (Cu), gold (Au), silver (Ag), cobalt (Co), chromium (Cr), and nickel (Ni), which are highly conductive materials. Copper and copper alloys with high reliability and low production cost, such as electro migration (EM) and stress migration (SM), are widely applied.

종래의 구리배선은 알루미늄보다 고유저항(resistivity)을 갖고 있어 RC 시간 지연을 줄일 수 있으므로, 0.13㎛이하의 디자인 룰(design rule)을 갖는 소자에서 사용하게 되었다.Conventional copper wiring has a specific resistivity (resistivity) than aluminum and can reduce the RC time delay, it is used in devices having a design rule of 0.13㎛ or less.

그런데 구리배선의 열팽창 계수는 유전체막(dielectric film)보다 10배정도 큰 값을 가지며, 이로 인해 압축 스트레스(compressive stress)가 쌓이게 되는데, 이것이 크면 스트레스 완화를 위하여 힐록(hillock)이 형성되어 공정 신뢰성(reliability)에 영향을 주게 된다.However, the coefficient of thermal expansion of copper wiring is 10 times larger than that of a dielectric film, which causes compressive stress to accumulate. ) Is affected.

한편, 상기와 같은 공정 신뢰성의 악영향을 줄이기 위해 구리 일렉트로 케미컬 플레이팅(Cu electro chemical plating) 후에 어닐링(annealing) 처리로 플레이팅시 발생하는 스트레스를 완화시킬 수 있으나, 최근 보고서에 의하면 구리 박막은 CMP 등의 평탄화 공정으로 다시 스트레스가 발생하고 있다.On the other hand, in order to reduce the adverse effects of the process reliability as described above, the stress generated during plating by annealing after Cu electro chemical plating (Cu electro chemical plating) can be alleviated, but according to a recent report, the copper thin film is CMP The stress is generated again by the planarization process.

따라서 상기와 같은 스트레스가 제거되지 않으면 후속 공정에서 스트레스 마이그레이션(stress migration) 현상이 생기게 된다.Therefore, if such stress is not removed, a stress migration phenomenon occurs in a subsequent process.

본 발명은 상기와 같은 종래의 문제점을 해결하기 위한 것으로, 스트레스 마이그레이션으로 발생하는 힐록(hillock)과 보이드(void)를 개선하여 배선의 신뢰성을 향상시키도록 한 반도체 소자의 구리(Cu)배선 형성방법을 제공하는데 그 목적이 있다. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a method of forming copper (Cu) wiring of a semiconductor device to improve the reliability of wiring by improving the hillock and void caused by stress migration. The purpose is to provide.

상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 구리배선 형성방법은 반도체 기판의 표면내에 소정깊이를 갖는 트랜치를 형성하는 단계와, 상기 트랜치를 포함한 반도체 기판의 전면에 베리어 금속막을 형성하는 단계와, 상기 베리어 금속막상에 구리 박막을 형성하는 단계와, 상기 구리 박막의 전면에 평탄화 공정을 진행하여 상기 트랜치의 내부에 구리배선을 형성하는 단계와, 상기 구리배선을 질소 분위기에서 열처리하는 단계와, 상기 열처리된 구리배선에 수소화규소 분위기에서 실리사이드화하여 상기 구리배선의 표면에 실리사이드막을 형성하는 단계를 포함하여 형성함을 특징으로 한다.The copper wiring forming method of a semiconductor device according to the present invention for achieving the above object is to form a trench having a predetermined depth in the surface of the semiconductor substrate, and to form a barrier metal film on the entire surface of the semiconductor substrate including the trench Forming a copper thin film on the barrier metal film, forming a copper wiring on the entire surface of the copper thin film, and heat-treating the copper wiring in a nitrogen atmosphere. And forming a silicide film on the surface of the copper wiring by silicidating the heat-treated copper wiring in a silicon hydride atmosphere.

이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 구리배선 형성방법을 보다 상세히 설명하면 다음과 같다.Hereinafter, a copper wiring forming method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.

도 1a 내지 도 1d는 본 발명의 실시예에 따른 반도체 소자의 구리배선 형성방법을 나타낸 공정단면도이다.1A to 1D are cross-sectional views illustrating a method of forming copper wirings in a semiconductor device according to an exemplary embodiment of the present invention.

도 1a에 도시한 바와 같이, 반도체 기판(31)(또는 층간 절연막)에 포토 및 식각 공정을 통해 상기 반도체 기판(31)을 선택적으로 제거하여 소정깊이를 갖는 트랜치(32)를 형성한다.As shown in FIG. 1A, a trench 32 having a predetermined depth is formed by selectively removing the semiconductor substrate 31 through a photolithography process and an etching process on the semiconductor substrate 31 (or an interlayer insulating layer).

여기서, 상기 트랜치(32)만을 설명하고 있지만 듀얼 다마신 공정 등에 의한 비아홀 또는 콘택홀 및 트랜치를 형성할 수도 있다.Here, although only the trench 32 is described, via holes or contact holes and trenches may be formed by a dual damascene process.

이어, 상기 트랜치(32)를 포함한 상기 반도체 기판(31)의 전면에 베리어 금속(barrier metal)막(33)을 형성한다. Next, a barrier metal layer 33 is formed on the entire surface of the semiconductor substrate 31 including the trench 32.

여기서, 상기 베리어 금속막(33)은 물리기상증착법이나 화학기상증착법으로 TiN, Ta, TaN, WNX, TiAl(N) 등을 10 내지 1000Å의 두께로 증착하여 형성하며, 상기 베리어 금속막(33)은 후에 형성되는 구리 박막으로부터의 구리 원자가 반도체 기판(31)으로 확산하는 것을 방지하는 역할을 한다.Here, the barrier metal film 33 is formed by depositing TiN, Ta, TaN, WNX, TiAl (N), etc. in a thickness of 10 to 1000 kPa by physical vapor deposition or chemical vapor deposition, and the barrier metal film 33 The copper atom from the copper thin film formed after the silver serves to prevent diffusion into the semiconductor substrate 31.

그리고 상기 베리어 금속막(33)을 포함한 반도체 기판(31)의 전면에 구리 박막(34)을 형성한다.A copper thin film 34 is formed on the entire surface of the semiconductor substrate 31 including the barrier metal film 33.

여기서, 상기 구리 박막(34)을 형성하는 방법은 전기도금법을 이용하고 있는데, 상기 전기도금법은 안정하고 깨끗한 구리 시드층(seed layer)의 증착이 필수적인 공정으로 되어 있다. In this case, the copper thin film 34 is formed by an electroplating method, which is an essential process for depositing a stable and clean copper seed layer.

또한, 다른 방법은 물리기상증착(PVD)법을 이용한 챔버 및 화학기상증착(CVD)법을 이용한 챔버로 구성된 장비에서 확산 방지막 및 구리 시드층을 증착한 후에 구리 전기도금 장비에서 구리 전기도금을 진행할 수도 있다.In addition, another method is to deposit the diffusion barrier and the copper seed layer in the equipment consisting of a chamber using a physical vapor deposition (PVD) method and a chamber using a chemical vapor deposition (CVD) method, and then copper electroplating in the copper electroplating equipment. It may be.

상기 구리 박막(34)은 구리 시드층을 형성한 후에 진공파괴 없이 구리 시드층 상에 금속-유기 화학기상증착(MOCVD)법이나 전기도금법으로 구리를 증착하여 형성한다.The copper thin film 34 is formed by depositing copper by metal-organic chemical vapor deposition (MOCVD) or electroplating on the copper seed layer without vacuum destruction after forming the copper seed layer.

여기서, 상기 금속-유기 화학기상증착법으로 구리 박막을 증착할 경우, 증착 온도는 50 내지 300℃로 하며, 전구체(precursor)를 5 내지 100sccm(standard cubic centimeter per minute) 사용한다. 여기서, 전구체는 (hfac)CuTMVS 및 첨가제가 포함된 그 혼합체, (hfac)CuVTMOS 및 첨가제가 포함된 그 혼합체, 또는 (hfac)CuPENTENE 및 첨가제가 포함된 그 혼합체를 사용한다.Here, when depositing a copper thin film by the metal-organic chemical vapor deposition method, the deposition temperature is 50 to 300 ℃, a precursor (precursor) is used 5 to 100 sccm (standard cubic centimeter per minute). Here, the precursor uses a mixture containing (hfac) CuTMVS and an additive, a mixture containing (hfac) CuVTMOS and an additive, or a mixture containing (hfac) CuPENTENE and an additive.

또한, 상기 전기도금법으로 구리 박막(34)을 증착할 경우, 구리 시드층을 형성한 후에 진공파괴 없이 -20 내지 150℃의 저온에서 구리를 증착한다.In addition, when the copper thin film 34 is deposited by the electroplating method, after the copper seed layer is formed, copper is deposited at a low temperature of −20 to 150 ° C. without vacuum destruction.

도 1b에 도시한 바와 같이, 상기 반도체 기판(31)상에 형성된 베리어 금속막(33)을 폴리싱 스톱(polishing stop)으로 하여 상기 구리 박막(34)의 전면에 CMP 공정을 통해 평탄화 공정을 진행하여 상기 트랜치(32)의 내부에 구리배선(35)을 형성한다.As shown in FIG. 1B, a planarization process is performed on the entire surface of the copper thin film 34 by a CMP process using the barrier metal film 33 formed on the semiconductor substrate 31 as a polishing stop. The copper wiring 35 is formed in the trench 32.

도 1c에 도시한 바와 같이, 상기 트랜치(32)의 내부에 형성된 구리배선(35)을 약 150 ~ 300℃ 온도의 질소(N2) 분위기에서 열처리를 실시하고, 다시 연속적으로 수산화규소(SiH4) 분위기에서 상기 구리배선(35)의 표면에 실리사이드(silicide)화하여 상기 구리배선(35)의 표면에 실리사이드막(36)을 형성한다.As illustrated in FIG. 1C, the copper wiring 35 formed in the trench 32 is heat-treated in an atmosphere of nitrogen (N 2 ) at a temperature of about 150 to 300 ° C., and then silicon hydroxide (SiH 4) is continuously formed. Silicide is formed on the surface of the copper wiring 35 in an atmosphere to form a silicide film 36 on the surface of the copper wiring 35.

여기서, 상기 실리사이드막(36)은 상기 구리배선(35) 표면의 산화를 방지할 수 있다.Here, the silicide layer 36 may prevent oxidation of the surface of the copper wiring 35.

도 1d에 도시한 바와 같이, 상기 반도체 기판(31)의 상부 표면을 폴리싱 스톱으로 하여 베리어 금속막(33) 및 실리사이드막(36)을 선택적으로 연마하여 상기 트랜치 영역에만 구리배선(35)을 형성한다.As shown in FIG. 1D, the barrier metal film 33 and the silicide film 36 are selectively polished using the upper surface of the semiconductor substrate 31 as the polishing stop to form the copper wiring 35 only in the trench region. do.

이상 설명한 내용을 통해 당업자라면 본 발명의 기술 사상을 이탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

따라서, 본 발명의 기술적 범위는 실시예에 기재된 내용으로 한정하는 것이 아니라 특허 청구범위에 의해서 정해져야 한다.Therefore, the technical scope of the present invention should not be limited to the contents described in the examples, but should be defined by the claims.

이상에서 설명한 바와 같은 본 발명에 따른 반도체 소자의 구리배선 형성방법에 있어서 다음과 같은 효과가 있다.The copper wiring forming method of the semiconductor device according to the present invention as described above has the following effects.

첫째, CMP 공정을 통해 구리배선을 형성한 후에 열처리를 진행함으로써 스트레스를 완화하여 배선의 신뢰성을 향상시킬 수 있다.First, after the copper wiring is formed through the CMP process, heat treatment may be performed to reduce stress to improve reliability of the wiring.

둘째, 구리배선의 표면에 실리사이드막을 형성하여 구리배선의 산화를 방지하여 배선의 신뢰성을 향상시킬 수 있다. Second, by forming a silicide film on the surface of the copper wiring to prevent oxidation of the copper wiring can improve the reliability of the wiring.

Claims (4)

반도체 기판의 표면내에 소정깊이를 갖는 트랜치를 형성하는 단계;Forming a trench having a predetermined depth in the surface of the semiconductor substrate; 상기 트랜치를 포함한 반도체 기판의 전면에 베리어 금속막을 형성하는 단계;Forming a barrier metal film on an entire surface of the semiconductor substrate including the trench; 상기 베리어 금속막상에 구리 박막을 형성하는 단계;Forming a copper thin film on the barrier metal film; 상기 구리 박막의 전면에 평탄화 공정을 진행하여 상기 트랜치의 내부에 구리배선을 형성하는 단계;Performing a planarization process on the entire surface of the copper thin film to form copper wiring inside the trench; 상기 구리배선을 질소 분위기에서 열처리하는 단계;Heat-treating the copper wiring in a nitrogen atmosphere; 상기 열처리된 구리배선에 수소화규소 분위기에서 실리사이드화하여 상기 구리배선의 표면에 실리사이드막을 형성하는 단계를 포함하여 형성함을 특징으로 하는 반도체 소자의 구리배선 형성방법.Forming a silicide film on the surface of the copper wiring by silicideating the heat-treated copper wiring in a silicon hydride atmosphere. 제 1 항에 있어서, 상기 실리사이드막을 형성하고 상기 반도체 기판을 폴리싱 스톱으로 하여 전면에 평탄화 공정을 실시하는 단계를 더 포함하여 형성함을 특징으로 하는 반도체 소자의 구리배선 형성방법.The method of claim 1, further comprising forming the silicide layer and performing a planarization process on the entire surface of the semiconductor substrate as a polishing stop. 제 1 항에 있어서, 상기 질소 분위기의 열처리는 약 150 ~ 300℃에서 실시하는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The method of claim 1, wherein the heat treatment of the nitrogen atmosphere is performed at about 150 ~ 300 ℃. 제 1 항에 있어서, 상기 구리 박막은 전기 도금법 또는 CVD, PVD, MOCVD 중에서 어느 하나를 사용하여 증착하는 것을 특징으로 하는 반도체 소자의 구리배선 형성방법.The method of claim 1, wherein the copper thin film is deposited using any one of electroplating or CVD, PVD, or MOCVD.
KR1020040112060A 2004-12-24 2004-12-24 Method for forming cu metal line of semiconductor device KR20060073189A (en)

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