KR20060070290A - Method of fabricating phase change memory device including fine contact point formation process - Google Patents

Abstract

A method of manufacturing a phase change memory device is provided. The present invention forms a polysilicon pattern by patterning a polysilicon layer in a lithography apparatus, and forms a polysilicon pattern having a small critical line width by oxidizing the polysilicon pattern. Fine holes may be formed in the metal mask layer using the polysilicon pattern having a smaller critical line width, and fine contacts may be formed in the insulating layer by the micro holes. Accordingly, the present invention can manufacture a low power consumption type high density phase change memory device using the fine contact forming process.

Description

Method for fabricating phase change memory device including fine contact point formation process

1 is a flowchart illustrating only a fine contact forming process in a method of manufacturing a phase change memory device according to the present invention.

2 to 10 are cross-sectional views illustrating a method of manufacturing a phase change memory device including a fine contact forming process according to an embodiment of the present invention.

11 is a cross-sectional view illustrating a method of manufacturing a phase change memory device including a process of forming a fine contact according to another exemplary embodiment of the present invention.

FIG. 12 is a photo illustrating fine contacts formed when a phase change memory device is manufactured according to the present invention.

The present invention relates to a phase change memory device, and more particularly, to a method of manufacturing a phase change memory device including a fine contact forming process.

The nonvolatile memory device, which has the characteristic that the stored information does not disappear even after the power is cut off after storing the information, has made rapid progress with the recent explosive demand of portable personal terminal devices. Currently, flash memory occupies most of the market for nonvolatile memory devices for mobile devices. This is because flash memory devices offer the advantages of low cost and high density based on existing silicon semiconductor processes.

However, due to problems such as the use of a relatively high voltage for storing information and the limited number of repetitive storage of information, researches and developments of next-generation nonvolatile memory devices have been actively conducted to overcome them. .

Next-generation nonvolatile memory devices can be classified into two types according to information storage methods. The first is a capacitor type memory device, the second is a resistor type memory device. A representative example of a capacitor type memory device is a ferroelectric memory device using a ferroelectric material. The ferroelectric memory element has a form in which the polarization direction of the ferroelectric thin film constituting the capacitor is aligned in a predetermined direction when a voltage is applied, and the type of stored information is read out from the difference in the polarization direction. Ferroelectric materials used are mainly ferroelectric oxide materials, but recently, research is being conducted on nonvolatile memory devices using ferroelectric organic materials.

Resistor-type nonvolatile memory devices are typical of magnetoresistive memory devices and phase change memory devices. Magneto-resistive RAM (MRAM) has a device structure in which a very thin insulating layer is inserted between two magnetic materials. The magnetoresistive memory element stores information by controlling the spin polarization direction of two magnetic materials surrounding the insulating layer, and from the magnitude of the tunnel current passing through the insulating layer between the cases where the spin polarization directions are the same and different from each other, that is, the magnitude of the resistance. The type of stored information is read.

Phase-Change RAM (PRAM) devices control the crystal state of a material by selecting a method of applying current or voltage under appropriate conditions by using a phase-change material whose resistance value changes according to the crystal state of a material. It is a method of storing information and reading the type of stored information from the change of the resistance value according to the crystal state of the material.

Each type of nonvolatile memory device has its advantages and disadvantages. For example, a ferroelectric memory device has a long history of research and development, and satisfies most of the performance required as a next generation nonvolatile memory device. However, the ferroelectric memory device has difficulty in miniaturization, and there is a problem in realizing the degree of integration beyond the flash memory device using current technology.

Magneto-resistive memory devices have the advantage of very high operating speeds, but the device's operating characteristics are likely to deteriorate with the miniaturization of the device, and the power consumption of the device is inevitably increased with the miniaturization of the device. There are disadvantages.

On the other hand, the phase change memory device can use the chalcogenide metal alloy phase change material, which has been mainly used for optical storage information devices such as CD-RW and DVD, and the manufacturing process is conventional silicon-based device. The good match with the manufacturing process is that it can easily achieve the same degree of integration as DRAM. Therefore, in view of the state of the art development so far, it is attracting great attention as the most promising next-generation nonvolatile memory device candidate that can replace the current flash memory device.

However, in order to commercialize the phase change memory device, it is necessary to greatly reduce power consumption required for driving. As described above, since the phase change memory device is driven by a method of controlling the crystal state of the phase change material by using Joule heat generated when a current flows through the resistor, it may inevitably consume a lot of power. In addition, this problem is related to the fact that the phase change memory device has recently gained attention in recent years, while having relatively advantageous advantages over other nonvolatile memories.

In other words, the design rules used in the semiconductor process have been reduced by a certain scaling method, and when manufacturing a phase change memory device using a conventional semiconductor process that manufactured a relatively large sized device, the entire system cannot afford it. The realization of the memory device was impossible due to the problem of power and heat generation. However, the size of the device itself is greatly reduced along with the continuous reduction of design rules, and using the design rules of the semiconductor process, which is generally used now, can significantly reduce the power consumption required for the operation of the phase change memory device.

Efforts to reduce the amount of current for the operation of phase change memory devices are ongoing, which is closely related to the densification of phase change memory devices. Development of a low power consumption device structure is essential to ensure reliable memory operation of a high density phase change memory device. This has another important purpose in addition to reducing the absolute power consumption of the entire phase change memory array.

That is, the heat generated during the memory operation of a particular device should not destroy or change the information stored in the adjacent memory device. In particular, the spacing of each device in the memory array having a high density is very likely to be reduced, and in some cases, a specific cell memory operation itself may be a factor that inhibits the memory operation of an adjacent cell.

In order to reduce the value of the current required to operate the phase change memory device, two methods are typically used.

First, a method of reducing the required current value by lowering the temperature required for phase transition by employing a phase change material having a relatively low melting point. This uses the same device structure and changes the phase change material itself to reduce the overall power consumption of the phase change memory device.

Second, a method of reducing a required current value by minimizing a phase change region, which is an operation core part of a phase change memory device. That is, since the phase change memory device experiences a phase transition state using heat generated at the contact portion of the phase change material and the electrode material, the total power consumption of the phase change memory can be greatly reduced by minimizing the contact portion.

Of these, the most common way to achieve the second method is to form fine contacts using a lithography process that can form finer patterns. That is, the size of the fine contact required for the fabrication of the phase change memory device is determined by the limitation of the resolution of the lithography process used unless another special method is employed. Thus, using electron beam lithography with the highest resolution of currently available lithography equipment, it is theoretically possible to machine fine contacts with dimensions of tens of nanometers.

However, only the contact formation during the entire process of device fabrication has to be incurred in process complexity and cost. Therefore, it is more effective than the resolution of the lithography process using the size of the fine contact of the phase change material and the electrode material in the fabrication of the phase change memory device while using the same lithography process to process patterns other than the fine contact. If it can be formed, it is obvious that it will greatly contribute to the low power consumption of the memory device.

In addition, it is preferable that the formed fine contact is made to the same size in a predetermined area on a predetermined substrate. In addition, if the method of forming a fine contact is likely to cause a size difference of more than a certain distribution on a predetermined substrate, it is difficult to employ such a formation method in the fabrication of an actual memory device. The reason is that the smaller the size of the micro-contact, the smaller the amount of current required, and the distribution between the elements of the size of the micro-contact is more likely to cause different operation between operating cells under the same current conditions. This is because the opposite results.

Accordingly, the technical problem to be achieved by the present invention is to change the phase of low power consumption, including the process of forming a micro-contact point to form the size of the micro-contact point more than the resolution of the lithography process, and uniformly formed on the same substrate while using a conventional lithography process The present invention provides a method for manufacturing a memory device.

In order to achieve the above technical problem, the phase change memory device of the present invention is a first insulating layer on a semiconductor substrate. A lower metal electrode layer, a heat generating metal electrode layer, and a second insulating layer. Sequentially forming a sacrificial oxide layer and a polysilicon layer. Subsequently, the polysilicon layer is patterned to form a first polysilicon pattern having a critical line width of L1. The first polysilicon pattern is oxidized to form a second polysilicon pattern having a critical line width L2 smaller than L1. The sacrificial oxide layer is etched using the second polysilicon pattern as an etch mask to form a sacrificial oxide pattern. A metal mask layer is formed on the second insulating layer between the stacked structure of the second polysilicon pattern and the sacrificial oxide pattern. The sacrificial oxide pattern and the second polysilicon pattern are removed to form a metal mask pattern having micro holes. The second insulating layer is etched using the metal mask pattern having the fine holes as an etch mask to form fine contacts. The metal mask pattern is removed.

The second polysilicon pattern may be obtained by oxidizing the first polysilicon pattern to form an oxide layer and removing the oxide layer. A metal mask layer may also be formed on the second polysilicon pattern, and the sacrificial oxide pattern and the second polysilicon pattern may be removed by a liftoff method. Preferably, the second insulating layer is formed of a nitride film.

The microcontact point may be determined according to the amount of oxidation of the first polysilicon pattern. After the fine contact is formed, a phase change layer is formed on the fine contact point, a third insulating layer having a contact hole to open the phase change layer is formed, and is formed in the contact hole to contact the phase change layer. The upper metal electrode layer may be formed.

After forming the fine contact, a phase change layer buried in the fine contact may be formed, and an upper metal electrode layer connected to the phase change layer may be formed on the phase change layer and the second insulating layer.

Hereinafter, with reference to the accompanying drawings will be described embodiments of the present invention; However, embodiments of the present invention illustrated below may be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Embodiments of the present invention are provided to more completely explain the present invention to those skilled in the art. In the drawings, the size or thickness of films or regions is exaggerated for clarity.

1 is a flowchart illustrating only a fine contact forming process in a method of manufacturing a phase change memory device according to the present invention.

Specifically, the insulating layer is formed on the substrate for manufacturing the phase change memory device formed up to the lower metal electrode layer by using a suitable process method. At this time, the insulating layer formed is formed of a nitride film in consideration of the relationship with the subsequent process (step 100).

After the insulating layer forming process is completed, the sacrificial oxide layer and the polysilicon layer are continuously formed on the insulating layer. The thickness of the sacrificial oxide layer and the polysilicon layer is appropriately selected in consideration of the correlation with the subsequent process (step 102).

After the polysilicon layer forming process is completed, the polysilicon layer is patterned using a lithography apparatus to form a first polysilicon pattern. At this time, the lithography equipment used is i-line, KrF, or ArF as a light source. The critical line width of the first polysilicon pattern is determined by the resolution of the lithographic equipment used (step 104).

When the patterning process of the polysilicon layer is completed, the first polysilicon pattern is oxidized by a dry or wet oxidation method. Accordingly, the first polysilicon pattern is oxidized to form an oxide layer on the surface and both sidewalls of the first polysilicon pattern (step 106).

When the oxidation process of the first polysilicon pattern is completed, the oxide layer formed on the surface and both sidewalls of the first polysilicon pattern is removed through a wet etching process using an aqueous hydrogen fluoride (HF) solution. In this case, the height and the critical line width of the first polysilicon pattern are lowered below the resolution of the lithographic apparatus to become the second polysilicon pattern. In other words, a second polysilicon pattern lower than the critical line width of the first polysilicon pattern is formed (step 107).

Next, the sacrificial oxide layer is etched using the second polysilicon pattern lowered below the resolution of the lithographic apparatus as an etching mask. Since this process requires high etching anisotropy, a dry etching process is used (step 108).

When the etching process of the sacrificial oxide layer is finished, a predetermined metal mask film to be used as a mask is deposited in a subsequent process. The type and thickness of the metal mask film are appropriately selected in consideration of the relationship with subsequent processes. Subsequently, the laminated structure of the sacrificial oxide layer, the polysilicon pattern, and the metal mask film is removed by a lift-off process using an aqueous hydrogen fluoride solution (step 110).

When the laminated structure including the sacrificial oxide layer, the polysilicon pattern, and the metal mask layer is removed, minute holes having a predetermined size are formed on the substrate between the metal mask layers. In other words, a metal mask pattern having fine holes is formed on the insulating layer (step 112).

The insulating layer is etched using a metal mask pattern having fine holes as an etching mask. Since the etching process of the insulating layer also requires high etching anisotropy, a dry etching process is used (step 113).

The metal contact pattern may be removed or, in some cases, fine contacts may be formed on the insulating layer by using an etching condition in which all of the metal mask patterns are removed during the insulating layer etching process. The size of the fine contact point is determined according to the oxidation rate of the first polysilicon pattern, which is determined by the size of the first polysilicon pattern formed by the lithography process, the oxidation temperature and the time of the oxidation process of oxidizing the first polysilicon pattern. (Step 114).

2 to 10 are cross-sectional views illustrating a method of manufacturing a phase change memory device including a fine contact forming process according to an embodiment of the present invention.

Referring to FIG. 2, a first insulating layer 12 is formed on a semiconductor substrate 10, for example, a silicon substrate. The first insulating layer 12 is formed of a silicon oxide film formed by thermal oxidation of a silicon substrate or another insulating layer. The first insulating layer 12 is formed of a material capable of electrically or thermally insulating the semiconductor substrate 10 and the phase change memory device. The lower metal electrode layer 14 and the heat generating metal electrode layer 16 of the phase change memory device are sequentially stacked on the first insulating layer 12.

The lower metal electrode layer 14 serves as a lower terminal of the phase change memory device and is formed of a low resistance metal film. The lower metal electrode layer 14 is formed of platinum (Pt), tungsten (W) or titanium tungsten alloy (TiW). The lower metal electrode layer 14 is formed by a general metal electrode forming method.

The heat generating metal electrode layer 16 serves to generate sufficient heat to change the crystal state of the phase change layer 38 at the contact portion with the phase change layer 38 (FIG. 10) formed later. This is achieved by the current supplied through the lower metal electrode layer 14, so that the resistance of the exothermic metal electrode layer 16 is higher than that of a general metal electrode. Selection of the material constituting the heat generating metal electrode layer 16 is an important factor in determining the operating characteristics of the phase change memory device. The exothermic metal electrode layer 16 is formed of titanium nitride (TiN), titanium oxynitride (TiON), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), or tantalum silicon nitride (TiSiN).

Referring to FIG. 3, a second insulating layer 18 is formed on the heat generating metal electrode layer 16. The second insulating layer 18 is formed of a different type from the sacrificial oxide layer to be used in a subsequent process. The reason is to secure the etching selectivity with the sacrificial oxide layer during the etching process of the sacrificial oxide layer to be used in the subsequent process as described in FIG. Therefore, in this embodiment, it is most preferable to use a silicon nitride film which is an insulating layer other than the silicon oxide film, but it is also possible to form an insulating layer of other materials having similar performance in some cases.

The sacrificial oxide layer 20 and the polysilicon layer 22 are formed on the second insulating layer 18. The thickness of the sacrificial oxide layer 20 is formed thick enough to allow the subsequent liftoff process to be performed without problems as described in FIG. 1. In this embodiment, the sacrificial oxide layer 20 is formed to a thickness of at least 500nm. In the present embodiment, the thickness of the polysilicon layer 22 is selected in consideration of the size of the fine contact to be formed. This is selected in consideration of the oxidation rate upon oxidation of the subsequent first polysilicon pattern as described in FIG. 1.

Referring to FIG. 4, the polysilicon layer 22 is patterned using a lithography apparatus to form a first polysilicon pattern 24 having a critical line width of L1. The critical line width L1 of the first polysilicon pattern 24 is determined by the resolution of the lithographic apparatus used, and has a predetermined shape according to the pattern shape of the prepared photomask. For example, if a photolithography apparatus having a mask pattern having a line width of 500 nm and a resolution sufficient to form the same is prepared, the first polysilicon pattern 24 having a line width of 500 nm is formed.

Referring to FIG. 5, the first polysilicon pattern 24 is oxidized by a dry or wet oxidation method to form an oxide layer 28. In this case, the first polysilicon pattern 24 becomes the second polysilicon pattern 26 having L2 whose critical line width is smaller than L1. Oxidation conditions of the first polysilicon pattern 24 are determined in consideration of the size of the fine contact to be formed. In order to determine the oxidation conditions, an accurate oxidation rate of the first polysilicon pattern 24 is secured in advance. The conditions of the oxidation process are determined from the secured oxidation rate of the first polysilicon pattern 24 and the size of the fine contact to be formed.

Referring to FIG. 6, the oxide layer 28 formed on the first polysilicon pattern 26 is removed through a wet etching process using an aqueous hydrogen fluoride (HF) solution. Through this wet etching process, all of the oxide layer 28 formed on the surface and both side walls of the second polysilicon pattern 26 is removed. Of course, some of the sacrificial oxide layer 20 present in portions other than the second polysilicon pattern 26 may be removed. As a result, after the oxide layer 28 is removed, a second polysilicon pattern 26 having a critical line width of L2 is formed. The critical line width of the second polysilicon pattern 26 theoretically determines the size of the fine contact formed according to this embodiment.

Subsequently, the sacrificial oxide layer 20 is etched using the second polysilicon pattern 26 as an etch mask to form the sacrificial oxide pattern 30. Since the etching process for forming the sacrificial oxide pattern 30 requires high etching anisotropy, a dry etching process is used. In addition, the wet etching process for a short time may be performed once more to accurately expose the interface between the sacrificial oxide layer 20 and the second insulating layer 18 existing thereunder. This is performed by using the etching selectivity in the wet etching process using the aqueous hydrogen fluoride solution between the sacrificial oxide layer 20 and the second insulating layer 18 present thereunder.

Referring to FIG. 7, the metal mask layer 32 is formed on the entire surface of the substrate 10 on which the sacrificial oxide pattern 30 and the second polysilicon pattern 26 are formed. The metal mask film 32 is formed on the second insulating layer 18 between the laminated structures. The method of forming the metal mask film 32 is formed by a method that is excellent in vapor deposition linearity of metal elements as much as possible. The reason is that the metal mask film 32 is deposited on the wall surface of the laminated structure of the sacrificial oxide pattern 30 and the second polysilicon pattern 26 so as not to cause problems in the subsequent lift-off process described in FIG. 1. . As described above with reference to FIG. 1, the metal mask layer 32 is formed using a material having sufficient chemical resistance to an aqueous hydrogen fluoride solution to be used in a subsequent lift-off process.

Referring to FIG. 8, the stacked structure of the sacrificial oxide pattern 30, the polysilicon pattern 26, and the metal mask layer 32 is removed by a lift-off process. The lift-off process is performed using an aqueous hydrogen fluoride solution. In other words, the lift-off process removes the pillar structure of the sacrificial oxide pattern 30 that is removable on the hydrogen fluoride solution, thereby collectively removing the stacked second polysilicon pattern 26 and the metal mask layer 32. It is a process.

The thickness of the sacrificial oxide pattern 30 needs to be thick enough, and the formation method of the metal mask film 32 needs to ensure good deposition straightness. As a result of performing the lift-off process, when the stacked structure including the sacrificial oxide pattern 30, the polysilicon pattern 26, and the metal mask layer 32 is removed, the micro holes 31 having a predetermined size on the substrate 10 are removed. A metal mask pattern 33 is formed. The size of the hole 31 is equal to the size of the fine contact formed in the subsequent process.

Referring to FIG. 9, the second insulating layer 18 is etched using the metal mask pattern 33 having the micro holes 31 as an etch mask. Since the etching process of the second insulating layer 18 requires high etching anisotropy, a dry etching process is used. When the process is completed, the metal contact pattern 33 is finally removed or, in some cases, the micro contact point is formed on the second insulating layer 18 using an etching condition in which the metal mask pattern 33 is removed during the etching process. 36 is formed.

The second insulating layer 18 electrically insulates the phase change layer (38 of FIG. 10) formed in a later process, the lower heating metal electrode layer 16, and the lower metal electrode layer 14. In addition, the second insulating layer 18 serves to thermally insulate each material by contacting the phase change layer 38 and the heat generating metal electrode layer 14 only in a small portion. In addition, the heat transfer characteristic of the second insulating layer 18 has a very important influence on the operating characteristics of the phase change memory device, so it is necessary to pay attention to the material selection. In the present embodiment, as described above, the second insulating layer 18 is formed of a nitride film.

The size of the fine contact 36 formed in this embodiment can theoretically be reduced to about tens of nanometers. That is, the size of the fine contact 36 may vary depending on the process resolution and the degree of control of the oxidation process of the first polysilicon pattern 24 when patterning the polysilicon layer 22 using lithography equipment.

In practice, it is very important to keep the size of the fine contact of the phase change memory device fabricated on a substrate having a constant size as uniform as possible, and the size of the fine contact is likely to be determined by this criterion. However, since the process methods provided in the present invention use only a reliable process in which sufficient technical records have already been accumulated, high uniformity can be obtained in comparison with the fine contact processing method using other methods proposed in the prior art.

Referring to FIG. 10, the metal mask pattern 33 is removed. Subsequently, the phase change layer 38 is formed on the second insulating layer 18 while the fine holes 36 are buried. The phase change layer 38 is the most important material constituting the phase change memory device.

The phase change layer 38 is composed of an alloy of chalcogenide-based metal elements. The phase change layer 38 has various phase change characteristics according to the constituent elements and the composition of the metal alloy, which plays a very important role in the operation of the phase change memory device. Typical examples of the chalcogenide-based metal elements constituting the phase change layer 38 are Ge, Se, Sb, Te, Sn, As, and the like, and the chalcogenide phase change material is formed by appropriate combination of these elements. Is formed. In addition, elements such as Ag, In, Bi, and Pb may be mixed in addition to the chalcogenide-based metal element to improve the characteristics of the phase change layer 38. As a widely used material in the application of the optical storage device, Ge ₂ Sb ₂ Te _{5 in} which Ge, Sb, and Te are combined at a ratio of 2: 2: ₅ is the most common, and this material is also used for the manufacture of phase change memory devices. Can be used. As the method of forming the phase change layer 38, a multi-element sputtering film formation method or a one-way electron beam deposition method may be used.

Next, a third insulating layer 40 having a contact hole 39 exposing an upper portion of the phase change layer 38 is formed on the phase change layer 38 and the second insulating layer 18. The third insulating layer 40 serves to electrically insulate the lower phase change layer 38 and the upper metal electrode 42 formed later. The third insulating layer 40 needs to be formed at the lowest possible temperature. This is because the oxidation of the phase change layer 38 is prevented and the process of forming the third insulating layer 40 should not significantly change the crystal state of the phase change layer 38.

Next, the contact hole 39 is filled with the upper metal electrode layer 42 on the third insulating layer 40 while being connected to the phase change layer 38. The upper metal electrode layer 42 serves as an upper terminal of the phase change memory device, and is formed of a low resistance metal film generally used like the lower metal electrode layer. However, in some cases, an extra metal layer having a property of preventing diffusion to improve contact characteristics between the upper metal electrode layer 42 and the phase change layer 38 and to prevent unnecessary reactions or movement of elements, which may occur at the interface, may be used. It may be inserted.

11 is a cross-sectional view illustrating a method of manufacturing a phase change memory device including a process of forming a fine contact according to another exemplary embodiment of the present invention. In Fig. 11, the same reference numerals as Figs. 2 to 10 denote the same members.

Specifically, the manufacturing method shown in FIGS. 2 to 9 is performed. Subsequently, after the metal mask pattern 33 is removed, the phase change layer 38 is formed only in the fine contact 36. In other words, the phase change layer 38 is formed to fill all of the fine contacts 36 formed in the second insulating layer 18 and is not formed on the second insulating layer 18.

 This minimizes the volume of the phase change layer constituting the stack structure of the phase change memory device, and simultaneously supplies all of the heat generated from the bottom heat generating metal electrode layer 14 to the phase change layer buried in the fine contact structure. Is to maximize. Such a structure can be achieved by a method utilizing chemical-mechanical planarization (CMP), which is generally used in semiconductor processes, under appropriate conditions.

An upper metal electrode layer 42 is formed on a portion of the phase change layer 38 and the second insulating layer 18. In this structure, as shown in FIG. 10, the upper metal electrode layer 42 is disposed directly on the phase change layer 38 without having to perform the process of forming the third insulating layer 40 on the phase change layer 38. It is also possible to manufacture a phase change memory device.

FIG. 12 is a photo illustrating fine contacts formed when a phase change memory device is manufactured according to the present invention.

Specifically, the photograph of the actual process presented shows the shape of the metal mask pattern in which the micro holes described in FIG. 8 are formed. The pattern size of the first polysilicon formed using the lithography process described in FIG. 4 was about 850 nm, and the lithography equipment used used an i-line light source. As a result of applying the embodiment of the method for forming a fine contact according to the present invention, it is possible to form a fine contact of about 500 nm.

This is a result showing that the method for forming a fine contact according to the present invention can be sufficiently utilized in the actual process. Of course, the microcontact made using the method for forming a microcontact according to the present invention referenced in Figure 12 is not formed to a sufficiently small size as required by the present invention. However, this is a result showing that the method for forming a fine contact according to the present invention can be fully utilized in the actual process, and that the fine contact having a smaller size can be processed by applying the embodiment of the present invention by optimizing each process condition. The result is proof.

As described above, the present invention can form the fine contact of the phase change memory device through the semiconductor process to be lower than the resolution of the equipment while using the process equipment for photolithography.

According to the present invention, by using a fine contact forming process for manufacturing a phase change memory device, it is possible to effectively form a fine contact of a phase change memory device having a predetermined size without being limited to the resolution limitation of the lithography apparatus. As a result, the present invention can greatly reduce the power consumption of the phase change memory device.

The present invention provides a process for forming a contact having a fine size beyond the resolution guaranteed by the lithography process using a conventional lithography process. Accordingly, it is possible to manufacture a low power consumption type high density phase change memory device using the fine contact forming process according to the present invention.

Claims (7)

A first insulating layer on the semiconductor substrate. A lower metal electrode layer, a heat generating metal electrode layer, and a second insulating layer. Sequentially forming a sacrificial oxide layer and a polysilicon layer; Patterning the polysilicon layer to form a first polysilicon pattern having a critical line width of L1; Oxidizing the first polysilicon pattern to form a second polysilicon pattern having a critical line width L2 less than L1; Etching the sacrificial oxide layer using the second polysilicon pattern as an etch mask to form a sacrificial oxide pattern; Forming a metal mask film on the second insulating layer between the laminated structure of the second polysilicon pattern and the sacrificial oxide pattern; Removing the sacrificial oxide pattern and the second polysilicon pattern to form a metal mask pattern having micro holes; Etching the second insulating layer using the metal mask pattern having the micro holes as an etching mask to form a fine contact point; And And removing the metal mask pattern. The method of claim 1, wherein the forming of the second polysilicon pattern comprises: And oxidizing the first polysilicon pattern to form an oxide layer, and removing the oxide layer. The method of claim 1, wherein a metal mask layer is formed on the second polysilicon pattern, and the sacrificial oxide pattern and the second polysilicon pattern are removed by a lift-off method. . The method of claim 1, wherein the second insulating layer is formed of a nitride film. The method of claim 1, wherein the microcontact point is determined according to an oxidation amount of the first polysilicon pattern. The method of claim 1, wherein after the forming of the fine contact, Forming a phase change layer on the fine contact point, forming a third insulating layer having a contact hole to open the phase change layer, and an upper metal electrode layer formed on the contact hole and in contact with the phase change layer A method of manufacturing a phase change memory device, characterized in that it comprises a step of forming. The method of claim 1, wherein after the forming of the fine contact, Forming a phase change layer buried in the fine contact, and forming an upper metal electrode layer connected to the phase change layer on the phase change layer and the second insulating layer. Method of manufacturing a memory device.

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