KR20060068990A - Method of using serialize processing in digital multimedia broadcasting a receiving set - Google Patents

Abstract

The present invention provides a method of controlling a memory of a serialization block in a forward error correction encoding unit, the method comprising: determining a size of a memory for storing each channel data to control each channel memory in the serialization block; Storing each channel data value in the sized memory; Determining the memory of the channel data to be read first by comparing the transmission rate of the channel data among the memories in which the channel data values are stored; Comparing the address value of the channel data by calculating a difference between a storage address and a read address when the memory of the channel data to be read first is determined; A serial processing method of a digital multimedia broadcasting receiver comprising determining whether to read a memory based on the address value of the compared channel data.

Therefore, according to the present invention, even when the transfer rate is different for each memory, it is possible to control and serialize it.

Forward Error Correction Coder, Serialization Block, Control Unit, Memory

Description

Method of using serialize processing in Digital Multimedia Broadcasting a receiving set}

1 is a block diagram of a digital multimedia broadcasting receiver including the present invention.

2 is a block diagram showing a configuration of a forward error correction coding unit according to the present invention.

3 is a block diagram showing a configuration of a serialization block according to the present invention.

4 is a flowchart illustrating a process of reading a memory according to the present invention.

5 is a diagram illustrating an interface with an A / V data decoder according to the present invention.

* Explanation of symbols for the main parts of the drawings

200: forward error correction encoder 210: time inverse interleaver

220: Viterbi decoder 230: byte reverse interleaver

240: serialization block 250: RS decoder

260: byte / bit converter 270: A / V data decoder

300: control unit 310: memory

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a forward error correction encoder in a digital multimedia broadcasting receiver, and more particularly, to a method of controlling each channel memory in a serialization block of forward error correction encoding according to various transmission rates.

Digital multimedia broadcasting can be classified into terrestrial digital multimedia broadcasting and satellite digital multimedia broadcasting.

Terrestrial digital multimedia broadcasting provides audio and video services while moving based on Orthogonal Frequency Division Multiplexing (OFDM).

The satellite digital multimedia broadcasting is based on CDM (Code Division Multiplexing), which uses a ground gap filler, which is a repeater used to solve a satellite and a shadow area that cannot receive radio waves directly from the satellite. To enable audio and video services on the go.

At present, the technology of the satellite digital multimedia broadcasting basically adopts a CDM transmission method, and is a new concept service of communication and broadcasting convergence, which broadcasts weather, traffic, and video information using CD (Compact Disk) level sound quality and various channels.

Of these digital multimedia broadcastings, the satellite digital multimedia broadcasting has a broad coverage as a national broadcasting, but the transmission channel is a wireless mobile receiving channel, and the size of the received signal is not only time-varying, but also due to the influence of mobile receiving. Doppler shift of the received signal spectrum occurs.

In consideration of the transmission and reception in such a channel environment, the satellite digital multimedia broadcasting transmission method adopts the CDM method, and interleaves the time domain signals to correct errors occurring in the transmission channel.

The interleaved channel data is deinterleaved by the forward error correction encoder in the receiving apparatus to enter the A / V data decoder to be displayed. In order to enter the A / V data decoder, the interleaved channel data is serialized. We propose a control method for memory.

SUMMARY OF THE INVENTION The present invention has been made in view of the above, and an object of the present invention is to provide a method for controlling each channel memory in a serialized block of a forward error correction encoder according to various data rates.

In order to achieve the above object, the present invention comprises the steps of determining the size of the memory for storing each channel data, in order to control each channel memory in the serialization block; Storing each channel data value in the sized memory; Determining the memory of the channel data to be read first by comparing the transmission rate of the channel data among the memories in which the channel data values are stored; Comparing the address value of the channel data by calculating a difference between a storage address and a read address when the memory of the channel data to be read first is determined; In the digital multimedia broadcasting receiver comprising the step of determining whether to read the memory by the address value of the compared channel data provides a serialization processing method.

In the determining of the size of the memory, the size of memory required for each channel data is N times 204 bytes.

The determining of the memory of the channel data to be read first may include indicating that the memory of the data of the channel having the largest transfer rate is the memory to be read first.

Comparing the address value of the channel data, characterized in that the least common multiple of the transmission rate as a reference of the packet in order to equal the denominator of the transmission rate of each given channel data for comparing the write address and the read address.

When the compared address value is one packet size or more, the process proceeds to the next step.

The determining of whether to read the memory may include a vector table to determine whether the memory is read or not.

If the value of the vector table is not null (N), the current memory is read. If the value of the vector table is null (N), one packet is waited for the length to be processed.

The memory control method is characterized by repeating the above process for the memory of each channel.

In addition, the terminology used in the present invention is a general term that is currently widely used as possible, but in certain cases, the term is arbitrarily selected by the applicant, and in this case, since the meaning is described in detail in the corresponding part of the present invention, a simple term It is to be clear that the present invention is to be understood as a meaning of terms rather than names.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

First, Figure 1 is a block diagram showing a schematic configuration of a digital multimedia broadcasting receiving apparatus including the present invention.

Looking at the receiving process of the receiving device, the received signal input to the antenna is converted to the baseband (Baseband) in the tuner 100, the converted signal is a constant size of the signal input to the A / D (120) In order to maintain the signal, the A / D 120 is converted into a digital signal via an automatic gain control unit 110 that measures the power of the received signal and multiplies the calculated gain value.

In order to demodulate the signal in the CDM transmission method, the converted signal must capture a pseudo-noise sequence (PN) used for signal spreading. The searcher 130 enters a SEARCHER 130 functioning to secure within / 2 chips, and the signal found in the searcher 130 enters a tracker 141 to 14n that finely synchronizes signals. The process performed by the tracker is called signal tracking.

In the above description, the chip refers to a division unit of the pseudonoise sequence PN.

In this way, the signal that is captured and tracked and synchronized is despread by multiplying the pseudonoise sequence (PN) generated by the receiver, and the symbol of the desired CDM channel is extracted by multiplying the WALSH code used to distinguish the CDM channels. 151-15n). This process is performed in all the multiple paths searched by the searcher 130, and each is called a finger.

Here, the frequency offset estimator 195 estimates the frequency offset for each finger, synthesizes it, and feeds back the tuner 100 to correct the frequency offset.

The RAKE synthesizer 160 synthesizes the extracted symbols by multiplying the WALSH codes. Rake synthesis is performed on all CDM channels for demodulation. The synthesized symbols extract the timing of the frame and superframe using the pilot channel in the timing extraction circuit 170 of the frame and the superframe.

In this way, the signal sent from the rake synthesizer 160 enters the forward error correction encoder 200, which is a part corresponding to the present invention, and the forward error correction encoder 200 receives one pilot channel and four channel data. Receive and correct the error.

The pilot channel includes a code for decompressing channel data, and the four channel data are detected by the data mode detector 170 and the time inverse interleaver 210 and the Viterbi decoder 220 in the forward error correction encoder 200. ), Enter serialization block 240, RS decoder 250, byte / bit converter 260 and decode it using a pilot channel to be displayed via A / V data decoder 270.

2 is a block diagram illustrating a structure of a forward error correction encoder 200 including the present invention.

The forward error correction encoder 200 includes a time deinterleaver 210, a Viterbi decoder 220, a byte deinterleaver 230, and a serialization block. (Serialize block) 240, an RS decoder (Reed-Solomon decoder) 250, a byte / bit converter (Byte / Bit converter) (260).

The time reverse interleaver 210 performs reverse interleaving on a bit basis at the receiving end to interleave bit by bit at the transmitting end so as to correct an error that may occur in the transmission process.

The Viterbi decoder 220 performs Viterbi decoding of the time deinterleaved signal. The Viterbi decoder 220 generates a new bit pattern by forming a relational expression using several bits preceding the current bit to generate a new bit pattern. Even if an error occurs, a method of detecting and correcting a bit having an error by examining the preceding bit is called convolutional coding. The Viterbi decoder decodes the convolutional coded signal.

The byte deinterleaver 230 may deinterleave it in byte units after the Viterbi decoding. In this way, the signal interleaved and transmitted by the transmitting end is deinterleaved by bit unit and byte unit through the above-described process.

The serialization block 240 transmits a channel transmitted in parallel through the byte deinterleaver 230 as a single channel for each packet, which is placed in front of the RS decoder 250 and the RS decoder 250. It is characterized by the role of the interface to share.

When the RS decoder 250 transmits data and parity bits in a manner of adding a redundant parity by cutting a channel that is input through the serialization block 240 into a predetermined length, the receiving side reports each data and parity, By checking the presence or absence of the error correction method, the cluster error of the byte deinterleaved channel is corrected.

The byte / bit converter 260 finally transmits the coarse channel to the RS decoder 250 to the A / V data decoder 270 to receive only the channel in bits for display. ) Is a converter that converts channels in bytes into channels in bits for the interface with).

3 is a block diagram showing the configuration of a serialization block 240 according to the present invention, the serialization block 240 is composed of a control unit 300 and a memory 310.

The controller 300 performs a role of controlling the memory 310 in order to serialize a signal coming in parallel through the byte deinterleaver 230.

The memory 310 exists for each channel, and performs a role of storing channel data in order to serially process channel data coming in parallel through the byte deinterleaver 230, and in the memory 310, 1 per channel. There are two memories, each having a transfer rate per memory 310.

In the digital multimedia broadcasting receiver currently under development, the respective transmission rates are 1/2, 2/3, 3/4, 5/6, and 7/8. Currently, only the transmission rates of 1/2 are used. There is no need to control 310 separately.

However, if the transfer rate is different for each memory 310, there is a need to control this, the present invention proposes a method that can be controlled even if each transfer rate is different for each memory (310).

As described above, the data rate of each channel may be different, and information about the rate of each channel is transmitted to the pilot channel.

Since the data rate may be different for each channel, an appropriate memory 310 control method is required to convert the values transmitted in parallel to the serialized manner as required by the A / V data decoder 270.

Since the RS decoder 150 of the digital multimedia broadcasting receiver currently being developed uses 204 and 188 bytes per packet, the size of one packet is 204 bytes. Thus, a memory for storing one channel data value ( The size of 310 is determined by N times 204 bytes.

Here, the largest transfer rate of 7/8 and the smallest transfer rate of 1/2 differ in the transfer rate, which is about twice the size of the memory 310 required per channel data in order to serialize and process channel data values simultaneously input in parallel. Is determined by N times 204 bytes.

However, preferably three times 204 bytes is suitable and most efficient.

The transmission rate different from the above means that the write speed is different for each channel from the viewpoint of the memory 310, and the serial processing means that the read speed is the same for each channel. Therefore, the read speed has an operating speed that is many times as many as the channel than the write speed.

As described above, in order to read data transmitted at different data rates of 1/2, 2/3, 3/4, 5/6, and 7/8 in channel order, the following vector table is processed. .

Vector table based on bit rate

1/2 One 0 One 0 One 0 One 0 One 0 One 0 One 0 One ... 0 One 0 2/3 One One 0 One One 0 One One 0 One One 0 One One 0 ... One One 0 3/4 One One One 0 One One One 0 One One One 0 One One One ... One One 0 5/6 One One One One One 0 One One One One One 0 One One One ... One One 0 7/8 One One One One One One One 0 One One One One One One One ... One One 0

In the above vector table, if the least common multiple of 2, 3, 4, 6, and 8 is obtained so that the 5 transmission rates are the same, the common denominator is 24. If the transmission rate is obtained again, the 12/24, 16 / 24, 18/24, 20/24, 21/24.

This means that based on 24 packets, 12, 16, 18, 20, and 21 packets are transmitted, respectively. Therefore, based on 24 packets, the vector table is determined by arranging the positions of null packets for each transmission rate, and one packet is not read at a position determined as null ('0'). After waiting as long as the length of the next to read the value of the memory 310 that stores the channel data.

If the value is '1' in the vector table, this indicates that the memory 310 can be read. If the value is '0', the memory 310 waits until one packet is processed without reading the memory 310 and then waits for the next memory ( 310) should be read.

The present invention uses the vector table as above to control the memory 310 in the serialization block 240 above.

Referring to the method of controlling the memory 310, FIG. 4 is a flowchart illustrating a process of reading the memory 310 according to the present invention.

First, step S10 determines the memory 310 to be read by the control unit 300.

In order to determine the memory 310, the controller 300 determines that the memory 310 reads the memory 310 of the channel having the largest transmission rate with the information on the transmission rate of each channel sent from the pilot channel.

In operation S20, the controller 300 calculates and compares a difference between the determined write address and the read address of the memory 310.

In step S30, the difference between the write address and the read address is compared. If the comparison value does not exceed the size of one packet, the process returns to step S20, and if the comparison value becomes the size of one packet or more, Now move on to the next step.

In step S40, the vector table is read.

In step S50 it is determined whether the read vector table value is null (hereinafter 'null').

In step S60, if the read vector table value is not null, the current memory 310 is read, and then the process returns to step S20 to read the next memory 310.

In step S70, if the read vector table value is null, the controller 300 waits for one packet processing length, and then returns to step S10 to read the next memory 310.

In this way, the control of the memory 310 in the control unit 300 with respect to one channel data is finished.

The above-described process is performed for each channel. In the determining of the memory 310, the order of reading the memory 310 is determined. First, the channel memory 310 having the largest transfer rate is determined and the next size is determined. The memory is read in the order of the memory 310 having the transfer rate, and the process of reading the memory 310 is repeated for each memory 310 from step S20 to step S60.

Then, serialization is performed for each channel through the above-described processes.

In the above-described process, the control unit 300 controls the memory 310 of each channel in the serialization block 240.

Thus, this controlled serialized channel data value enters the RS decoder 250 for error correction and then enters the A / V data decoder 270 via the byte / bit converter 260 for display.

5 is a diagram illustrating a signal flow for interfacing with the A / V decoder.

Through the above-described process, each channel data enters and displays the A / V data decoder 270 through the RS decoder 250 and the byte / bit converter 260 as the signal as shown in FIG. 5.

As described above, one packet becomes 1632 bits as 204 x 8, of which 188 x 8 = 1504 bits have channel data and the remaining 128 bits are used as a signal for distinguishing channel data.

The present invention is not limited to the above-described embodiments, and as can be seen in the appended claims, modifications can be made by those skilled in the art to which the invention pertains, and such modifications are within the scope of the present invention.

At present, satellite digital multimedia broadcasting transmits only one-half of all channels, and a memory control method is simple. However, in the future, it is determined that transmission can be performed at various transmission rates for each channel memory, and there is also a possibility of transmission at a higher transmission rate in order to improve the service in the future. I need a way to deliver it.

Therefore, the present invention proposes a method of controlling a memory when the transmission rate of each channel is different, so that the A / V data decoder can process the data even if there is a change in the transmission rate.

Claims (8)

To control each channel memory in the serialization block, Determining a size of the memory for storing each channel data; Storing each channel data value in the sized memory; Determining the memory of the channel data to be read first by comparing the transmission rate of the channel data among the memories in which the channel data values are stored; Comparing the address value of the channel data by calculating a difference between a storage address and a read address when the memory of the channel data to be read first is determined; And determining whether to read a memory by using the address values of the compared channel data. The method of claim 1, wherein the determining of the size of the memory comprises: And a memory size required for each channel data is N times 204 bytes. The method of claim 1, wherein the determining of the memory of the channel data to be read first, A method for serializing a digital multimedia broadcasting receiver, characterized in that the memory of the data of the channel having the largest data rate is the first memory to be read. The method of claim 1, wherein the comparing of the address values of the channel data comprises: And a least common multiple of the transmission rate as a reference for the packet so that the denominator of the transmission rate of each given channel data is compared to compare the write address and the read address. The method of claim 4, wherein And proceeding to the next step if the compared address value is larger than one packet size. The method of claim 1, wherein determining whether to read the memory comprises: And a vector table to determine whether the memory is in a readable or non-readable stage. The method of claim 6, If the value of the vector table is not null (N), the current memory is read; if the value of the vector table is null (N), the serial processing method of the digital multimedia broadcasting receiver characterized in that the waiting for the length of one packet to be processed. . The method of claim 1, And the memory control method repeats the above process for the memory of each channel.

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