KR20060103719A - Method of memory control for bit-deinterleaving - Google Patents

Abstract

The present invention is to reduce the power consumption by controlling the clock of the memory for bit deinterleaving, the present invention is to serialize the bit deinterleaver and the memory in order to serialize the bit reverse interleaving for each channel, the reverse of each channel data A first step of determining whether the interleaving mode is the same; A second step of generating an address and a bit width of each channel data by the start data and the end data in an address generator generating an address of each channel data to read or write the memory when the deinterleaving mode is the same. It provides a method of processing in units of bytes, including. Therefore, according to the present invention, the clock speed of the memory can be lowered by adjusting each channel data, thereby reducing power consumption.

DMB, Bit Reverse Interleaver, SDRAM

Description

Method of Memory Control for Bit-Deinterleaving

1 is a conceptual block diagram of a digital multimedia broadcasting receiver including the present invention.

2 is a timing diagram showing an input waveform in a general bit deinterleaver

3 is a timing diagram showing an input waveform in the bit reverse interleaver according to the present invention.

* Explanation of symbols for the main parts of the drawings

19: bit reverse interleaver

The present invention relates to a digital multimedia broadcasting receiver, and more particularly, to a method for reducing power consumption of a memory (SDRAM) used for deinterleaving through generation of a byte address in a bit deinterleaver in a forward error correction coding unit.

Digital multimedia broadcasting can be classified into terrestrial digital multimedia broadcasting and satellite digital multimedia broadcasting.

The terrestrial digital multimedia broadcasting provides audio and video services during movement based on an orthogonal frequency division multiplexing (OFDM) scheme.

The satellite digital multimedia broadcasting is based on the CDM (Code Division Multiplexing) method and uses a Gap Filler on the ground, which is a repeater used to solve the satellite and the shadow area that is not directly received by the satellite. To enable audio and video services on the go.

Currently, the technical standard of satellite digital multimedia broadcasting adopted in Korea and Japan is the System-E method defined by ITU, which basically adopts CDM transmission method, and uses CD (Compact Disk) quality and weather, traffic, and video using various channels. It provides new concept services of representative communication and broadcasting convergence that broadcast information.

The satellite digital multimedia broadcasting uses frequencies in the uplink 13.824 ~ 18.883 GHz band, the downlink 2.630 ~ 2.655 GHz, and the 12.21 ~ 12.23 GHz band, and Korea and Japan support up to 64 channels using 32 channels, respectively.

In addition, the satellite digital multimedia broadcasting has a wide coverage as a national broadcast, but the transmission channel is a wireless mobile reception channel, the size of the received signal is not only time-varying, but also the reception signal due to the influence of the mobile reception Doppler shift of the spectrum occurs.

In consideration of the transmission and reception under such a channel environment, the satellite digital multimedia broadcasting adopts the CDM method as a transmission method, and may correct an error occurring in a transmission channel by interleaving a time domain signal. It was.

The CDM method multiplies the data to be transmitted by a pseudo noise signal having a data rate much faster than that of the data, thereby spreading and transmitting the data by narrowing the narrow-band signal interference. There is a strong characteristic against interference, and it is possible to reduce deterioration of reception performance due to multiple paths through a receiver having a RAKE structure.

However, since the pilot channel, which is a control channel, contains information on interleaver size and convolutional coding rate, it must be demodulated.

The Forward Error Correction unit for decoding the pilot channel has a clock speed of 4.096 MHz after passing the input I, Q serialization and four-channel serialization, so that it is read / write from the SDRAM. In order to perform (Read / Write), a clock of 32.768 MHz or more must be used as an operation clock of the SDRAM.

Therefore, in the satellite digital multimedia broadcasting system, which is applied to a portable terminal having high personal mobility, the power consumption is an important issue, the frequency of the operation clock of the SDRAM is high, which causes a lot of power consumption.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to reduce the speed of an operation clock by 1 / N times at the time of interface with a memory in a bit deinterleaver in a digital multimedia broadcasting receiver. To reduce power consumption.

In order to achieve the above object, in the memory control method for bit deinterleaving according to the present invention, in order to interface with the bit deinterleaver and the memory for serialized bit deinterleaving for each channel, the deinterleaving mode of each channel data Determining whether is equal to; A second step of generating an address and a bit width of each channel data by the start data and the end data in an address generator that generates an address of each channel data to read or write the memory when the deinterleaving mode is the same. It characterized in that the processing by byte unit.

In this case, in the second step, when the reverse interleaving mode is different, it is preferable to perform bit reverse interleaving for each channel.

The second step may be processed in units of bytes through the address generator regardless of the number of channels.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described.

The same components as in the prior art are given the same names and the same reference numerals for convenience of description, and detailed description thereof will be omitted.

In addition, the term used in the present invention was selected as a general term widely used as possible now, but in some cases, the term is arbitrarily selected by the applicant, in which case the meaning is described in detail in the description of the invention, the simple term It is to be clear that the present invention is to be understood as a meaning of terms rather than names.

The operation of the memory for the bit deinterleaver according to the present invention configured as described above will be described in detail with reference to the accompanying drawings. At this time, the memory for the bit reverse interleaver of the present invention will be described as an example of the SDRAM.

1 is a conceptual block diagram of a digital multimedia broadcasting receiver according to the present invention.

Looking at the receiving process of the receiving device, the received signal input to the antenna is converted into a baseband (tuner band) in the tuner 10, the converted signal is maintained at a constant size of the signal to the A / D 12 For this purpose, the A / D 12 is converted into a digital signal through an automatic gain control unit 11 which measures the power of the received signal and multiplies the calculated gain value.

In this case, in order to demodulate a signal in the CDM transmission scheme, the acquisition of a pseudo-noise sequence used for signal spreading should be prioritized. This process involves two steps of acquisition and tracking of a signal. Is made of.

The division unit of the pseudo-noise sequence is called a chip, and the signal acquisition is a process of securing signal synchronization within 1/2 chip at a receiver, and is performed by a searcher 13. In addition, the signal tracking refers to fine synchronization of the found signal and is performed in the trackers 141 to 14n.

In this way, the synchronized signal is despread by multiplying the pseudonoise sequences generated by the receiver through the despreaders 151 to 15n, and extracting the desired CDM channel symbols by multiplying the WALSH codes used to distinguish the CDM channels. do.

This process is performed in all the multiple paths searched by the searcher 13, each called a finger.

In this case, the frequency offset estimator 27 estimates the frequency offset for each finger, synthesizes it, and then feeds back the tuner to correct the frequency offset.

The extracted symbols are synthesized by the rake synthesizer 16. In this case, a method of improving reception performance may be obtained by estimating and compensating a reception channel environment.

In this case, the rake synthesis in the rake synthesizer 16 is performed for all CDM channels to be demodulated, and then the pilot decoding consists of a pilot Viterbi decoder 18, a pilot deinterleaving 20, and a pilot RS decoder 22. The grandfather 30 extracts and decodes the pilot signal.

A forward error correction coder 40 composed of a bit deinterleaver 19, a Viterbi decoder 21, a byte deinterleaver 23, and an RS decoder 25 is passed through the data mode detector 24. To correct any errors in the data. The error corrected data in the forward error correction encoder 40 is decoded through the A / V data decoder 26 and output.

In this case, satellite digital multimedia broadcasting is a CDMA-based system in which several data channels are received in parallel in time. Accordingly, the bit deinterleaver 19 is positioned at the front end of the forward error correction encoding unit 40 for error correction robust to burst errors of the wireless channel.

Hereinafter, the bit deinterleaver 19 currently used in the satellite digital multimedia broadcasting system will be described.

The process of performing bit deinterleaving in the conventional satellite digital multimedia broadcasting system will be described. In the past, four channel input types into the forward error correction encoder were time-domain multiplexed (TDM).

That is, as defined in the satellite digital multimedia broadcasting standard, the data rate per channel operates at 256 Kbps, that is, 256 KHz. However, due to the offset, etc., it actually operates at 512 KHz inside the system.

When I and Q serialize the data again, the data input to the forward error correction encoder has a clock speed of 1.024 MHz.

That is, the clock speed required for decoding one channel is 1.024 MHz, and since the four channels are serialized and decoded simultaneously in the forward error correction coding unit, the required clock speed is increased to 4.096 MHz.

At this time, when reading / writing to a memory interfacing with the bit deinterleaver in order to bit deinterleave one channel, the clock speed needs to be at least 8 times the clock speed of the currently operating data.

That is, since the clock speed of the data after passing the I, Q serialization and 4-channel serialization input to the forward error correction coding unit is 4.096 MHz, a clock of 32.768 MHz or more is required to read / write the memory in SDRAM. It should be used as the operating clock of.

Compared to the static random access memory (SRAM), the SDRAM stores more data, supports a higher clock speed, and needs to be periodically refreshed due to the characteristics of the dynamic random access memory (DRAM). This eventually causes more power consumption than SRAM.

Since the satellite digital multimedia broadcasting system is applied to a portable terminal with strong personal mobility, the reduction of power consumption becomes an important issue in the system implementation.

Therefore, it is necessary to lower the clock speed used for the SDRAM in order to reduce the power consumption as described above.

In this case, bit deinterleaving is performed separately for each channel through channel serialization, and the process of reading / writing to the SDRAM has the same clock speed. Therefore, in order to reduce the clock speed by adjusting the address and bit width of data for each channel by combining several channels together, an address generator generates a byte address and treats it as one data so that the clock speed can be reduced much compared with the conventional method. You can expect the effect.

That is, as described above, although the direct clock speed of the SDRAM cannot be reduced, the clock speed of the SDRAM only needs to be 8 times larger than the data clock in order to reduce the clock speed. Likewise, by processing the data in bytes, the clock speed of the data is lowered to reduce the clock speed of the SDRAM.

That is, a method of lowering the clock speed of the data is used as a method of reducing power consumption by lowering the clock speed of the SDRAM.

To see this, first, the operation of the bit deinterleaver will be described. FIG. 2 is a timing diagram illustrating an input waveform of a general bit deinterleaver 19.

As shown in FIG. 2, the input waveform of the bit deinterleaver 19 is input after serializing for each channel.

Therefore, the data of FIG. 2 is addressed in the order of start data and end data for each channel, so that the clock speed of the SDRAM can be increased by the number of channels.

Referring now to the operation of the bit deinterleaver in the present invention, FIG. 3 is a timing diagram showing the input waveform of the bit deinterleaver 19 according to the present invention.

Referring to FIG. 3, as described above, the SDRAM should have a clock speed of at least eight times that of the data clock speed. At this time, since it is difficult to lower the direct clock speed of the SDRAM, as described above, in order to lower the clock speed of the relative SDRAM and the data as a whole, a method of lowering the clock speed of the SDRAM in proportion to the data clock speed by reducing the clock speed of the data is provided. I would like to.

That is, in the interface with the SDRAM for bit deinterleaving in the bit deinterleaver 19, the address and the bit of each data in the address generator for generating the address of the data for reading / writing in the SDRAM By adjusting the bit width, the start data is combined with the start data and the end data is combined with the end data to generate a single byte address, thereby addressing the data in byte units, thereby reducing the clock speed of the data.

4 illustrates an example in which an input waveform is generated for each start data and end data by tying the four clock channels together.

By using the above-described method, the clock speed of data for one channel in FIG. 2 was 4.096 MHz. According to the present invention, the clock speed of data drops to 1.024 MHz.

Therefore, when performing the data read / write process of reducing the data clock rate for one channel in the SDRAM using the method according to the present invention, 8 times of the data clock, that is, 8.192 MHz is required. This significantly reduces the clock speed in SDRAM compared to 32.768 MHz, which in turn reduces the system's power consumption.

At this time, the processing of the channels at once by combining the start data and the end data at the byte unit requires the assumption that each channel has the same reverse interleaving mode. This is because the address generator can generate an address in consideration of the address and bit width of each data for byte unit processing.

However, if the deinterleaving mode is different from each other, since the address for each channel is different, the above method cannot be applied.

However, in the standard of the satellite digital multimedia broadcasting system that is actually being serviced, since the inverse interleaving mode of all the channels is fixed and used, the present invention can be applied and thus 1 / N times (where N is the number of channels). It can have a clock speed of.

Therefore, bit deinterleaving can be flexibly applied according to the channel condition being actually broadcasted.

That is, when the deinterleaving mode of each channel is different as a result of decoding by the data mode detector 24, since the address of each channel is different, bit deinterleaving is performed for each channel as in the case of the related art. If the reverse interleaving mode of each channel is the same, the address is the same for each channel, so if only the bit width of the data is adjusted, all the channels can be bundled and processed as byte data as one data. The clock speed to run the SDRAM can be reduced, which in turn will reduce power consumption in the overall digital multimedia broadcasting system.

Currently, the number of channels is defined as four channels in the digital multimedia broadcasting system. However, the number of channels may increase depending on the future situation.

Thus, the present invention is not necessarily applied only when the four channels are decoded, but can be extended by using the basic concept of the present invention even when the number of channels increases.

For example, a case may be considered in which the number of channels extends to 8 or 16 channels. In the case of four channels, if the soft bit is used as four bits, one data processing unit becomes 16 bits.

That is, the clock speed is lowered because it can be converted from processing four 4-bit data to processing one 16-bit data.

When the number of channels is extended to eight channels, the processing can be changed from processing eight 4-bit data to processing one 32-bit data, and in the case of 16 channels, 16 four-bit data is processed. Since it can be converted from processing one 64-bit data, this method can be easily extended and applied even if there are four or more channels without any modification.

At this time, even if the number of channels to be decoded increases, the clock speeds are all constant. That is, since the clock rate of the original symbol is 1.024 MHz, even if the increase in the case of 8 channels and 16 channels, there is an advantage that the same can be processed to 8.192 MHz.

Rather, as the number of channels increases, the efficiency of the present invention becomes higher.

Referring to the effects of the bit deinterleaver memory according to the present invention described above, according to the present invention, even if the number of channels increases in the digital multimedia broadcasting system, the power consumption can be reduced.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (3)

In the interface of the bit deinterleaver and the memory to serialize bit by bit deinterleaving for each channel, A first step of determining whether the deinterleaving mode of each channel data is the same; A second step of generating an address and a bit width of each channel data by the start data and the end data in an address generator generating an address of each channel data to read or write the memory when the deinterleaving mode is the same. The memory clock control method for bit deinterleaving, characterized in that for processing by byte unit. The method of claim 1, wherein in the second step, And if the reverse interleaving mode is different, performing bit reverse interleaving for each channel. The method of claim 1, wherein the second step is The memory clock control method for bit deinterleaving, characterized in that the processing can be performed in units of bytes through the address generator regardless of the number of channels.

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