KR20060057215A - Method of de-interleaving in digital receiver - Google Patents

Abstract

The present invention relates to a method for deinterleaving a digital receiver. The present invention provides a method of constructing an address matrix for deinterleaving by receiving an interleaving mode value, generating a read / write address of a memory through the configured address matrix, and data received in the memory according to the generated address. It provides a method of deinterleaving a digital receiver comprising the step of performing a read / write operation. Accordingly, it is possible to cope with various modes of the digital receiver and to enable bit deinterleaving through an address matrix.

Satellite DMB, Interleaved, Pilot Signal, Interleaved Mode

Description

Method of de-interleaving in digital receiver

1 is a conceptual diagram of a bit interleaver shown to explain the bit deinterleaving method according to the present invention.

2 is a diagram illustrating a bit interleaver and a bit deinterleaver shown for explaining a deinterleaving method according to the present invention.

3 is a diagram illustrating an interleaving size according to an interleaving mode shown to explain a deinterleaving method according to the present invention.

4 is a flow chart illustrating a deinterleaving algorithm according to the present invention.

5 is a flowchart illustrating a method of constructing an address matrix used in a deinterleaving algorithm according to the present invention.

6 is a diagram showing a configuration example of an actual address matrix according to the present invention;

7 is a block diagram schematically showing the overall configuration of a satellite DMB receiver according to the present invention.

-Explanation of symbols for the main parts of the drawings-

1: Tuner 5: A / D Converter

9: Tracker 15: Rake Synthesizer                 

25: data mode detector 27: bit reverse interleaver

35: A / V data decoder

The present invention relates to a deinterleaving method of a digital receiver, and more particularly, to a method of deinterleaving an interleaved transmitted signal among error correction encoding methods for more stable reception in a mobile reception environment.

Hereinafter, a satellite digital multimedia broadcasting (DMB) receiver using a CDM transmission method will be described.

The portion of the deinterleaving method for error correction in the satellite DMB receiver is not specified in the spec and is an implementation problem, so there is no specific prior art defined. Here, the satellite DMB receiver will be briefly described as follows.

Digitalization of broadcasts has made Digital Multimedia Broadcasting (DMB) possible, encompassing data transmission and multimedia services. The DMB is robust against noise and distortion on a transmission channel, has a high transmission efficiency and has an advantage of enabling a multimedia service.

The satellite DMB broadcasting adopted in Korea is based on the Japanese system E system and consists of a performance equipment, earth station, satellite, terrestrial relay equipment and subscriber receiver.

The satellite DMB broadcasting system transmits multimedia contents from the earth station transmission center to the satellite, and the user receives the data directly from the satellite or from a terrestrial auxiliary relay called a gap filter in a shaded area where the signal strength is weak. It will work.

In this case, the transmission channel of the satellite DMB is a wireless mobile reception channel, and the amplitude of the received signal is not only time-varying, but also the Doppler shift of the received signal spectrum occurs due to the mobile reception. .

Therefore, in consideration of the transmission and reception in such a channel environment, the satellite DMB transmission method adopts a code division multiplexing (CDM) transmission method.

The CDM transmission method is a method of multiplying a data to be transmitted by a pseudo noise signal having a data rate much faster than that of the data to spread and transmit the signal. band interface), and the receiver of the RAKE structure reduces the degradation of reception performance due to the multipath.

Satellite DMB using the CDM transmission method is a new concept service of convergence communication and broadcasting, which broadcasts weather, traffic, and video information using CD quality sound and various channels.

In such satellite DMB, an interleaving method is used to improve immunity from instantaneous noise. The interleaving refers to a process of mixing signals in a transmitter according to a predetermined rule, and de-interleaving refers to a process of rearranging the mixed signals in an original order in a receiver.

The reverse interleaving is performed at the Forward Error Correction (FEC) stage of the receiver. In particular, the bit reverse interleaver distributes the concatenation error and converts the error into a range of errors that can be corrected in the FEC system. Therefore, the development of bit deinterleaving method in satellite DMB is an important problem.

The present invention is to solve the above problems, and to propose an algorithm for performing bit deinterleaving corresponding to various modes according to the bit interleaver standard defined in the satellite DMB system.

In order to achieve the above object, the present invention comprises the steps of constructing an address matrix for deinterleaving by receiving an interleaving mode value, generating a read / write address of the memory through the configured address matrix, and the generated address According to the present invention, there is provided a method of deinterleaving a digital receiver, the method including performing a read / write operation of data received in a memory.

The address matrix constructing step includes constructing the first column of the matrix with values from 0 to (B-1) * N / 2, and multiplying the interleaved size by subtracting the column number configured from the branch number (B). Moving to the next column to form the next column, and repeating the step until the last row of the last column becomes zero.

Accordingly, according to the present invention, it is possible to cope with various modes of the satellite DMB receiver and to enable bit deinterleaving through an address matrix.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described.

In addition, the terminology used in the present invention was selected as a general term widely used as possible now, but in some cases, the term is arbitrarily selected by the applicant, in which case the meaning is described in detail in the corresponding description of the invention, The present invention is to be understood as the meaning of terms rather than names.

1 is a conceptual diagram of a bit interleaver shown for explaining a bit deinterleaving method according to the present invention.

As shown in FIG. 1, the bit interleaver defined in the satellite DMB standard adopts a partitioned convolutional interleaving method having a period of 51 in units of bits. That is, interleaving is performed bit by bit in a time delay manner with a period from 0 to 50.

In more detail, the first bit is output without delay in the data frame, and the next bit is delayed by 17 of the numbers 0 to 50 times the interleaved size (m). The next bit is delayed by 34 times the interleaved size (m), and the next bit is delayed by the interleaved size (m).                     

In this manner, the delayed outputs are arranged to have 51 cycles so that they are interleaved. Of course, the period is interleaved with time delay in units of bits even if the period is constantly arranged from 0 to 50, but the numbers from 0 to 50 are randomly arranged again to add the randomness.

The randomly arranged form is one of values that should be known to the transmitter and the receiver. The interleaving form and the reverse interleaving method according to the present invention will be described with reference to FIG. 2.

2 is a diagram illustrating a bit interleaver and a bit deinterleaver shown to explain a deinterleaving method according to the present invention.

As shown in FIG. 2, the interleaver having a period of 51 has 51 branches, and one branch is selected and delayed for each bit to be interleaved. In this case, the box of FIG. 2 illustrates a delay element. For example, in case of the branch 1, the box 1 is delayed by 17 by the interleave size (m). In this case, branch 0 is output without delay.

In more detail, the time delay relationship for interleaving will be described in detail. When the bit position of the delay amount is 0, the delay amount D of the bit in the n-th position can be calculated using the following equation.

D = 51 * (I + 17 * J) * m

In the above formula, I is an integer of 0 to 16, which is a value obtained by cutting off the decimal point of the quotient when n is divided by 51 and the remainder is divided by 3. J is the remainder of n divided by 3 and is an integer from 0 to 2.

Meanwhile, the interleave size m is shown in FIG. 3, and the interleave size is set differently according to each interleave mode as shown in FIG. 3. The interleave size of 654 is used as a default value.

Referring to the reverse interleaving relationship performed at the receiving end with respect to the interleaved data in this manner, it will be described below.

As shown in Fig. 2, the arrangement of the delay elements in the reverse interleaver is arranged in the reverse order of the delay elements arranged in the interleaver.

For example, the bit corresponding to the branch 0 in the interleaver is output without a delay. In the inverse interleaver, the branch 0 is delayed by 50 * m so that the delay amount is for convenience of explanation. The amount is the result calculated by Equation 1 described above). In addition, the bit corresponding to the branch 1 in the interleaver is output with a delay of 17 * m. In the inverse interleaver, the bit is delayed by 33 * m. As a result, the branch 0 and the branch 1 have 51 cycles and were arranged before being interleaved. Output in bit order.

For example, since the branch 2 of the interleaver is delayed by 34 * m and the branch 2 of the reverse interleaver is delayed by 16 * m, the bit output from the reverse interleaver is delayed to have 51 cycles.

Similarly, the delay elements of the interleaver or the reverse interleaver are arranged so that all 51 branches have the same period, so that the interleaved data is delayed for a certain time through the interleaver and outputted with the same period again through the reverse interleaver. The data before it is output through the reverse interleaver.

Referring to Figure 4 attached to the deinterleaving algorithm according to the present invention according to the interleaving and deinterleaving method as follows. For convenience of description, where more detailed explanation of the steps is required, it will be described with reference to the accompanying drawings again.

4 is a flowchart illustrating a deinterleaving algorithm according to the present invention.

As shown in FIG. 4, the inverse interleaver first receives an interleaving mode value to construct an address matrix for reverse interleaving of received data.

In this case, the interleaving mode value is shown in FIG. 3, and as shown in FIG. 3, an interleaved mode detection value corresponding to each interleave size (m) is present. m) can be known.

The address matrix constructed according to the interleaving mode value will be described with reference to FIG. 5.

5 is a flowchart illustrating a method of constructing an address matrix used in a deinterleaving algorithm according to the present invention.

As shown in FIG. 5, the address matrix constitutes the first column of the matrix with values from 0 to (B-1) * N / 2. (S10) In the above formula, B represents the number of branches. N is the branch multiplied by the interleave size (N = B * m)                     

The next column of the first column is constructed by shifting the interleaved size by subtracting the number of columns constructed from the branch number. (S20) (B- (configured column number)) * M) When constructing the second column of, it is configured by shifting the interleaved size by subtracting 1, which is the number of the first column of the branch.

Similarly, when configuring the next third column, the subtracted number, which is the number of the second column configured from the branch number, is moved by the number multiplied by the interleave size.

 The configuration of such a column is repeated until the value of the last row of the last column (B column) becomes 0. (S30) In this case, the address matrix of B * [(B-1) * N / 2] + 1 is repeated. It is composed.

The configuration of the actual address matrix according to the address matrix construction step according to the present invention is shown in FIG. 6.

The address matrix illustrated in FIG. 6 illustrates a case where B = 4, m = 2, and N = 8 for convenience of description.

As shown in FIG. 6, the first column in the address matrix is arranged from 0 to 12 according to the formula of step 10 (S10) in the flowchart of FIG. 5 (since B = 4 and N = 8). It is configured according to the formula of S20), so it can be seen that 0 is moved down 6 spaces in the column direction. Since the next column is moved by 4 according to the formula of step 20 (S20), 0 is moved in the column direction by 4 again. In the same way, when you construct the last column, the last row of the last column is zero and the address matrix is constructed.                     

On the other hand, after configuring the address matrix as in the present invention, the read / write address of the memory is generated again through the address matrix as shown in Figure 4 (S20).

That is, a write address (WA) is created while moving one column in each row of the address matrix, and a read address (RA) is created by moving the write address once.

Referring to the address matrix of FIG. 6 attached thereto, the write address is as follows.

0, 7, 3, 1, 1, 8, 4, 2, 2, 9, 5, 3, ..., 12, 6, 2, 0, 7, ..., (repeat)

In this case, since the read address is configured by moving the write address once, the read address is as follows.

X, 0, 7, 3, 1, 1, 8, 4, 2, 2, 9, 5, 3, ..., 12, 6, 2, 0, 7, ..., (repeat)

That is, it writes data to an address first, and then reads data from the same address on a clock.

As described above, when actual data is input after generating the read / write address, the read / write operation is executed in the memory using the generated address.

On the other hand, Figure 7 is a block diagram showing the overall configuration of the satellite DMB receiver in which the technical idea according to an embodiment of the present invention is implemented.

As shown in FIG. 7, the received signal input through the antenna is converted into a baseband signal through the tuner 1, and the magnitude of the signal is kept constant through the AGC (Automatic Gain Controller) unit 3. . A signal whose size is relatively constant by the AGC unit 3 is sampled by an A / D converter 5 and converted into a digital signal.

In the CDM transmission method, the acquisition of a pseudo-noise sequence used for spreading a signal should be prioritized. This process is divided into an acquisition and a tracking step.

Since the division unit of the pseudo noise sequence is called a chip, the acquisition is a process of securing signal synchronization within ± 1/2 chips at a receiver, and this process is performed by a searcher 7. The tracking of the signal finely synchronizes the captured signal, and is performed in the trackers 9 (1), ..., 9 (n).

The synchronized signal is then despread by multiplying the pseudo-noise sequences generated by the receiver in the PN despreading and WALSH despreading units 11 (1), ..., 11 (n), and used to distinguish the CDM channels. By multiplying the WALSH code, the symbol of the desired CDM channel is extracted.

This process is performed in all the multiple paths found in the searcher (7), each of which is called a finger.

Thereafter, the frequency offset estimator 13 estimates the frequency offset for each finger, synthesizes it, and feeds it back to the tuner 1 to correct the frequency offset.

The symbols extracted through this process are synthesized by the Rake synthesizer 15. In this case, a method of improving reception performance may be used by estimating and compensating a reception channel environment. The rake synthesis is performed for all CDM channels for which demodulation is desired.

Thereafter, the frame and super frame timing extracting circuit 17 extracts the timing of the frame and the super frame included in the pilot signal and specifies the start position of the channel decoding in the subsequent channel decoding process. It will play the role of matching.

The pilot channel, which is the control channel, is then demodulated through the corresponding building blocks, such as convolutional decoding and reverse interleaving. In particular, the data mode detector 25 obtains information on the interleaving mode according to the present invention and decodes the data channel. I use it.

On the other hand, the data channel performs deinterleaving in the bit deinterleaver 27 in the method according to the embodiment of the present invention. That is, an interleaving mode value detected by the data mode detector 25 is input to construct an address matrix, a read / write address of a memory is generated through the address matrix, and a read on the received data according to the generated address. / Deinterleaving by performing a write operation.

Thereafter, the bit deinterleaved data is convolutionally decoded through the corresponding construction block, and after RS deinterleaving again, RS decoded and A / V data decoded to display A / V data on a screen (not shown).

The present invention is not limited to the above-described embodiments, and as can be seen in the appended claims, modifications can be made by those skilled in the art to which the invention pertains, and such modifications are within the scope of the present invention.

The error correction encoding method according to the present invention described above can cope with various modes of a satellite DMB receiver and has an effect of enabling bit deinterleaving as a simple address generation algorithm.

Claims (4)

Receiving an interleaving mode value and constructing an address matrix for deinterleaving; Generating a read / write address of a memory through the configured address matrix; And, And performing a read / write operation of the data received in the memory according to the generated address. The method of claim 1, wherein the constructing the address matrix comprises: Constructing the first column of the matrix with values from 0 to (B-1) * N / 2, Constructing the next column by moving by the number obtained by subtracting the column number configured by the number of branches (B) by the interleave size And repeating the above steps until the last row of the last column becomes zero. The method of claim 1, And the read address is configured by shifting the write address by one clock. The method of claim 1, And the interleaving mode value is data included in a pilot channel of a received signal.

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