KR20060062919A - Semiconductor memory device - Google Patents

Abstract

The present invention discloses a semiconductor memory device. The semiconductor memory device is formed on at least one pad having a first conductive layer and a second conductive layer disposed on the first conductive layer and a semiconductor substrate under the at least one pad, and a first voltage is applied thereto. And a decoupling capacitor having a first active region, an insulating layer stacked on top of the first active region, and a third conductive layer stacked on top of the insulating layer, and to which a second voltage is applied. do.

Therefore, it is possible to provide a decoupling capacitor at the bottom of the pad by overcoming the stress in bonding in a limited area semiconductor memory device, thereby reducing the power noise generated when the semiconductor memory device is driven, thereby preventing malfunction of the device Will be able to improve.

Description

Semiconductor memory device

1 is a cross-sectional view showing the structure of a semiconductor pad according to the prior art.

2 is a cross-sectional view showing the structure of an embodiment of a semiconductor pad according to the present invention.

3 is a plan view illustrating a structure of the semiconductor substrate of FIG. 2.

4 is a cross-sectional view showing the structure of another embodiment of a semiconductor pad according to the present invention.

5 is a plan view illustrating a structure of the semiconductor substrate of FIG. 4.

6 is a cross-sectional view showing the structure of another embodiment of a semiconductor pad according to the present invention.

FIG. 7 is a plan view illustrating the structure of the gate poly of FIG. 6.

8 is a part of a cross-sectional view showing a structure of still other embodiments of a semiconductor pad according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor device having a pad capable of reducing power supply noise and bonding stress.

The pad of the semiconductor memory device is formed to have a function of performing input / output, address, and control, and has a predetermined area for bonding in a package.

As semiconductor memory devices become highly integrated, ultra-fast, and low-power, many circuits such as impedance matching circuits and other signal response speeds are required, and the area occupied by input / output circuits in semiconductor chips is increasing.

In addition, since the high-speed input / output circuit uses a large amount of current, the power noise generated when the semiconductor memory device is switched in the power supply unit is very large, which is a major factor in reducing the reliability of the semiconductor memory device.

In order to prevent such a phenomenon, a method of reducing noise by adding a decoupling capacitor component between a first power supply voltage and a second power supply voltage to instantly compensate for insufficient charge amount is provided. In this case, the power supply voltage may be applied to the first voltage, and the ground voltage may be applied to the second voltage.

However, it is not easy to provide a decoupling capacitor in the input / output circuit which occupies a large area already due to the limitation of the chip size and the layout of the semiconductor memory device.

In addition, the current general semiconductor memory device has a structure as shown in FIG. 1, and has a semiconductor substrate 1, a poly gate electrode 3, a bit line 4, a poly plate 5, and a first metal layer ( 6), the second metal layer 7 and the insulating layers 2a to 2e provided between the layers.                         

Then, the pad is embodied, that is, bonded through the second metal layer 7.

In this case, in addition to the second metal layer 7 to which the pad is bonded, the reason why the poly gate electrode 3, the bit line 4, the poly plate 5, and the first metal layer 6 is further provided is the bonding that is generated when the pad is bonded. This is to protect the semiconductor substrate 1 from stress (bonding stress).

That is, the poly gate, the bit line 4, the poly plate 5, and the first metal layer 6 stacked below the second metal layer 7 to which the pad is bonded are provided to perform a buffer role.

As described above, the semiconductor memory device according to the related art has the stacked structure as described above, and no circuit is inserted below the second metal layer 7 to which the pad is bonded.

Accordingly, the present invention provides a semiconductor memory device capable of forming a decoupling capacitor under the pad and solving problems such as cracking and shorting due to bonding stress of the pad.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having a decoupling capacitor in a region below a pad of a semiconductor memory device that has not been utilized in the past, thereby reducing power noise and minimizing the influence of bonding stress.

In order to achieve the above objects, a semiconductor memory device of the present invention includes at least one pad including a first conductive layer and a second conductive layer disposed to overlap the first conductive layer, and a semiconductor substrate under the at least one pad. And a first active region having a first voltage applied thereto, an insulating layer stacked over the first active region, and a third conductive layer stacked over the insulating layer, and having a second voltage applied thereto. It is characterized by including one decoupling capacitor.

Hereinafter, a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

2 is a diagram for describing the structure of a semiconductor memory device according to a first embodiment of the present invention.

As shown in FIG. 2, the semiconductor memory device of the present invention has a stacked structure, and as shown in FIG. 1, the bit line 4, the poly plate 5, the first metal layer 6, and the second A metal layer 7 and a plurality of insulating layers 2a to 2e formed between the layers, wherein the semiconductor substrate 1, the insulating layer 2a, and the poly gate electrode 3 of FIG. 131, the insulating layer 132, and the poly gate electrode 103.

Referring to the drawings, the poly gate electrode 103 is connected to the first power supply voltage, and the semiconductor substrate 131 is an area in which the active area 121 and the active area are not formed. The non-active region 101, and the insulating layer 132 is positioned between the active region 121 and the poly gate electrode 103 of the semiconductor substrate, thereby providing a voltage between the poly gate electrode 103 and the active region 121. Insulation that insulates the poly gate electrode 103 and the active region 121 by being located between the capacitor region 122 that charges the charge corresponding to the difference, and the inactive region 101 and the poly gate electrode 103 of the semiconductor substrate. Region 112.                     

Accordingly, the semiconductor memory device of FIG. 2 implements a decoupling capacitor with the poly gate electrode 103, the active region 121 of the semiconductor substrate 101, and the capacitor region 122, and the decoupling capacitor is the center of the pad. Implementing on the edge away from it avoids the direct effect of the bonding stress, which makes it possible to have a decoupling capacitor at the bottom of the pad.

Therefore, a decoupling capacitor is implemented under the pad of the semiconductor memory device without increasing the chip size of the semiconductor memory device, and power supply noise between the first power supply voltage and the second power supply voltage is reduced through the decoupling capacitor.

3 is a view showing a structure in which an active region 121 formed in the semiconductor substrate of FIG. 2, that is, a decoupling capacitor, is formed.

As shown in FIG. 3, when the contact surface between the insulating layer 132 and the semiconductor substrate 131 is horizontally cut out, the active region 121 corresponds to the semiconductor substrate 131 corresponding to the edge region of the poly gate electrode 103. It can be seen that the rectangular donut shape is formed at the position of).

In the pads of the semiconductor memory device of FIGS. 2 and 3 described above, a step is caused by a height difference between the active region 121 in the semiconductor substrate and the inactive region 101 of the semiconductor substrate.

Thus, the structure of the semiconductor memory device, which minimizes the step difference caused by the semiconductor substrate and reduces the bonding stress on the pad, is further described below.                     

FIG. 4 is a diagram showing the structure of a pad of the semiconductor memory device according to the second embodiment of the present invention, and FIG. 5 is a diagram showing the structure of the semiconductor substrate according to FIG.

4 has the same stacked structure as FIG. 2, but replaces the semiconductor substrate 131 of FIG. 2 with the semiconductor substrate 231 of FIG. 4.

The semiconductor substrate 201 may include a first active region 221 connected to a second power supply voltage, a second active region 211 not connected to a power supply voltage, and an area in which they are not formed, that is, an inactive region ( 21).

At this time, the second active region 211 minimizes the step difference due to the pad due to the inactive region 201 of the semiconductor substrate, and protects the semiconductor substrate 201 from a leakage phenomenon caused by stress during bonding. do.

As shown in FIG. 5, the second active region 211 is spaced apart from the inside of the first active region 121 having a rectangular donut shape by a predetermined distance to form a quadrangular shape.

FIG. 6 is a diagram illustrating a semiconductor memory device according to a third embodiment of the present invention, and FIG. 7 is a diagram illustrating a structure of a poly gate electrode according to FIG.

FIG. 6 has the same stacked structure and semiconductor substrate 231 as in FIG. 4, but the insulating layer 132 of FIG. 4, the poly gate electrode 103, and the insulating layer 302 of FIG. Replace with electrode 333.

Referring to the drawings, the poly gate electrode 323 is positioned at the edge of the poly gate electrode 323 and is located in the capacitor electrode region 333 connected to the first power voltage and in the region corresponding to the second active region. And an internal gate region 313 not connected to the first power supply voltage, and an insulating region 343 disposed between the regions 313 and 323 and separating the regions 313 and 323. In this case, the insulating region 343 is formed of the same material as the insulating layer 302.

Thus, decoupling capacitor region 322 is insensitive from the effects of bonding stress.

Accordingly, as illustrated in FIG. 7, the inner gate region 313 is spaced apart from the capacitor electrode region 323 formed in a rectangular donut shape corresponding to the position of the first active region 121 to be spaced in a predetermined distance. 2 will appear in a square shape at a position corresponding to the active region 211.

8A, 8B, and 8C illustrate a semiconductor memory device according to a fourth embodiment of the present invention. 8A has the same stacked structure as that of FIG. 2 and includes a semiconductor substrate 131 including a poly gate electrode 103 and an active region 121 formed thereon, and a capacitor formed between the poly gate electrode 103 and the active region 121. Is replaced by the semiconductor substrate 431 in which the active region 121 and the deep well 151 of FIG. 8A are formed.

8B is a semiconductor substrate 231 having the same stacked structure as that of FIG. 4 and having a first active region 121 connected to a second power supply voltage and a second active region not connected to a second power supply voltage. Is replaced by the semiconductor substrate 531 in which the active region 121 and the deep well 151 of FIG. 8B are formed.

In addition, FIG. 8C has the same stacked structure as that of FIG. 6, and has a capacitor electrode region 323 connected to the edge of the poly gate electrode and the first power supply voltage and the first active voltage, and corresponds to the second active region. An inner gate region 313 cut by a position and an insulating layer 343 between the capacitor electrode region 323 and the inner gate region 313, and the semiconductor substrate 201 is formed in the active region 121 of FIG. 8C. The semiconductor substrate 631 in which the deep well 151 is formed is replaced with the semiconductor substrate 631.

That is, the semiconductor memory device shown in FIGS. 8A, 8B, and 8C may be formed outside the active region 121 and the active region 121 serving as capacitors of the semiconductor substrate regions 431, 531, 631 of FIGS. 2, 4, and 6. A deep well 151 deeply spaced apart from each other is provided.

Accordingly, in the pads of the semiconductor memory device of the above embodiments, a deep well 151 is formed between the pads and the pads and between the pads and the circuits to separate the circuits so that the circuits are less influenced by the signals and thus further reduce noise. It has advantages.

In the above description, each layer of the semiconductor memory device is formed on the semiconductor substrate in the order of the poly gate electrode, the bit line, the poly plate, the metal layers and the insulating layer between the layers, but in practical applications, the stacking order, the material, and Naturally, the number can be changed in various ways according to user or design needs.

In addition, in the present invention, a capacitor is provided in the insulating layer between the poly gate electrode and the semiconductor substrate, but it is natural that an element having the same function as a decoupling capacitor can be formed by using another interlayer insulating layer if necessary. .

While the above has been described with reference to the preferred embodiments of the present invention, those skilled in the art will be variously modified and modified within the scope of the present invention without departing from the spirit and scope of the present invention described in the claims below. It will be appreciated that it can be changed.

As described above, the semiconductor memory device of the present invention has a decoupling capacitor having a function of maintaining a constant signal level of a power supply or a specific signal in a pad in a high-speed semiconductor memory device of limited space, thereby reducing power noise. Therefore, there is an advantage of preventing malfunction of the semiconductor memory device and improving reliability.

Claims (7)

At least one pad having a first conductive layer and a second conductive layer disposed to overlap the first conductive layer; And A first active region formed in the semiconductor substrate under the at least one pad and to which a first voltage is applied; An insulating layer stacked on the first active region; And And a decoupling capacitor stacked on top of the insulating layer and having a third conductive layer to which a second voltage is applied. The method of claim 1, wherein the decoupling capacitor, A semiconductor memory device characterized by being insulated from the pad The method of claim 1, wherein the first active region, A semiconductor memory device, characterized in that the rectangular donut shape. According to claim 1, And a second active region formed in an inner region of the first active region formed in the substrate. According to claim 1, And a deep well spaced apart from the first active region by a predetermined distance and formed in an outer region of the first active region. The method of claim 4, wherein the third conductive layer, And a first region formed at a position overlapping with the first active region, and a second region formed at a position overlapping with the second active region. According to claim 1, And wherein the first voltage is a power supply voltage and the second voltage is a ground voltage.

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