KR101062848B1 - Shielding Structure for Cross-talk Shielding in Semiconductor Chips with Through Silicon Vias - Google Patents

Abstract

The present invention is to provide a semiconductor chip that can shield crosstalk between the through-silicon via and minimize the substrate noise, the semiconductor chip of the present invention comprises a silicon substrate; A plurality of through silicon vias penetrating the silicon substrate; And a crosstalk shielding portion surrounding the periphery of at least one of the through silicon vias, and the present invention includes a crosstalk shielding portion surrounding the periphery of the through silicon vias, thereby preventing crosstalk between the through silicon vias. In addition, the present invention has the effect of preventing the crosstalk between the through-silicon via and the substrate noise by enclosing the periphery of the through-silicon via using a capacitor.

Semiconductor Package, Through Silicon Via, Crosstalk, Noise, Intervia

Description

SHIELDING STRUCTURE FOR CROSSTALK SHELDING IN SEMICONDUCTOR CHIP WITH THROUGH SILICON VIA}

The present invention relates to a semiconductor package, and more particularly, to a semiconductor chip having a through silicon via structure having a shielding structure for crosstalk shielding.

Packaging technologies for semiconductor integrated devices have been continuously developed in accordance with the demand for miniaturization and high capacity. Recently, various technologies for multilayer semiconductor packages that can satisfy the miniaturization and high capacity and the mounting efficiency have been developed.

Integrating multiple semiconductor chips in one package horizontally requires long off-chip interconnection, which is consumed in interconnection in low power applications. Power consumption is getting bigger.

Previously, wirebonding has been used for three-dimensional lamination. However, wire bonding has severe spatial constraints and has been a limiting factor in circuit operation due to parasitic inductance.

Therefore, while 3D IC technology is being developed that stacks on a semiconductor chip in three dimensions, a through silicon via (TSV) technology that passes through a silicon substrate is developed to realize the shortest connection wiring. It became.

A stacked semiconductor package using through silicon vias (TSVs) generally forms a via hole penetrating through the semiconductor chip in the semiconductor chip, and fills a conductive material in the through via hole to pass through silicon via. A through electrode called TSV), and is electrically connected between the upper semiconductor chip and the lower semiconductor chip through the through electrode.

1 is a cross-sectional view illustrating a semiconductor chip having a through silicon via according to the prior art.

As illustrated in FIG. 1, the semiconductor chip 100 includes a silicon substrate 110 and a plurality of through silicon vias 120 penetrating through the silicon substrate 110. In addition, bumps 130 are formed at both ends of the through silicon vias, and an insulating layer 140 is coated on the top and bottom surfaces of the silicon substrate 110, and the through silicon vias 120 are buried in the insulating layer 140. It is also covered by the side wall of the through hole (not shown).

Although not shown, in the case of stacking a plurality of semiconductor chips, the semiconductor chips are physically and electrically connected to each other by the through silicon vias 120. The through silicon vias 120 are electrically connected to pads of the semiconductor chip through redistribution and the like, and are formed of a metal film.

However, in the related art, as the through silicon via 120 penetrates through the entirety of the silicon substrate 110, substrate noise, which may affect the circuit operation, and a couple of adjacent through silicon vias 120 are coupled. There is a problem that crosstalk occurs due to a ring phenomenon. Alternatively, crosstalk between the through silicon vias and the active circuits or between the through silicon vias and the passive circuits and the on-chip interconnection is easy to occur in both directions.

Therefore, a structure for shielding crosstalk is needed.

It is natural to use a grounded through silicon via (GND TSV, hereinafter abbreviated as 'Ground Through Silicon Via') structure to shield crosstalk, effectively reducing crosstalk between various structures. However, because the minimum pitch between the through-silicon vias is larger than the on-chip connection wiring structure, it is necessary to always keep the ground-through silicon via (GND TSV) next to the chip area.

Accordingly, there is a need for a method capable of effectively reducing crosstalk without occupying a large chip area in a three-dimensional multilayer integrated circuit using through silicon vias.

The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a semiconductor chip capable of shielding crosstalk between through silicon vias.

In addition, another object of the present invention to provide a semiconductor chip that can minimize the substrate noise.

The semiconductor chip of the present invention for achieving the above object is a silicon substrate; A plurality of through silicon vias penetrating the silicon substrate; And a crosstalk shielding portion surrounding at least one of the through silicon vias, and further comprising an insulating layer formed on an upper surface of the silicon substrate, wherein the crosstalk shielding portion is provided inside the insulating layer. While being connected to the silicon substrate and grounded, the crosstalk shielding portion surrounding the periphery of the through silicon via; And a plurality of vias connected to the silicon substrate and grounded through the ring.

In addition, the semiconductor chip of the present invention is a silicon substrate; A plurality of through silicon vias penetrating the silicon substrate; An insulating film formed on the silicon substrate; A crosstalk shielding portion formed in the insulating layer and surrounding at least one of the through silicon vias; And a guard ring formed in the silicon substrate to surround the periphery of the through silicon via.

In addition, the semiconductor chip of the present invention is a semiconductor chip having a silicon substrate and a plurality of through-silicon via penetrating the silicon substrate; And a capacitor formed on the silicon substrate so as to surround the at least one of the through silicon vias.

The present invention described above has an effect of preventing crosstalk between the through silicon vias by providing a crosstalk shielding portion surrounding the periphery of the through silicon vias.

In addition, the present invention has the effect of preventing the crosstalk between the through-silicon via and the substrate noise by enclosing the periphery of the through-silicon via using a capacitor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. .

The ground shielding structure for shielding the crosstalk proposed by the present invention is a guard ring in which a bias is applied to an inter-level ground via and a ground previously used in on-chip. There are two structures, the finely distributed DRAM cell capacitor structure. Three simple structures on the on-chip can be used to connect to ground, effectively shielding crosstalk from 3D-IC using through silicon vias.

FIG. 2A is a plan view showing the structure of a semiconductor chip according to a first embodiment of the present invention, FIG. 2B is a cross-sectional view taken along the line AA ′ of FIG. 2A, and FIG. 2C is a line B-B ′ of FIG. 2A. According to the cross-sectional view.

2A to 2C, the semiconductor chip 200 according to the first embodiment may include a silicon substrate 210, a plurality of through silicon vias 220A and 220B passing through the silicon substrate 210, and at least one of the semiconductor chips 200. And a crosstalk shielding portion 230 surrounding the periphery of the through silicon via 220B. In addition, an upper surface and a bottom surface of the silicon substrate 210 are covered with an insulating film 240 such as a silicon oxide film (SiO ₂ ), and the insulating film 240 is a through hole in which the through silicon vias 220A and 220B are embedded. Is also covered by the side wall. That is, an insulating film 240 is formed between the through silicon vias 220A and 220B and the silicon substrate 210. Bumps 250 are connected to both ends of the through silicon vias 220A and 220B, and a protective layer 260 is coated on one side (under the crosstalk shielding portion) of the silicon substrate 210. It is.

The crosstalk shielding unit 230 is for reducing crosstalk between each other in a structure in which the through silicon vias 220A and 220B face each other. The crosstalk shielding unit 230 may use an inter-via used in an on-chip layout to surround the periphery of one of the through silicon vias. The crosstalk shielding part 230 is grounded to the silicon substrate 210, thereby preventing crosstalk between neighboring through silicon vias 220A and 220B. Preferably, the crosstalk shielding part 230 may be located inside the insulating film 240, and includes a ring 230A surrounding the periphery of the through silicon via 220B and a plurality of vias penetrating a portion of the ring 230A. 230B). Here, the via 230B is grounded to the silicon substrate 210. The ring 230A may have a rectangular shape, in which the via 230B is connected to the silicon substrate 230 through each side of the ring 230A. Thus, the ring 230A may be insulated from the silicon substrate 210 by the insulating film 240. The crosstalk shielding portion 230 is formed of a conductive film such as a tungsten film.

In the above-described first embodiment, the through silicon vias 220A and 220B may both include a signal through silicon via (Signal TSV). Therefore, crosstalk between the signal passing silicon vias that are faced by the crosstalk shielding unit 230 is prevented.

 Preferably, the through silicon vias 220A and 220B include an aluminum film Al, and a barrier film serving as a barrier between the silicon substrate and the insulating film 240 may be formed in advance before the through silicon vias 220A and 220B are formed. . The barrier film may sequentially form titanium (Ti) and titanium nitride film (TiN).

3A is a plan view showing the structure of a semiconductor chip according to a second embodiment of the present invention. The second embodiment is a structure for preventing crosstalk between the signal through silicon via and the ground through silicon via.

Referring to FIG. 3A, the semiconductor chip 300 according to the second embodiment may include a ground through silicon via (GTSV, 320A) and a signal through silicon via (STSV,) that pass through the silicon substrate 310 and the silicon substrate 310. 320B) and a crosstalk shielding portion 330 surrounding the periphery of the signal penetrating silicon via 320B.

The crosstalk shielding unit 330 is to reduce crosstalk between each other in a structure in which the ground penetrating silicon vias 320A and the signal penetrating silicon vias 320B face each other. The crosstalk shielding unit 330 may use an inter-via used in an on-chip layout to surround the periphery of the signal penetrating silicon via 320B. The crosstalk shielding unit 330 is connected to the ground through silicon via 320A through a connection wire 340 to ground to the silicon substrate 310, and thus the signal to the neighboring ground through silicon via 320A is signaled. Crosstalk between the through silicon vias 320B is prevented. Preferably, the crosstalk shielding portion 330 may include a ring 330A surrounding the periphery of the signal penetrating silicon via 320B and a plurality of vias 330B penetrating a portion of the ring 330A. One via 330B is connected to the ground through silicon via 320A through the connection line 340. Here, all of the vias 330B may be connected to the silicon substrate 310. The ring 330A may have a rectangular shape, in which the via 330B is connected to the silicon substrate 310 through each side of the ring 330A. The crosstalk shielding portion 330 is formed of a conductive film such as a tungsten film.

In the above-described second embodiment, the through silicon via may include a form in which the signal through silicon vias SSTV 320B and the ground through silicon vias GTSV 320A face each other. Therefore, crosstalk between the signal penetrating silicon via 320B and the ground penetrating silicon via 320A which is faced by the crosstalk shielding unit 330 is prevented.

The second embodiment may have a structure as shown in FIG. 3B.

3B is a modified example of the second embodiment, and the semiconductor chip 300A may further prevent crosstalk by further using a guard ring 350 contacted to the silicon substrate 310 with a ground. The guard ring 350 may be used simultaneously with the crosstalk shielding part 330 or may be used separately. For example, the guard ring 350 may be formed by etching the silicon substrate 310 in the form of a trench so as to surround the region where the through silicon via is to be formed, and then embedding an insulating layer in the trench.

In the presence of signal through silicon vias (GND TSVs) and through silicon vias that pass through the silicon substrate, crosstalk between the through silicon vias and the adjacent active devices, ie, substrate coupling, may be problematic. In order to suppress such crosstalk, in the third embodiment, a capacitor having finely distributed vias may be connected to ground.

When the electrode of the cell capacitor is connected to the ground potential, it has an effect of suppressing noise generated in the through silicon via structure. Two types of cell capacitor structures exist. When the trench cell capacitor structure is used, noise propagation to the substrate and adjacent through silicon vias is suppressed, and when the stacked cell capacitor structure is used, noise propagation to adjacent through silicon vias can be suppressed. .

4A is a plan view illustrating a structure of a semiconductor chip according to a third exemplary embodiment of the present invention, and FIG. 4B is a cross-sectional view taken along line AA ′ of FIG. 4A. The third embodiment is a case where the crosstalk shielding portion which prevents crosstalk between the signal through silicon via and the ground through silicon via is a capacitor.

4A and 4B, the semiconductor chip 400 according to the third embodiment may include a silicon substrate 410, a through silicon via 420 penetrating through the silicon substrate 410, and a periphery of the through silicon via 420. A capacitor 430 is formed in the silicon substrate 410 while surrounding it. In addition, an upper surface and a bottom surface of the silicon substrate 410 are covered with an insulating film 440 such as a silicon oxide film, and the insulating film 440 is also covered with sidewalls of through holes (not shown) in which the through silicon vias 420 are embedded. It is. In other words, an insulating film 440 is formed between the through-silicon via 420 and the silicon substrate 410. Bumps 450 are connected to both ends of the through silicon via 420. A protective layer 460 is coated on one surface (under the crosstalk shielding portion) of the silicon substrate 410.

As described above, when the capacitor 430 is used, a quasi-coaxial TSV structure is formed.

The capacitor 430 is connected to ground, and prevents crosstalk between the through silicon vias 420 and simultaneously reduces substrate noise. The capacitor 430 may use a DRAM cell capacitor used in an on-chip layout to surround the periphery of the through silicon via 420. Therefore, the capacitor 430 may include a capacitor having a plate electrode and a charge storage electrode, and a dielectric film between the plate electrode and the charge storage electrode. In addition, the capacitor 430 may include a trench capacitor or a stack capacitor. The capacitor 430 illustrated in FIGS. 4A and 4B is a case where a trench capacitor is applied.

In the case of applying the trench capacitor, the crosstalk shielding portion may be formed inside the trench provided in the silicon substrate.

In the above-described third embodiment, cross talk between the through-silicon vias is prevented by the capacitor 430 connected to the ground. In addition, in the third embodiment, substrate noise can be suppressed by applying a capacitor as the crosstalk shielding portion.

In order to prove the crosstalk minimization effect of the structure proposed in the present invention, the difference will be examined through 3D full-wave simulation.

5A is a diagram comparing S parameters, and FIG. 5B is a diagram comparing crosstalk voltages. 5A and 5B, a reference semiconductor chip without a shielding structure and a semiconductor chip Inter-Via having a crosstalk shielding portion according to the first embodiment are compared.

FIG. 5A shows a frequency domain result of a 3D full-wave simulator as an 'S' parameter result, which means a coupled crosstalk between two unconnected signal through silicon vias (STSVs). It can be seen that the structure grounded with intervia has a lower effect than a reference semiconductor chip without a shielding structure.

When the TDR / TDT simulation is performed in the time domain using the S parameter of FIG. 5A, as shown in FIG. 5B, in the case of the semiconductor chip using intervia rather than the reference semiconductor chip, the magnitude of crosstalk voltage is reduced. That is, it can be seen that the near coupling is reduced from 35mV to 22mV, and the far coupling is reduced from 22mV to 15mV.

FIG. 6 is a diagram illustrating noise suppression effect when a shielding structure using a capacitor is used as in the third embodiment, in which the shielding structure using a capacitor is provided (W Quasi-Coaxial) when there is no shielding structure using a capacitor. It can be seen that the noise suppression effect is about 10dB higher than that of (WO Quasi-coaxial).

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

1 is a cross-sectional view showing a semiconductor chip having a through silicon via according to the prior art.

2A is a plan view showing the structure of a semiconductor chip according to the first embodiment of the present invention.

FIG. 2B is a cross-sectional view taken along the line AA ′ of FIG. 2A;

FIG. 2C is a cross-sectional view taken along line BB ′ of FIG. 2A;

3A is a plan view showing the structure of a semiconductor chip according to a second embodiment of the present invention.

3B is a modification of the second embodiment.

4A is a plan view showing the structure of a semiconductor chip according to a third embodiment of the present invention.

4B is a cross-sectional view taken along the line AA ′ of FIG. 4A.

5A is a comparison of S parameters.

5B is a diagram comparing crosstalk voltage.

FIG. 6 is a diagram showing a noise suppression effect when a shielding structure using a capacitor is used as in the third embodiment; FIG.

* Explanation of symbols for the main parts of the drawings

210: silicon substrate 220A, 220B: through silicon via

230: crosstalk shielding portion 240: insulating film

250: bump

Claims (18)

Silicon substrate; A plurality of through silicon vias penetrating the silicon substrate; And A crosstalk shielding portion surrounding at least one of the through silicon vias Semiconductor chip comprising a. The method of claim 1, Further comprising an insulating film formed on an upper surface of any one of the silicon substrate, The crosstalk shielding portion is provided inside the insulating layer and is connected to the silicon substrate and grounded. The method of claim 1, The crosstalk shielding unit, A ring surrounding the periphery of the through silicon via; And A plurality of vias connected to the silicon substrate and grounded through the ring Semiconductor chip comprising a. The method of claim 1, The crosstalk shielding portion is a semiconductor chip formed of a conductive film. The method of claim 1, The plurality of through-silicon vias comprises a signal through silicon via. The method of claim 1, The plurality of through silicon vias may include a signal through silicon via (Signal TSV) and a ground through silicon via (GND TSV), and the crosstalk shielding portion may surround the signal through silicon via. The method of claim 6, And the ground through silicon via is grounded, and the crosstalk shielding portion is connected to the ground through silicon via. Silicon substrate; A plurality of through silicon vias penetrating the silicon substrate; An insulating film formed on the silicon substrate; A crosstalk shielding portion formed in the insulating layer and surrounding at least one of the through silicon vias; And A guard ring formed in the silicon substrate to surround the periphery of the through silicon via Semiconductor chip comprising a. The method of claim 8, And the crosstalk shielding portion is connected to the silicon substrate and grounded. The method of claim 8, The crosstalk shielding unit, A ring surrounding the periphery of the through silicon via; And A plurality of vias connected to the silicon substrate and grounded through the ring Semiconductor chip comprising a. The method of claim 8, The crosstalk shielding portion is a semiconductor chip formed of a conductive film. The method of claim 8, The plurality of through silicon vias may include a signal through silicon via (Signal TSV) and a ground through silicon via (GND TSV), and the crosstalk shielding portion may surround the signal through silicon via. The method of claim 12, And the ground through silicon via is grounded, and the crosstalk shielding portion is connected to the ground through silicon via. The method of claim 8, The guard ring may include an insulating film embedded in a trench provided in the silicon substrate. A semiconductor chip having a silicon substrate and a plurality of through silicon vias penetrating through the silicon substrate; And A capacitor formed in the silicon substrate to surround at least one of the through silicon vias Semiconductor package comprising a. The method of claim 15, The capacitor is a grounded semiconductor package. The method of claim 15, The capacitor is a semiconductor package including a trench capacitor (Trench capacitor). The method of claim 15, The capacitor is a semiconductor package including a stack capacitor (Stack capacitor).

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