KR20060061501A - Overlay measurement system and method for measuring overlay - Google Patents

Abstract

The present invention relates to an overlay measurement system and an overlay measurement method for accurate overlay measurement and compensation, the overlay measurement system according to the present invention. An overlay measuring unit for measuring an overlay to determine whether the alignment is performed, and determining and adjusting the overlay according to the measured value; Before measuring the overlay in the overlay measuring unit, the tilt component of the overlay mark is measured and analyzed to determine whether the tilt is generated and an auto leveling unit for compensating for this. According to the present invention, the reliability of the overlay measurement can be improved, and process defects can be prevented or minimized.

Overlay, Tilt, Reward, Mark

Description

Overlay measurement system and method for measuring overlay}             

1 is a diagram illustrating an overlay measurement method using an overlay mark.

2 is a view showing a normal overlay mark

3 is a diagram showing an overlay mark at the time of tilt generation;

4 is a block diagram of an overlay measurement system according to an embodiment of the present invention.

5 and 6 illustrate signals for determining whether tilt is generated.

7 is a flow chart for overlay measurement

* Description of the symbols for the main parts of the drawings *

100: auto leveling unit 200: overlay measurement unit

110: tilt measurement unit 120: tilt compensation unit

The present invention relates to an overlay measurement system and an overlay measurement method used in a photolithography process, and more particularly, to an overlay measurement system and an overlay measurement method capable of auto leveling.

In recent years, with the rapid spread of information media such as computers, semiconductor devices are also rapidly developing. In terms of its function, the semiconductor device is required to operate at a high speed and to have a large storage capacity. In response to such demands, manufacturing techniques have been developed for semiconductor devices to improve the degree of integration, reliability, and response speed. Accordingly, the demand for microfabrication techniques such as photolithography techniques is becoming strict as a main technique for improving the integration degree of the semiconductor device.

In general, photo-lithography is a process for transferring different pattern images formed on a plurality of reticles onto a wafer, and these pattern images are accompanied by performing other processes such as etching or film deposition. By being sequentially transferred and combined on the wafer, a circuit pattern having a plurality of layers is formed.

Important management items in the photolithography process include designing a precise circuit pattern and different pattern layers constituting the circuit pattern to be precisely aligned and overlapping each other, that is, overlaying.

Even now, many limitations have been challenged to implement a more integrated and more accurate circuit pattern such as modifying a reticle pattern or changing a photoresist for an overlay management item. Thus, reliability for overlay measurements is increasingly required.

Although the pattern size is largely determined by the equipment's specifications and photoresist, the overlay of each pattern image is required to be constantly improved by regular preventive maintenance or by the development of the instrument.

The ultimate goal of overlay management is to ensure that the pattern layer by the transferred pattern image overlaps as accurately as possible with the existing pattern layer, and through measurement of this overlay, development and subsequent process progress or misalignment of existing patterns ( It is to obtain the data for correcting misalignment and criteria for judging rework.

As semiconductor devices become more integrated and miniaturized, the overlay of the lower and upper layers becomes more and more important for the reliability and yield of the device, so accurate measurement of the overlay state is necessary. In proceeding with the lithography for manufacturing the semiconductor device of the laminated structure, the identification of the overlay of the lower layer and the upper layer already formed is generally performed using the overlay mark shown as an example in FIG.

As shown in Fig. 1, the overlay mark 10 is formed in the frame-shaped first mark 20 formed during the formation of the lower layer in the pre-process with the test wafer and in the chord process. It consists of a plate-shaped second mark 30. This overlay mark 10 is usually provided on a scribe line that divides the die. The first mark 20 is formed of a pattern made of the same material as the lower layer, and the second mark 30 is formed of a photoresist pattern.

In the measurement apparatus for measuring the overlay mark 10, the X-axis spacing X1 and X2 of the first mark 20 and the second mark 30 are read. Then, from the read value, the offset X = (X1-X2) / 2 from which the center of the second mark 30 deviates from the center of the first mark 20 is calculated. The closer the offset is to zero, the better the overlay is.

Since the shift may occur not only in the X-axis direction but also in the Y-axis direction, the first mark 20 and the second mark 30 also measure the offset in the Y-axis direction after measuring the offset in the X-axis direction. .

The measuring device feeds back the various overlay parameters including the measured X and Y offsets to the exposure device. As a result, the compensating of the overlay by the measured overlay parameter is performed on the next wafer for forming the actual device.

Recently, tool-induced shift (TIS) correction is performed in order to minimize the influence of the light incident on the light and the influence of the film quality of the measurement mark.

TIS correction is performed as follows.

The wafer on which the first mark 20 and the second mark 30 are formed is rotated at 0 degrees and 180 degrees to measure X and Y offsets at 0 degrees and 180 degrees.

Ideally, if the offset at 0 degrees is X = 0.12 Y =-0.1, then at 180 degrees, X =-0.12 Y = 0.1. Thus, TIS offset X = (X value 0 degrees + X value 180 degrees) / 2 = (0.12 + 0.12) / 2 = 0, TIS offset Y = (Y value 0 degrees + Y value 180 degrees) / 2 = (- 0.1 + 0.1) / 2 = 0.

However, in practical situations, for example, if X = 0.12 Y =-0.1 at 0 degrees and X =-0.14 Y = 0.09 at 180 degrees, then TIS offset X = (X value 0 degrees-X value 180 degrees) / 2 = ( 0.12 + 0.14) / 2 = -0.01, TIS offset Y = (Y value 0 degrees-Y value 180 degrees) / 2 = (-0.1 + 0..09) / 2 =-0.05.

 When the TIS offset is performed, the TIS offset is added to each target by adding or subtracting the TIS offset value, which has been pre-calculated to the actual reading of the target value at 0 degrees. This results in more accurate and ideal data.

However, a wafer which is automatically conveyed onto the wafer stage and fixed on the wafer holder looks like a completely flat surface (FLAT), but usually undergoes some warping or twisting due to processing such as a high temperature process. If such warpage or twist occurs, the exposure surface may not be perpendicular to the exposure optical axis depending on the chip. If a tilt occurs in the wafer mark due to the warping or twisting of the wafer, the overlay measurement result may appear in the misaligned state even though the actual aligned state is normal. May appear in alignment.

FIG. 2 shows the normal overlay mark state, and FIG. 3 shows the overlay mark at the time of tilt generation.

As shown in FIG. 2, when the overlay mark 110 is normal, the first mark 120 and the second mark 130 are measured in a normal state. As shown in FIG. 3, the overlay mark 210 is measured. At the time of tilt generation, if the measured value such as TIS offset is actually aligned with light, but the mark is tilted due to the degree of warpage of the wafer or the effect of film quality, it may affect the measured value during overlay measurement. It can be a factor. That is, when the first mark 220 and the second mark 230 are normally aligned, when the tilt is not generated in the mark 210, the error component is measured as a value close to "0", When the tilt occurs, it is measured in the state of miss reading of several nm to several tens nm.

Therefore, there is a need for a system capable of compensating the tilt component of the wafer in the overlay measurement system to minimize such error components.

Accordingly, an object of the present invention is to provide an overlay measuring system and an overlay measuring method capable of overcoming the above-mentioned conventional problems.

Another object of the present invention is to provide an overlay measuring system and an overlay measuring method capable of compensating by measuring the tilt of the overlay mark.

Still another object of the present invention is to provide an overlay measuring system and an overlay measuring method capable of improving the reliability of overlay measuring.

Still another object of the present invention is to provide an overlay measuring system and an overlay measuring method capable of preventing or minimizing a process defect caused by misalignment of an overlay mark.

According to an aspect of the present invention for achieving some of the above technical problems, the overlay measurement system according to the present invention measures the overlay to determine whether the alignment, and whether or not according to the measured value An overlay measurement unit for determining and compensating for this; Before measuring the overlay in the overlay measuring unit, the tilt component of the overlay mark is measured and analyzed to determine whether the tilt is generated and an auto leveling unit for compensating for this.

The overlay may be various overlay parameters including X, Y offset, and TIS offset values, and the auto leveling unit may include a tilt measuring unit for measuring a tilt component of the overlay mark; And a tilt compensator for analyzing the tilt component of the measured overlay mark and compensating for the position of the wafer on which the overlay mark is formed according to the analyzed data. The position compensation of the wafer may be performed by PZT having a volume correlation coefficient with respect to the voltage applied to the wafer stage.

According to another aspect of the present invention for achieving some of the above technical problem, the overlay measuring method according to the present invention, by measuring the tilt component of the overlay mark and analyzing it to determine whether the tilt to compensate for the tilt generation Wow; The method may include measuring the overlay of the overlay mark and analyzing the overlay to determine whether the alignment is aligned, and compensating for the misalignment.

The overlay may be various overlay parameters including X, Y offset, and TIS offset values, and the tilt compensation of the overlay mark may be performed by applying a predetermined voltage to a PZT having a volume correlation coefficient with respect to the voltage applied to the wafer stage. By applying.

According to the above apparatus and method configuration, tilt compensation of the overlay mark can be performed and the reliability of overlay measurement can be improved.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, without any other intention than to provide a thorough understanding of the present invention to those skilled in the art.

4 is a block diagram of an overlay measurement system according to an embodiment of the present invention.

As shown in FIG. 4, the overlay measurement system according to the exemplary embodiment includes an auto leveling unit 100 and an overlay measurement unit 200.

The auto leveling unit 100 measures the tilt component of the overlay mark and analyzes the tilt component to determine whether the tilt is generated and compensates for it. The auto leveling unit 100 includes a tilt measuring unit 110 and a tilt compensating unit 120.

 The tilt measuring unit 110 measures the tilt component of the overlay mark.

Whether the overlay mark is tilted can be determined by measuring the overlay mark on the wafer with an image camera and analyzing the measured image signal.

The tilt compensator 120 analyzes the tilt component of the measured overlay mark and compensates the position of the wafer on which the overlay mark is formed according to the analyzed data. The position compensation of the wafer is performed by a Piezo Crystal Controller (PZT) having a volume correlation coefficient with respect to the voltage applied to the wafer stage.

The overlay measuring unit 200 measures the overlay parameters including X, Y offset, TIS offset value, and the like as in the related art, analyzes them, determines whether to align, and compensates for them.

5 and 6 illustrate a method of determining whether or not an overlay mark is generated. FIG. 5 is an image signal of an overlay mark in a normal case, and FIG. 6 is an image signal of an overlay mark when tilt is generated.

As shown in FIG. 5, the image signal of the overlay mark in the normal case has a structure in which the left and right are symmetric, and thus, no tilt is generated.

As shown in FIG. 6, when the tilt is generated, there is a difference between the left signal 40 and the right signal 50. For example, it is determined that the left side of the wafer is formed higher than the right side by analyzing such a signal.

FIG. 7 illustrates an operation flowchart for overlay measurement and compensation in FIG. 4.

As shown in FIG. 7, the operation of the overlay measurement system according to an embodiment of the present invention begins by first loading a wafer into a wafer stage (312).

Once the wafer is loaded 312, alignment for overlay measurement is done 314.

Once the alignment is done (314), it moves to the overlay mark to be measured for overlay measurement (316).

Thereafter, auto focus adjustment is performed (318), and thus the movement to the most optimal focus is prepared (320) for overlay measurement.

Next, the tilt component of the overlay mark is measured by the auto leveling unit 100 of the overlay measurement system, and thus the tilt component is determined by analyzing the measured tilt component (322).

Tilt analysis is to analyze the image signal as shown in Figures 5 and 6 by comparing the left and right signals in the X-axis, and the top and bottom signals in the Y-axis direction.

If it is determined that the mark is not tilted, the process proceeds to the next step. If it is determined that the mark is tilted, tilt compensation is performed (326).

The tilt compensation is done by PZT having a volume correlation coefficient for the voltage applied to the wafer stage. The compensation in the X-axis direction is that if the result of subtracting the peak value of the left signal from the peak value of the left signal has a positive value, the PZT is moved upward, and if it has a negative value, Move the PZT down. Accordingly, the tilt is compensated for by moving the wafer stage.

And, the compensation in the Y-axis direction is to move the PZT up if the result of subtracting the peak value of the lower signal from the peak value of the lower signal has a positive value, and if the negative value has a negative value, Make it move down. As a result, the tilt of the wafer is compensated.

Next, it is measured whether the mark is tilted again, and it is determined whether the tilt component is within the range of the reference spec (326) (326).

If the tilt component is out of the reference specification, the tilt component is analyzed and compensated again. If the tilt component is in the range of the reference specification, overlay measurement is performed as in the prior art (328). In other words, by analyzing the measured values of the various overlay parameters including the X, Y offset, TIS offset value, etc. to determine whether to align or compensate for them (330).

When the compensation of the overlay mark is performed, the control moves to the next target (332).

Overlay measurement and compensation are performed by the above process.

As described above, according to the present invention, it is possible to improve the reliability of the overlay measurement by providing a system that automatically determines whether the overlay mark is tilted and compensates it, unlike the conventional art.

The description of the above embodiments is merely given by way of example with reference to the drawings for a more thorough understanding of the present invention, and should not be construed as limiting the invention. In addition, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the basic principles of the present invention.

As described above, according to the present invention, unlike measuring only various overlay parameters in the related art, the reliability of overlay measurement can be improved by determining whether the overlay mark is tilted and automatically compensating for it. As a result, process defects due to misalignment of overlay marks may be prevented or minimized.

Claims (7)

In the overlay measurement system: An overlay measuring unit for measuring an overlay to determine whether the alignment is performed, and determining and adjusting the overlay according to the measured value; And an auto leveling unit configured to measure the tilt component of the overlay mark and analyze the tilt component of the overlay mark before measuring the overlay in the overlay measurement unit to determine whether the tilt is generated and compensate for it. The method of claim 1, The overlay measurement system, characterized in that the overlay parameters including the X, Y offset, TIS offset value. The method of claim 2, wherein the auto leveling unit, A tilt measuring unit for measuring a tilt component of the overlay mark; And a tilt compensator for analyzing the tilt component of the measured overlay mark and compensating for the position of the wafer on which the overlay mark is formed according to the analyzed data. The method of claim 3, Position compensation of the wafer is performed by the PZT having a volume correlation coefficient for the voltage applied to the wafer stage. In the overlay measurement method: Measuring the tilt component of the overlay mark and analyzing the tilt component to determine whether the tilt is to be compensated for when the tilt is generated; And measuring the overlay of the overlay mark and analyzing the overlay to determine whether the alignment is aligned, and compensating for the misalignment. The method of claim 5, The overlay measuring method of the overlay characterized in that the various overlay parameters including the X, Y offset, TIS offset value. The method of claim 6, Tilt compensation of the overlay mark is performed by applying a predetermined voltage to the PZT having a volume correlation coefficient with respect to the voltage applied to the wafer stage.

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