KR101861121B1 - A Subaperture Stitching Method for measuring of a Wafer Geometry Metric - Google Patents

Abstract

The present invention relates to a method for providing wafer geometry that is suitable for improving overlay and process control during semiconductor fabrication, wherein the wafer geometry measurement is performed using a small diameter gauge (reference mirror) having a smaller measurement diameter than a large diameter wafer A method of calculating a single wafer geometry metric through a stitching process by measuring a wafer with a sub-aperture in each region will be described. A method for compensating for a system error (stage error, piston error, tilt, aberration, etc.) which is involved in acquiring data in each sub-aperture in order to stitch each sub-aperture into each other is included in the stitching step. In the present invention, a step for primarily compensating for the stage error is performed first, and then a step for compensating for other system errors except for the stage error is performed first, and then, until the final stitching result value becomes optimal The steps of the primary and secondary are repeatedly performed.

Description

[0001] The present invention relates to a sub-aperture stitching method for measuring a wafer geometry metric,

The present invention relates to a method for providing wafer geometry suitable for improving overlay and process control during semiconductor fabrication, and more particularly to a method and apparatus for wafer geometry measurement using a small diameter gauge (reference mirror) having a smaller measurement diameter than a wafer of large diameter in wafer geometry measurement The present invention relates to a method for calculating a single wafer geometry metric through a stitching process in which a wafer is divided into small areas (hereinafter referred to as " minor bores "

The present invention also provides a stitching processor for matching measured aperture diameters to compensate for system errors (stage error, piston error, tilt, aberration, etc.) that are involved in acquiring data at each aperture Method.

To accomplish this, a first stage for compensating the stage error and a second stage for compensating for other system errors except for the stage error are performed in the present invention, and in order to obtain an optimal stitching result value, Is repeatedly performed.

In order to make a semiconductor chip on a wafer, a fine pattern is formed for each layer by using lithography, and these patterns are stacked to form a semiconductor chip formed of a plurality of thin film layers. (PR, Photo Resist) application, soft bake, exposure process, development, process, chemical etching process, PR removal, ion implantation, Chemical vapor deposition (CVD), metallization, chemical mechanical planarization (CMP), and the like. As a result of the complexity of such a process, uneven stresses are generated in the wafer each time it is subjected to each process, which is influenced by aligning the upper and lower thin layers, that is, the vertical alignment between the layers, which is defined as an overlay . In the past, when the minimum line width was larger than 100 nm, the displacement due to the process was not a large factor, but the circuit line width gradually decreased, reaching the nearest 10 nm, and the influence of the process displacement caused by such a process is increasing.

The overlay error indicating the vertical misalignment between the respective layers can be obtained by examining the alignment state of the pattern formed on the semiconductor substrate and the pattern formed in the current process by using an overlay key (overlay mark) by using the optical overlay measuring apparatus, And detects defects in the semiconductor process. An overlay process for measuring and inspecting alignment of fine patterns on a wafer substrate is performed by using an overlay process to confirm that the upper and lower thin film layer patterns are accurately aligned on three or more thin film layers formed of three or more thin film layers, mark, and the alignment state of the upper thin film layer and the lower thin film layer is confirmed.

This overlay process is based on the fact that the overlay mark is limited in each field, and various components causing the overlay error - [(1) Wafer level factor? Stage grid error, process induced wafer deformation, thermal deformation. (2) Field level factor? Reticle stage motion error, reticle write error, pellicle distortion, illumination mismatch, etc.) are combined and finally measured, it is difficult to accurately analyze the overlay error, It is very difficult to deduce the influence of

A technique for measuring wafer deformation induced during a process using a wafer geometry metric without an overlay mark and deriving an overlay error therefrom is disclosed in Prior Art 1 as disclosed in Patent Publication No. 10-2014-0069352 "New Wafer Geometry Metric " &Quot; Control overlay and semiconductor processing used ". Prior art 1 can acquire wafer geometry by using a technique for measuring wafer geometry such as a Fizeau interferometer and can calculate an overlay error value even without an overlay mark from it, thereby obtaining useful data (for example, overlay error And it is possible to acquire [derivation].

More specifically, in the method of providing wafer geometry metrics, obtaining a wafer shape value at each of a plurality of points on a wafer surface at a first processing level and at a further processing level; Wherein the wafer shape change value at each point using the obtained wafer shape value at each point of the first processing level and the further processing level, To correspond to changes in the wafer shape between the processing levels; The slope of the shape change value-the slope of the shape change value, by calculating the slope of the shape change at each point using the generated wafer shape change value at each of the points, Generating a set of slopes corresponding to slopes of the shape changes; Generating a set of values corresponding to slopes of the generated shape changes; Calculating a set of process tool correctors using the generated set of shape change value slopes; Generating a set of slope shape change residuals (SSCR) by calculating a slope of a shape change residual value at each of the points using the set of processing tool correction values; A plurality of metric analysis regions distributed over the entire surface of the wafer, said metric analysis regions each comprising at least one of said plurality of points; And generating one or more residual slope shape change metrics for each metric analysis region based on the one or more SSCRs in each metric analysis region.

Conventionally, a Fizeau wafer interferometer using a laser light source and an optical fiber was used to measure changes in wafer shape at a plurality of points on a wafer surface caused by local stress on the wafer surface in a semiconductor manufacturing process. In this case, the interferometer requires a reference plate having a diameter of 300 mm or more, which is larger than the wafer, for measurement of the wafer having a size of 300 mm, and a translucent bottom surface as the transparent material. Further, a collimator lens having a larger size than the wafer can also be used to generate a beam having a larger size than the wafer. Optical lenses and optical reference platforms larger in size than these wafers are expensive to manufacture due to their difficulty in making them highly flat. In addition, the probability of occurrence of an error in a process of a phase unwrapping algorithm or the like is increased when a region having a severe deformation of the wafer is measured due to a limited resolution.

Subaperture stitching is a method of attaching each image using a partial phase image obtained from a small aperture, instead of measuring the entire phase image of the measurement object at one time. This is because the size of the measurement object is smaller than the measurable range of the measurement tool It is applicable technology when large. Even if the size of the measurement object is large, since the interference fringes obtained from the small area of each part are processed and attached, it is possible to measure any extent even if the range in the lateral direction is widened. In addition, since a plurality of data obtained from the sub-aperture is used to attach, the resolution can be increased because more information can be obtained than data obtained with a single aperture.

However, instead of attaching the data of each data image when connecting the data obtained from each sub-aperture, instead of attaching the global coordinate system to the pixels of each image based on the position information obtained from the stage or the like, There is a great dependence on If the position information is inaccurate, the accuracy of the sub-aperture stitching will inevitably degrade.

Patent Publication No. 10-2014-0069352 (published on June 09, 2014), "Overlay and semiconductor processing control using new wafer geometry metric"

It is an object of the present invention to provide an optical system which is smaller in diameter than a wafer and is smaller in size than a wafer by using a reference flat and a collimator lens which are easier to manufacture and less expensive, And then the measured values are combined with each other to restore the size of the original wafer to a sub-aperture stitching method for measurement of geometric metrics.

Further, the present invention is a method for compensating for a system error (a stage error, a piston error, a tilt, aberration, and the like) that is involved in acquiring data in each sub-aperture in a stitching processor that matches measured sub- Suggest a plan.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a large diameter gauge (reference mirror) smaller in size than the large diameter wafer by measuring the surface shape change value of the large diameter wafer by using an interferometer, (A) a shape of the first sub-aperture through an interference fringe obtained from a first sub-aperture which is a partial region corresponding to the size of the small-diameter reference mirror among the small-diameter reference mirror and the large- (B) determining a second sub-aperture for causing the large-diameter wafer to move in a plane and interfering with the reference mirror, wherein the second sub-aperture is determined to overlap a portion of the first sub-aperture, Obtaining a shape value for the second sub-aperture through an interference fringe between the reference mirror and the second sub-aperture; and (c) N times to obtain the shape values for the N sub-apertures. The N number of sub-apertures obtained by performing the N times are performed N times so as to include all the regions of the large diameter wafer, (D) removing systematic errors that occur during movement of the wafer in each of the sub-apertures using the overlapping portions of the first through the N-th sub-apertures acquired through the step (c); And (e) calculating a shape value of the entire wafer by removing overlapping areas in the respective aperture sizes from which the system error has been removed.

(F) removing a stage error (position error) included in a system error in the step (d) and a tilt error; and (f-1) (F-2), determining the remaining minor bores as a comparative bore diameter, obtaining a portion of the portion overlapping the remaining minor bores in the reference bore with a reference rectangle, and (f-2) Determining a comparison rectangle smaller than the reference rectangle at a portion overlapping the reference rectangle among the minor bores; and (f-3) comparing the shape value of the comparison rectangle and the reference value of the reference rectangle while moving the comparison rectangle in the reference rectangle. Obtaining a similarity between the shape of the corresponding quadrangle and the shape of the corresponding quadrangle in the region of the quadrangle; and (f-4) comparing the obtained similarity to obtain the highest similarity value Shifting the position of the comparative quadrangle and the corresponding bore diameter of the comparative quadrangle to the position where the comparative quadrangle is obtained in the reference quadrangle to the position where the comparative quadrangle has been obtained to the highest position to match the coordinates of the comparative bore diameter to the coordinates of the reference bore diameter f-5) Repeating the steps (f-3) and (f-4) to match the coordinates of the remaining bores with the reference bores.

(G) The step of determining similarity of (f-3) includes comparing similarity by applying one of normalized cross correlation or sum of squared difference (SSD).

(B-1) In the step (b), the overlapping ratio of the first sub-aperture and the second sub-aperture is such that the area of the sub-aperture is in the range of 15 to 30% Overlap.

(H) removing a piston error (height error) included in the system error in the step (d) and a slope error; and (h-1) And the other remaining bore diameter is determined to be the comparator bore diameter, and the overlapping portion of the bore of the reference portion among the portions where the bore of the reference portion and the bore of the comparator portion overlap is determined as the reference overlapping surface without the piston error and the tilt error (H-2) determining a portion of the minor diameter of one of the comparator bores that overlaps the reference overlapping surface as a comparison overlapping surface with a piston error and a tilt error with respect to the reference overlapping surface; And (h-3) modeling the shape value of the comparison superimposed surface to include a piston error and a slope error based on the shape value of the reference superimposed surface, Measuring a piston error and a slope error of the comparison superimposed surface in comparison with a phase value; and (h-4) compensating the piston error and tilt error of the comparison superimposed surface by applying the measured piston error and tilt error. And (h-5) repeating the steps (h-2) and (h-4) to determine a comparative overlapping plane for the remaining comparator bores, And (h-6) compensating the piston error and tilt error of the overlapping surfaces of the remaining comparator bores based on the reference overlapping surface of the reference bore diameter, The remaining comparative aperture diameters are combined to calculate the surface shape value for one wafer.

Also, in the present invention, the process of measuring the piston error and the slope error of the comparison superimposed surface from the modeling equation applied in (h-3) is a least squares method for modeling the piston error and the slope error on the comparison superimposed surface, And measuring a piston error and an inclination error, and measuring an actual shape value of a comparative measurement surface to measure a piston error and an inclination error included in the actual shape value.

Further, in the present invention, the reference bore diameter is characterized in that the bore diameter data centered at the center of the wafer is referred to as a reference bore diameter, and a bore diameter obtained at the periphery of the reference bore diameter at the periphery thereof is taken as the diameter of the comparator portion .

According to another aspect of the present invention, there is provided a stitching method comprising: a first step of successively stitching a comparator bore located at upper, lower, left, and right sides of a reference bore, And a second step of successively stitching the minor bores.

The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

Prior to that, terms and words used in the present specification and claims should not be construed in a conventional and dictionary sense, and the inventor may properly define the concept of the term in order to best explain its invention It should be construed as meaning and concept consistent with the technical idea of the present invention.

As described above, according to the present invention, a reference flat and a collimator lens, which are easier to manufacture and less expensive than a diameter of a wafer, are used instead of optical components larger than the diameter of the wafer in the optical system configuration The shape of the large diameter wafer is measured inexpensively and conveniently by applying the sub-aperture stitching method for measuring the geometry metric to measure the sub-aperture smaller than the wafer, and then to integrate the measured values to the original wafer size There is an effect that can be done.

The present invention can also be applied to a stitching processor that matches measured diameters to compensate for system errors (stage errors, piston errors, tilt, aberrations, etc.) that are involved in acquiring data at each aperture, There is an effect of suggesting a new measurement method capable of minimizing errors.

FIG. 1 is a diagram illustrating a stitching algorithm process for combining wafer geometries acquired at respective aperture sizes into one geometry map and combining the same.
FIG. 2 is a diagram for explaining a process of processing raw data obtained in each aperture to acquire local wafer geometry.
3 is a view for explaining a method of covering the entire wafer by measuring a partial area of the wafer at each aperture.
Figure 4 illustrates the extraction of a rectangular area to set the range in the area between the overlapping sub-apertures to handle the step of correcting the stage error through comparison of pixel values between overlapping portions of sub-aperture data FIG.
5 is a diagram for describing a method of calculating a normalized cross-correlation to process a step of correcting a stage error through comparison of pixel values between overlapping portions of respective sub-aperture data .
Figure 6 is a conceptual illustration of the stitching of two bore diameters obtained using a wafer geometry measurement gauge (reference mirror).
Fig. 7 is a diagram showing an example of a sub-aperture area for measuring a wafer and a box area for extracting pixel values for calculating a correction value in an area overlapping the sub aperture; Fig.
8 is an example of a process of acquiring sub-aperture data during wafer full measurement and processing the stitching process. FIG. 8 is a view showing an example of processing an outer sub-aperture in order from the peripheral aperture with reference to the sub-aperture for measuring the center of the wafer to be.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. In this process, the thicknesses of the lines and the sizes of the components shown in the drawings may be exaggerated for clarity and convenience of explanation.

In addition, the terms described below are defined in consideration of the functions of the present invention, which may vary depending on the intention or custom of the user, the operator. Therefore, definitions of these terms should be made based on the contents throughout this specification.

In addition, the following embodiments are not intended to limit the scope of the present invention, but merely as exemplifications of the constituent elements set forth in the claims of the present invention, and are included in technical ideas throughout the specification of the present invention, Embodiments that include components replaceable as equivalents in the elements may be included within the scope of the present invention.

A preferred embodiment of the present invention comprises the steps of measuring (101) geometry for each sub-aperture as shown in Figure 1; Correcting (102) a stage error through pixel value comparison between overlapping portions of the obtained minor aperture data; Correcting (103) tilt, distortion, and piston error using the modeling function; Repeating steps 102 and 103 above to minimize residual error 104; And a step (105) of calculating a single wafer geometry metric by summing the sub-aperture data of the wafer geometry to obtain a final value.

In the present invention, by using a reference mirror smaller than the wafer, the size that can be measured at one time can be measured with a reference mirror size smaller than the wafer.

Therefore, the diameter of the wafer is measured to be smaller than that of the wafer, and then the result of the measurement is measured to measure the shape of the wafer. In the present invention, the small diameter measured is referred to as a diameter.

In this case, when the shape values for each sub-aperture are obtained, the shape values obtained in each sub-aperture are measured with different positions, heights and slopes between the sub-apertures, and there is an error between the sub-apertures. .

Here, the position error is an error caused when the wafer is moved on a plane on the stage, and hence is referred to as a stay error. The height error is referred to as a piston error since it is an error caused when the reference mirror moves in the optical axis direction.

Also, the tilt error is an error in which the slope of the measured shape value changes between each aperture, and this error is interpreted as a case where the error occurs due to an error occurring when the optical axis of the reference mirror moves.

  If the shape values of the wafers are acquired together without compensating for such errors, it is natural that the errors can not be loaded into the shape values of the wafers to obtain accurate wafer shape values.

Hereinafter, a process of compensating for the above error and acquiring the wafer shape value will be described.

An example of step 101 of obtaining the geometry for each sub-aperture is shown in Fig. An interference fringe is acquired 201 according to phase shifting and a wrapped phase map is acquired 202 by applying a phase shift algorithm. There are various algorithms such as a general four-step algorithm, a Carré algorithm, and a Hariharan algorithm. In the present invention, any algorithm can be applied, but in the embodiment, We will apply the Hari Haran algorithm.

[Equation 1]

  Where x (x, y) is the phase value of the arbitrary position (x, y) of the wafer and I is the brightness of the interference fringe obtained at the arbitrary position (x, y).

  Also, as shown in Equation (1), the phase values for the arbitrary position (x, y) are obtained by calculating the light intensity values of the interference fringes acquired by the camera, so that arbitrary positions (x, y) Is the corresponding value.

   Therefore, in the present invention, the arbitrary position of the wafer corresponds to one-to-one correspondence with the pixels of the camera, so that the position of the wafer and the pixels of the camera may be used in combination.

If a phase value is obtained for all the positions of the region through the values measured by the algorithm, a winding phase map 202 is created. At this time, there arises ambiguity of pi due to the characteristic of the tangent function. (Using the relationship of sine and cosine has ambiguity of 2π.) The phase spreading algorithm is applied as part of the process of eliminating this ambiguity. Various algorithms exist in the phase spreading algorithm, but in the present invention, IEEE GEOSCIENCE AND REMOTE SENSING LETTERS, VOL. 8, NO. 2, and MARCH 2011 by applying Heping Zhong et al., "An Improved Quality-Guided Phase-Unwrapping Algorithm Based on Priority Queue" And obtains the unfolded map 203.

Next, an example of a method of covering the entire wafer by measuring the partial area of the wafer with each aperture is described with reference to FIG. A circle 301 shown by a solid line in Fig. 3 represents a wafer to be measured, and a circle 302 indicated by a dotted line represents an area of the wafer obtained by each aperture. The area of the sub-aperture of the wafer to be measured is determined by considering the size of the wafer to be measured, the size of the sub-aperture to be measured, the width of the area overlapping the sub-aperture, and the like. The width of the overlapped area between the bores is preferably 15 to 30% of the width of the bore. If the width of the overlapped area is further expanded, the bore diameter stitching algorithm can be made more robust. However, .

Conversely, if the width of the overlapped region is reduced, the number of measurements may be reduced, but the error probability of the sub-aperture stitching algorithm may be higher.

A process 103 is performed to compensate for system errors (stage error, piston error, tilt, aberration, etc.) that accompany the acquisition of the data in each sub-aperture to stitch the sub-apertures together Stitching step. In the present invention, a step for compensating for a first stage error is first performed, a step for compensating for other system errors except a second stage error is performed, and the first and second The process is repeatedly performed.

Here, the stitching step is a step of combining the shape values of the respective bores, and obtaining the shape values of the wafers, and combining the shape values of the respective bores with each other using the overlapping values.

In a step 102 for compensating for a stage error, that is, a position error, the present invention extracts a region overlapping each aperture and calculates a cross-correlation or a sum of squared difference (SSD) in the extracted region, Stage error compensation is possible by examining the associations of sub-aperture data and modifying the global coordinates of the sub-aperture with the highest cross-correlation value or with the lowest SSD compensation position.

Figure 4 shows the step of correcting the stage error through comparison of pixel values between overlapping portions of sub-aperture data, showing the extraction of a rectangular area to set the range in the area between the overlapping sub-apertures will be.

In the present invention, for example, one of the two minor diameters measured in FIG. 4 is referred to as a reference minor diameter (hereinafter, referred to as a " reference diameter " 401, center circle), and another minor aperture is represented by a comparator aperture 402 (upper arc) to which the error is to be compensated. In order to minimize computational convenience and numerical error, a rectangular region is extracted from a common region of two bores. In the reference bore 401, a reference rectangle 403 is extracted and a comparison rectangle 404 is extracted in a sub-aperture to be compared, and the comparison rectangle is extracted to be accommodated in the reference rectangle.

     The reference rectangle and the comparison rectangle will be described in more detail with reference to FIG.

Box 501 represents a reference rectangle 403 having M x N pixels and is represented by a function f (x, y). Box 502 represents a comparison rectangle 404 having L x K pixels and is represented by a function w (x, y). The box 502 represented by the function w (x, y) is set by removing only a part of the edge frame in the area of the box 501 size. The degree of stage error is set by empirical values and is set to within 20 pixels in the present invention.

The normalized cross-correlation for comparing the similarity of the reference rectangle and the comparison rectangular region is calculated by the following equation.

&Quot; (2) "

here

Is an average value of shape values obtained at each pixel in the box region of the function w (x, y)

(i, j) is obtained from each pixel within the box (L x K size) corresponding to w (x, y) starting from i, j among the pixel values of the 501 box area f It is the average value of the shape values.

 Then, the normalized cross-correlation is obtained for w (x, y) and the corresponding box by using Equation (2) for the region 501 while sequentially increasing i and j.

 That is, when i and j increase sequentially, cross correlation is calculated every time, i, j, in which the cross-correlation value is the greatest among them, is regarded as an optimal position compensation value, Correct the value.

In this case, i and j are related to edge edge removal described above. That is, the values may be different according to the stage error tolerance. In the present invention, calculation is performed with a value within 20 pixels for each index.

As another example of the present invention, the calculation method of the SSD is as follows.

&Quot; (3) "

After the stage error, i.e., the position error, is compensated, a step is performed to compensate for other system errors such as piston error (height error), tilt, and aberration. Before describing the steps in which the actual stitching process is performed, a general bore diameter stitching method will be described first.

FIG. 6 is shown for conceptual explanations of two-bore stitching obtained using a wavefront measurement gauge (reference mirror) -fizeau interferometer.

601 and 602 are successively obtained, the region 603 overlapping between the two bores is present. At this time, each sub-aperture has data obtained from the ideal sub-aperture data (stage error (position error) - no system error)

(A height error (piston error), a tilt, an optical aberration, etc.) is added to the data

,

).

&Quot; (4) "

here

, The shape value measured at the minor diameter 601,

Is a shape value measured at the minor diameter 602,

and

Is a tilt coefficient in the x direction,

and

Is the y-direction tilt coefficient,

and

(Piston error) coefficient,

and

Means an optical aberration-related correction function.

and

May be set to include at least one term of Zernike polynomials such as focus, astigmatism, and comet aberration as in Equation (5), but in the present invention, .

&Quot; (5) "

In Equation (5)

Simply means a coefficient in each term.

If ideal sub-aperture data,

, It is usually difficult to separate ideal data from each other, and the method of calculating each coefficient by calculating the difference between the two diametrical data is used. (6)

&Quot; (6) "

6, for example, 601 in FIG. 6 is set as a reference subaperture with no error, and another sub-aperture (602 in FIG. 6) is defined as a comparison superimposed surface having an error with respect to the reference superposed surface, The reference overlapping plane is processed in such a manner that an error existing in the comparison overlapping plane is acquired and compensated for

Here is how to find the error.

&Quot; (7) "

In Equation (7)

Is the shape value for the reference superimposed surface without error,

Is a shape value on the comparison superimposed surface in which an error exists for the reference superimposed surface.

Here, a, b, and c can be obtained through simultaneous equations if there is at least three points (three pixels) of information overlapping in the reference and comparative overlapping planes. Considering the error, however, the calculation by the least square method through more pixel points may reduce the influence of the error. By using all the pixels in the overlapping area of the two aperture sizes, a, b, and c can be obtained from the above equation, and the component generated by the error is known. If this part is removed, stitching by error correction means is possible Loses.

Assuming that the number of pixels in the overlapping region is n, it can be expressed by the following equation (8).

&Quot; (8) "

If we obtain the solutions a, b, c from the determinant of equation (8), we can find the desired answer as a result.

Stitching each sub-aperture passes through stage error correction step 102 and other system error correction step 103, which may be repeated 104 to reduce the residual error value. Performing the stage error correction step after other system error correction may change the stage error correction value, i.e., the normalized cross-correlation value of the common area, which is minimized by repeating steps 102 and 103 .

Repeated steps to reduce the error residual value are performed when stitching each sub-aperture, and can generally be repeated two or three times.

7 shows an example of a sub-aperture area for measuring a wafer and a box area for pixel value extraction for calculating correction values in an area overlapping the sub aperture. As an embodiment of the present invention

And the peripheral diameter of the peripheral portion is preferentially stitched. Fig. 8 shows, as an embodiment thereof, stitching preferentially the diameter of the periphery of the measurement wafer, with the bore diameter measuring the center of the measurement wafer being the reference surface. Stitching between the respective aperture diameters is performed in steps 102, 103, and 104 of FIG. 1, and when the process is completed, the corrected value of the corresponding aperture is added to the global wafer geometry data having the global coordinate system.

Reference numeral 801 denotes a reference aperture for stitching. Reference numeral 802 denotes a sub-aperture to be corrected for stitching. Reference numeral 803 denotes a global wafer geometry having a coordinate system (global coordinate system) Means the minor diameter added to the data. The processes a, b, c, and d in FIG. 8 can proceed in any order, and concurrent processes through parallel calculation are also possible. In the step of stitching the sub-aperture corresponding to 802 in e, f, g, and h of FIG. 8, the portion overlapping with the sub-aperture of the center of the wafer Since it is difficult to perform the stitching steps 102 and 103, the stitching process is performed by comparing the two adjacent stitches.

This is computationally feasible in a manner in which a row representing the calculation with another minor aperture 802 is added in the determinant of equation (8), which means calculation of one minor aperture 801 and one minor aperture 802. That is, the stitching process can be performed through the calculation as in Equation (9).

&Quot; (9) "

 As shown in FIG. 8 (h), when the data for all the aperture sizes are added to the global wafer geometry data having the global coordinate system, the wafer geometry metric can be calculated as one example of the present invention. warp or bow, as well as variations in the geometry of various process wafers using wafer geometry metrics, such as in-plane distortion or out-of- plane distortion) of the overlay estimates.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes and modifications may be made therein without departing from the scope of the invention as defined by the appended claims. This is possible.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the same is by way of illustration and example only and is not to be construed as limiting the present invention. It is obvious that the modification or improvement is possible.

It is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

301: Wafer 302:
401: Reference aperture 402: Comparator aperture
403: Reference rectangle 404: Comparison rectangle
603: overlap area

Claims (8)

A method for measuring a surface shape change value of a large diameter wafer by applying an interferometer, wherein a small diameter gauge (reference mirror) smaller than the large diameter wafer is applied,
(a) obtaining a shape value for the first sub-aperture through an interference fringe obtained from the small aperture reference mirror and a first sub aperture that is a partial region corresponding to the size of the small aperture reference mirror among the large aperture wafer;
(b) determining a second sub-aperture for causing the large-diameter wafer to move in a plane and interfering with the reference mirror, the second sub-aperture being determined to overlap a portion of the first sub-aperture, Obtaining a shape value for the second sub-aperture through an interference pattern of the sub-aperture;
(c) performing the step (b) in succession N times to obtain shape values for N sub-apertures, wherein the N sub-apertures obtained by performing the N times are N times so as to include all areas of the large diameter wafer To obtain shape values for N minor diameters;
(d) removing systematic errors that occur during movement of the wafers in each sub-aperture using the overlapping portions of the first through the N-th sub-apertures acquired in the step (c);
(e) calculating shape values of the entire wafer by removing overlapping areas in each of the minor diameters from which the system error has been eliminated; A method of calculating the surface shape value for one wafer through The method according to claim 1,
(f) removing a stage error (position error) included in the system error in the step (d) and a tilt error
(f-1) one of the minor diameters is determined as a reference minor diameter, and the remaining minor diameters are determined as a comparative minor diameter, and a part of the portion overlapping the remaining minor diameters in the diameter of the reference portion As a reference rectangle;
(f-2) determining a comparison quadrangle smaller than the reference quadrangle at a portion overlapping the reference quadrangle among the remaining minor bores;
(f-3) obtaining the similarity between the shape value of the comparison rectangle and the shape value of the corresponding rectangle in the area of the reference rectangle while moving the comparison rectangle within the reference rectangle;
(f-4) comparing the acquired similarities to move the position of the comparison square to the position having the highest similarity to the position where the similarity is highest in the reference square, Aligning the coordinates of the minor aperture with the coordinates of the reference aperture;
(f-5) repeating the steps (f-3) and (f-4) to match the remaining sub-apertures with the coordinates of the reference aperture, thereby eliminating the stage error, How to calculate shape values 3. The method of claim 2,
(g) The step of determining the similarity of (f-3) is characterized in that similarities are compared by applying one of normalized cross correlation or SSD (Sum of Squared Difference) Method of calculating the surface shape value The method according to claim 1,
(b-1) In the step (b), the overlapping ratio of the first sub-aperture and the second sub-aperture is such that the area of the sub-aperture overlaps with the range of 15 to 30% A method of calculating a surface shape value for one wafer The method according to claim 1,
(h) removing the piston error (height error) included in the system error in the step (d) and the slope error
(h-1) determining one of the minor bores of each of the minor bores as a bore of the reference portion and determining the remaining bores of the other as the bore of the comparator portion, Determining a reference overlapping plane in which there is no piston error and tilt error;
(h-2) determining a portion of the minor diameter of one of the comparator bores overlapping the reference overlapping surface as a comparison overlapping surface with a piston error and a tilt error with respect to the reference overlapping surface;
(h-3) modeling the shape value of the comparison superimposed surface to include the piston error and the slope error based on the shape value of the reference superimposed surface, and comparing the modeled equation with the shape value of the actually measured comparison superimposed surface Measuring a piston error and a tilt error of the comparison superimposed surface;
(h-4) compensating the piston error and tilt error of the comparison superimposed surface by applying the measured piston error and tilt error;
(h-5) Repeating the steps (h-2) and (h-4) to determine a comparative overlapping plane for the remaining comparator bores. The piston error and slope Measuring and compensating for errors;
(h-6) the reference diameter and the remaining comparator diameters are combined in a state in which the piston error and the slope error of the comparative overlapped surfaces of the remaining comparative aperture diameters are compensated based on the reference superposed surface of the reference diameter, Method for calculating surface shape value 6. The method of claim 5,
In the process of measuring the piston error and the slope error of the comparative overlap plane from the modeling equation applied in (h-3), the equation modeled to include the piston error and the slope error on the comparison overlap plane is expressed as a piston error And measuring a slope error and a slope error included in the actual shape value by measuring an actual shape value of the comparative measurement surface, and calculating a surface shape value for one wafer 6. The method according to claim 2 or 5,
Wherein the diameter of the reference bore is a diameter of a reference bore centered on the center of the wafer and a bore diameter obtained at the periphery of the reference bore diameter at the periphery thereof is taken as the diameter of the comparator portion. Method for calculating surface shape value delete

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