KR20060058812A - Method for forming a gate pattern of flash memory device - Google Patents

Abstract

In the method of forming a gate pattern of a flash memory device, a conductive film pattern for a pre-floating gate is formed on a semiconductor substrate on which a field oxide film and a tunnel oxide film are formed, to partially expose the field oxide film. An etch stop layer, a dielectric layer, and a conductive gate control layer are formed on the entire structure of the substrate. A conductive gate pattern, an etch stop layer pattern for partially exposing the upper surface of the tunnel oxide layer by sequentially patterning the control gate conductive layer, the dielectric layer, the etch stop layer, and the pre-floating gate conductive layer pattern; The dielectric film pattern and the conductive film pattern for the control gate are sequentially formed. Accordingly, when the dielectric layer is etched, the substrate may be protected by preventing the pre-floating conductive layer pattern from being etched by the etch stop layer.

Description

Gate pattern formation method of flash memory device {METHOD FOR FORMING A GATE PATTERN OF FLASH MEMORY DEVICE}

1 is a cross-sectional view illustrating a gate pattern forming method of a flash memory device according to a conventional method.

2 is a plan view illustrating a portion of a flash memory device according to an exemplary embodiment of the present invention.

3 and 4 are cross-sectional views illustrating a method of forming a gate pattern of a flash memory device when the line II ′ of FIG. 2 is cut.

5 is a perspective view illustrating a gate pattern forming method of a flash memory device according to an exemplary embodiment of the present invention.

6 through 8 are cross-sectional views illustrating a method of forming a gate pattern of a flash memory device when the II-II ′ line of FIG. 2 is cut.

9 to 13 are cross-sectional views illustrating an application example of a gate pattern of a flash memory device when the II-II ′ line of FIG. 2 is cut.

Explanation of symbols on the main parts of the drawings

200: semiconductor substrate 201, 206: bit line

202, 207: string select line                 

203a, 203b: string select transistor positions

204 and 208: word lines 205a and 205b: cell transistor positions

210: field oxide film 215: tunnel oxide film

240: conductive film pattern for the pre-floating gate

240a, 240b: conductive film pattern for floating gate

250: etch stop film 250a, 250b: etch stop film pattern

255: dielectric film 255a, 255b: dielectric film pattern

260: conductive film for control gate 260a, 260b: conductive film pattern for control gate

270a and 270b: first hard mask film pattern

270c and 270d: second hard mask film pattern

280: photoresist pattern 285a, 285b: first opening

285c and 285d: second opening 290: insulating film

295a: first butting contact 295b: second butting contact

C: cell area P: surrounding area

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a gate pattern of a flash memory device.

The nonvolatile memory device, which is one of the semiconductor memory devices, is characterized in that stored information does not disappear even when power is not supplied. Therefore, the nonvolatile memory device is widely used in computers, memory cards, and the like. The flash memory device, which is one of the nonvolatile memory devices, has a simple structure, low manufacturing cost, and no need for a refresh operation for long-term data storage. Among the nonvolatile memory devices, the NAND type flash memory device is widely used in a highly integrated flash memory device because it is easier to increase the degree of integration as compared to the NOR type flash memory device.

1 is a cross-sectional view illustrating a gate pattern forming method of a conventional flash memory device.

Referring to FIG. 1, a tunnel oxide film 115 is formed on a semiconductor substrate 100. Subsequently, a conventional shallow trench isolation (STI) process is performed to define an electrically activated active region to form a field oxide layer 120 on the substrate 100. A floating gate polysilicon layer 130 that partially exposes an upper surface of the field oxide layer 210 is formed on the tunnel oxide layer and the field oxide layer 120. A dielectric layer 140 may be uniformly formed on the exposed field oxide layer 120 and the floating silicon polysilicon layer 130. The polysilicon layer 150 for the control gate is formed on the dielectric layer 140. In general, the dielectric layer 140 has a structure in which a first oxide film (not shown), a nitride film (not shown), and a second oxide film (not shown) are sequentially stacked (hereinafter, referred to as an “ONO film”). .

 In the conventional flash memory device formed as described above, an ONO film is used as the dielectric film 140 that insulates the floating gate polysilicon film 130 and the control gate polysilicon film 150. However, when the ONO film is used in a flash memory device according to a conventional 63 nm design rule, the interval between neighboring floating gate polysilicon films 130 after the ONO film is deposited is 10 nm. It is only. Therefore, when using an ONO film having the same thickness as described above in a flash memory device having a design rule of 60 nm or less, the distance between the neighboring floating gate polysilicon layers 130 is expected to be less than 0 nm. The structure of self-aligning the silicon film 130 becomes impossible, and as a result, the coupling ratio is drastically reduced. Therefore, in order to prevent the coupling ratio from decreasing, the dielectric layer 140 needs to use a high-k film having a higher dielectric constant than that of the conventional ONO.

However, the biggest problem in the case of using the high dielectric film is that the floating gate polysilicon layer 130 may be etched when the high dielectric film is etched to damage the silicon substrate in the active region. For example, when Al ₂ O ₃ is used as the high dielectric film material, an etching selectivity ratio of polysilicon: Al ₂ O ₃ obtained by using BCl ₃ as an etching solution is about 2: 1, so that more polysilicon is etched. Here, although the thickness of the Al ₂ O ₃ thin film used in place of the conventional ONO film is approximately 300 GPa, considering the overetch rate of 100%, the loss of the polysilicon film for the floating gate occurs 300 GPa or more. Therefore, since the thickness of the polysilicon film for floating gate used in the flash memory device of the conventional 63nm design rule is only 400 Å, the silicon substrate in the active region may be damaged when the Al ₂ O ₃ high dielectric film is etched.

In addition, high-k films have poor leakage current characteristics compared to ONO films. For example, when the 100O thick ONO film is compared with the AlO film, the leakage current of the AlO film is one order or more larger than that of the ONO film. Therefore, in order to satisfy the breakdown voltage (BV) when using the high dielectric film, the thickness of the thin film must be increased, which in turn causes a reduction in the coupling ratio.

Therefore, in order to solve the above problems, it is necessary to improve the stacked structure of the multilayer thin film forming the gate pattern of the conventional flash memory device.

An object of the present invention for solving the above problems is to provide a gate pattern forming method of a flash memory device for improving the multilayer thin film structure of the gate pattern.

In order to achieve the above object, a gate pattern forming method of a flash memory device according to an exemplary embodiment of the present invention may include a conductive film for a pre-floating gate that partially exposes the field oxide film on a semiconductor substrate on which a field oxide film and a tunnel oxide film are formed. Follow the steps to form a pattern. An etching stop layer is formed on the conductive layer pattern for the pre-floating gate and the exposed field oxide layer to reduce damage to the substrate due to an etching process. A step of forming a dielectric film and a conductive film for a control gate on the etch stop layer is performed. The control gate conductive layer is etched to expose the dielectric layer, thereby forming a control gate conductive layer pattern. And sequentially forming the dielectric layer, the etch stop layer, and the conductive layer pattern for the pre-floating gate to sequentially form the dielectric layer pattern, the etch stop layer pattern, and the conductive layer pattern for the floating gate.

According to an embodiment of the present invention as described above, by forming the etch stop layer having excellent etching resistance with respect to the floating gate conductive film between the dielectric film and the floating gate conductive film for etching the floating gate for the dielectric film Etching of the conductive film may be minimized to prevent damage to the silicon substrate in the active region. In addition, since the etch stop layer has better insulating properties than the dielectric layer, it is possible to prevent the dielectric layer from being formed inevitably thick in order to secure a breakdown voltage. Thus, even when the dielectric film is formed thin, the capacitance between the conductive film pattern for the floating gate and the dielectric film pattern is increased, thereby increasing the coupling ratio.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a plan view illustrating a portion of a flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 2, in the flash memory device, a point where the bit line 201 and the string select line 202 intersect in the cell region C is a string select transistor position 203a, and the bit line 201 The point at which the word lines 204 intersect is the cell transistor position 205a. In the peripheral area P, the point where the bit line 206 and the string select line 207 intersect is the string select transistor position 203b, and the point where the bit line 206 and the word line 208 intersect is Cell transistor position 205b.

3 and 4 are cross-sectional views illustrating a method of forming a gate pattern of a flash memory device when the line II ′ of FIG. 2 is cut.

Referring to FIG. 3, a tunnel oxide film 215 is formed on a semiconductor substrate 200 and polysilicon is coated. By a conventional shallow trench isolation (STI) process, a portion of the semiconductor substrate 200 is etched from the top to define an electrically active active region to form a trench (not shown). do. The active region is defined by applying a device isolation oxide film to the entire structure including the trench to fill the inside of the trench, and then performing chemical mechanical polishing (CMP) to form the field oxide film 210.

A conductive film for a floating gate (not shown) is deposited to a predetermined thickness on the field oxide film 210 and a thin film formed of polysilicon. The conductive film for the floating gate may be formed by depositing polysilicon. A photoresist pattern (not shown) is formed on the floating gate conductive film by applying a normal photolithography process. The photoresist pattern is formed to partially expose the conductive film for the floating gate positioned on the field oxide layer 210. Subsequently, the upper surface of the field oxide layer 210 is partially exposed by etching the exposed floating gate conductive layer using the photoresist pattern as an etching mask. The etched floating gate conductive film is converted into a pre-floating gate conductive film pattern 240.

Referring to FIG. 4, the etch stop layer 250 may be uniformly formed on the conductive layer pattern 240 for the pre-floating gate including the exposed field oxide layer 210.

The etch stop layer 250 may be formed in various thicknesses according to the use or characteristics of the device, but according to the present exemplary embodiment, the etch stop layer 250 may be formed to a thickness of 10 to 300 Å. In addition, the etch stop layer 250 is formed of a material having a higher etching resistance than the conductive layer pattern 240 for the pre-floating gate under an etching condition for etching the subsequent dielectric layer 255. Specifically, the etch stop layer 250 may be formed of a material having an etching resistance of 1.4 to 2.4 times that of the pre-floating gate conductive layer pattern 240 under etching conditions for etching the dielectric layer 255. Do.

The etch stop layer 250 may be formed by depositing silicon nitride (eg, Si ₃ N _4, etc.) or silicon oxide (eg, SiO _2, etc.).

In addition, the etch stop layer 250 may nitride the surface of the pre-floating gate conductive layer pattern 240 and the exposed field oxide layer 210 to perform nitriding on the pre-floating gate conductive layer pattern 240 and It may be formed by converting the upper surface of the exposed field oxide film 210 to silicon nitride. Examples of the nitriding treatment include plasma nitriding treatment and the like. Specifically, the plasma silencing process is performed by mounting the substrate 200 on which the conductive film pattern 240 for the pre-floating gate is formed in a vacuum chamber, and then nitrogen (N ₂ ), ammonia (NH ₃ ), or the like. Is applied to a vacuum chamber and an RF field is applied to energize the gas into a plasma state. At this time, helium (He) is used as a carrier gas. Remote plasma, decoupled plasma, slot plane antenna, or electron cyclotron resonance may be used as a plasma source in the plasma nitridation step.

In addition, the etch stop layer oxidizes the surfaces of the pre-floating gate conductive layer pattern 240 and the exposed field oxide layer 210 to oxidize the pre-floating gate conductive layer pattern 240 and the exposed field. It can be formed by converting the upper surface of the oxide film 210 to silicon oxide. Examples of the oxidation treatment include rapid thermal oxidation, furnace thermal oxidation, plasma oxidation, and the like. In the case of using the rapid thermal oxidation, the substrate 200 including the conductive film pattern 240 for the pre-floating gate is used at a temperature of 800 to 950 ° C. while maintaining a gas pressure of several Torr. Oxidize for seconds.

A dielectric layer 255 is uniformly formed on the etch stop layer 250. The dielectric layer 255 may be formed of an ONO layer having a multilayer thin film structure in which a first oxide layer, a nitride layer, and a second oxide layer are stacked, but according to the present exemplary embodiment, the dielectric layer 255 is formed of a high-k material. Examples of the high dielectric material include AlO, Al ₂ O ₃ , HfO ₂ , HfSi _x O _y , ZrO ₂ , and the like. According to the present preferred embodiment, Al ₂ O ₃ is preferably used.

A control gate conductive layer 260 is deposited on the etch stop layer 250. The control gate conductive layer 260 may be formed by depositing polysilicon.

5 is a perspective view illustrating a gate pattern forming method of a flash memory device according to an exemplary embodiment of the present invention.

Referring to FIG. 5, a hard mask layer (not shown) is formed on the conductive layer 260 for the control gate. Subsequently, by patterning the hard mask layer using a conventional photolithography process so that the top surface of the control gate conductive layer 260 is partially exposed, the first hard mask layer pattern is formed on the conductive layer 260 for the control gate. 270a and 270b are formed.

6 through 8 are cross-sectional views illustrating a method of forming a gate pattern of a flash memory device when the II-II ′ line of FIG. 2 is cut.

Referring to FIG. 6, the exposed control gate conductive layer 260 is etched using the first hard mask layer patterns 270a and 270b as an etching mask. By etching, the control layer conductive layer patterns 260a and 260b are formed on the dielectric layer 255 to partially expose an upper surface of the dielectric layer 255.

Referring to FIG. 7, the exposed dielectric layer 255 is etched by using the first hard mask layer patterns 270a and 270b and the control layer conductive layer patterns 260a and 260b as an etching mask. The exposed etch stop layer 250 is etched. By the etching, the etch stop layer patterns 250a and 250b and the dielectric layer pattern partially exposing the top surface of the pre-floating gate conductive layer pattern 240 on the pre-floating gate conductive layer pattern 240. (255a, 255b) are formed sequentially.

The conductive layer pattern 240 for the pre-floating gate has a higher etching rate than the dielectric layer patterns 255a and 255b, and thus, when the dielectric layer 255 is etched, the conductive layer pattern for the pre-floating gate is etched. The pattern 240 may be etched. However, the etch stop layer 250 is positioned between the dielectric layer 255 and the conductive layer pattern 240 for the pre-floating gate to prevent the pre-floating gate conductive layer pattern 240 from being etched. This is because the etch stop layer 250 has a lower etch rate than that of the dielectric layer 255, and the etch resistance is significantly superior to that of the conductive layer pattern 240 for the pre-floating gate. Therefore, the etch stop layer 250 may prevent the substrate 200 from being damaged by preventing the pre-floating conductive layer 240 from being etched.

Referring to FIG. 8, the first hard mask layer patterns 270a and 270b, the control layer conductive layer patterns 260a and 260b, the dielectric layer patterns 255a and 255b and the etch stop layer patterns 250a and 250b are etched. The exposed conductive layer pattern 240 for the pre-floating gate is etched using a mask. By etching, the conductive layer patterns 240a and 240b for floating gates are formed on the tunnel oxide layer 215 to partially expose an upper surface of the tunnel oxide layer 215. Accordingly, the floating gate conductive layer patterns 240a and 240b, the etch stop layer patterns 250a and 250b, the dielectric layer patterns 255a and 255b and the control gate conductive layer patterns 260a and 260b sequentially formed on the tunnel oxide layer. ) Forms a gate pattern of the flash memory device.

Etch Tolerance Evaluation by Thin Film

As above, Al ₂ O ₃ A high dielectric material is used as the dielectric film 255 and Si ₃ N ₄ or In order to evaluate the possibility of using a material of SiO ₂ as the etch stop layer 250, the conductive layer pattern 240 and the etch stop layer 250 for the pre-floating gate under an etching condition with respect to the dielectric layer 255. ) And the results of comparing the etching resistance of each thin film on the dielectric film 255 are shown in the table below. Here, the etching equipment used Applied Materials DPS, and the etching chemical used a chemical of BCl ₃ .

Dielectric Film (Al ₂ O ₃ ) Conductive film pattern for pre-floating gates (polysilicon) Etch stopper (Si ₃ N ₄ ) Etch stopper (SiO ₂ ) Etch Rate (Å / min) 600 1189 493 845 Selectivity to Al ₂ O ₃ (comparative film: Al ₂ O ₃ ) 1: 1 2: 1 0.8: 1 1.4: 1

Looking at the comparison table, in the etching conditions for the dielectric layer 255 of Al ₂ O ₃ , the etch stop layer of the Si ₃ N ₄ material compared to the conductive film pattern 240 for the pre-floating gate of polysilicon material ( 250) showed 2.4 times better etching resistance to the etching chemicals for etching the dielectric layer 255, and 1.4 times higher the etch stop layer 250 of the SiO ₂ material. In particular, in the case of the etch stop layer 250 of the Si ₃ N ₄ material, the dielectric film 255 of the Al ₂ O ₃ material Etch rate was lower than. Accordingly, by forming the etch stop layer 250 of the Si ₃ N ₄ material between the dielectric film 255 of the Al ₂ O ₃ material and the conductive film pattern 240 for the pre-floating gate of the polysilicon material, Since the conductive film pattern 240 for the pre-floating gate is prevented from being etched, the silicon substrate may be damaged. In addition, since the leakage current characteristics of the etch stop layer 250 of the Si ₃ N ₄ or SiO ₂ material is excellent compared to the dielectric film 255 of the Al ₂ O ₃ material, inherently formed inherently thick to secure a conventional breakdown voltage. The dielectric layer 255 of the entire material may be thinly formed. As a result, the coupling ratio may be improved by increasing the capacitance between the floating gate conductive layer patterns 240a and 240b and the dielectric layer patterns 255a and 255b.

The gate pattern formed as described above may be utilized in various ways, examples of which are illustrated in FIGS. 9 to 13. 9 to 13 are cross-sectional views illustrating a method of forming a butt contact by using a gate pattern of a flash memory device when the II-II ′ line of FIG. 2 is cut.

Referring to FIG. 9 as a subsequent process according to FIG. 8, the first string select gate electrode of the string select transistor position 203a of the cell region C and the string select transistor position 203b of the peripheral region P of FIG. Since the ground select gates of each region including the second string select gate electrode do not play a role of storing data, the conductive film patterns 240a and 240b for the floating gate and the conductive film patterns 260a and 260b for the control gate. Is electrically connected.

Accordingly, a photoresist (not shown) is coated on the entire structure on which the gate pattern is formed, and the photoresist pattern 280 is formed to expose the upper portions of the string selection gate and the ground selection gate electrode. By etching the first hard mask layer patterns 270a and 270b exposed below using the photoresist pattern 280 as an etching mask, the second hard mask layer pattern ( 270c and 270d).

Referring to FIG. 10, the photoresist pattern 280 existing on the second hard mask layer patterns 270c and 270d is removed by a conventional ashing and stripping process. By the above process, the second hard mask film patterns 270c and 270d are exposed in the cell region C and the peripheral region P. FIG.

Referring to FIG. 11, first openings 285a and 285b are formed by anisotropically etching the control gate conductive layer patterns 260a and 260b exposed below using the second hard mask layer patterns 270c and 270d. do.

Referring to FIG. 12, the dielectric layer patterns 255a and 255b and the etch stop layer patterns 250a and 250b exposed through the first openings 285a and 285b are anisotropically etched to form the conductive layer patterns 240a and Second openings 285c and 285d are formed to partially expose 240b). As mentioned above, the etch stop layer patterns 250a and 250b are disposed between the dielectric layer patterns 255a and 255b and the floating gate conductive layer patterns 240a and 240b. Prevents 240a and 240b from being etched.

Referring to FIG. 13, an insulating film 290 is formed on the entire structure including the second openings 285c and 285d. Subsequently, a portion of the insulating layer 290 is etched by a conventional photolithography process so as to form the second openings 285c and 285d again. Thus, by the etching, the floating gate conductive layer patterns 240a and 240b are partially exposed. The exposed second openings 285c and 285d are filled with a conductive material to form first and second butting contacts 295a and 295b in the cell C and the peripheral region P, respectively.

According to one preferred embodiment of the present invention, the etch stop layer having excellent etching resistance to the conductive layer pattern for the pre-floating gate is formed between the dielectric layer and the conductive layer pattern for the pre-floating gate. Thus, when the dielectric layer is etched, the conductive layer pattern for the pre-floating gate may be prevented from being etched to prevent damage to the silicon substrate in the active region. In addition, since the etch stop layer has superior insulating properties as compared to the dielectric layer, it is not necessary to increase the thickness of the dielectric layer in order to secure a breakdown voltage as in the related art, thereby improving the coupling ratio.

Although described above with reference to the preferred embodiment of the present invention, those skilled in the art various modifications and variations of the present invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (9)

Forming a conductive film pattern for a pre-floating gate that partially exposes the field oxide film on a semiconductor substrate having a field oxide film and a tunnel oxide film formed thereon; Forming an etch stop layer on the conductive layer pattern for the pre-floating gate and the exposed field oxide layer to reduce damage to the substrate due to an etching process; Forming a dielectric layer and a conductive layer for a control gate on the etch stop layer; And Etching the control gate conductive layer to expose the dielectric layer to form a conductive gate pattern; And And sequentially patterning the dielectric layer, the etch stop layer, and the conductive layer pattern for the pre-floating gate, to sequentially form the dielectric layer pattern, the etch stop layer pattern, and the conductive layer pattern for the floating gate. Method of forming a gate pattern. The gate pattern forming method of claim 1, wherein the etch stop layer is formed of a material having an etching resistance higher than that of the conductive layer pattern for the pre-floating gate under an etching condition of etching the dielectric layer. The gate of the flash memory device of claim 1, wherein the etch stop layer is formed of a material having an etch resistance of 1.4 to 2.4 times that of the conductive layer pattern for the pre-floating gate under an etching condition of etching the dielectric layer. Pattern formation method. The gate pattern forming method of claim 1, wherein the etch stop layer is formed by depositing silicon nitride or silicon oxide. The method of claim 1, wherein the etch stop layer, And nitriding the surface of the conductive film pattern for the pre-floating gate and the exposed field oxide film, thereby converting the upper surface of the conductive film pattern for the pre-floating gate and the exposed field oxide film to silicon nitride. A method of forming a gate pattern of a flash memory device.  The method of claim 1, wherein the etch stop layer, And the surface of the conductive film pattern for the pre-floating gate and the exposed field oxide is oxidized to convert the upper surface of the conductive film pattern for the pre-floating gate and the exposed field oxide into silicon oxide. A method of forming a gate pattern of a flash memory device. The gate pattern forming method of claim 1, wherein the etch stop layer is formed to a thickness of about 10 to about 300 microns. The gate pattern forming method of claim 1, wherein the dielectric layer is formed of a high-k material. The gate pattern forming method of claim 8, wherein the high dielectric material is Al ₂ O ₃ .

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