KR20060057654A - Thin film transistor array panel and liquid crystal display - Google Patents

Abstract

The liquid crystal display according to the exemplary embodiment of the present invention includes a thin film transistor having a drain electrode and a semiconductor, a drain electrode connected to a gate line, a data line insulated from and intersecting the gate line, and a gate electrode and a source electrode of the data line. A first pixel electrode and a first pixel connected directly to the drain electrode and a passivation layer covering the capacitive coupling electrode, the gate line, the data line, and the thin film transistor, each of which includes at least one bent portion and is connected to A thin film transistor array panel including a pixel electrode separated from the electrode and overlapping the capacitive coupling electrode, the pixel electrode including a second pixel electrode capacitively connected to the first pixel electrode, and facing the thin film transistor array panel. It includes a common electrode display panel formed.

LCD, vertical alignment, polarizer, coupling electrode, coupling capacitance

Description

Thin film transistor array panel and liquid crystal display including the same {THIN FILM TRANSISTOR ARRAY PANEL AND LIQUID CRYSTAL DISPLAY}

1 is a layout view of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment of the present invention.

2 is a layout view of a common electrode panel for a liquid crystal display according to an exemplary embodiment of the present invention.

3 is a layout view of a liquid crystal display according to an exemplary embodiment of the present invention including the display panel of FIGS. 1 and 2.

4 is a cross-sectional view of the liquid crystal display of FIG. 3 taken along the line IV-IV ';

5 is a circuit diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

6 is a layout view illustrating a structure of a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 7 is a cross-sectional view of the liquid crystal display of FIG. 6 taken along the line VII-VII ′. FIG.

8 is a layout view illustrating a structure of a liquid crystal display according to another exemplary embodiment of the present invention.                 

FIG. 9 is a cross-sectional view of the liquid crystal display of FIG. 8 taken along the line IX-IX '. FIG.

Explanation of reference numbers

11, 21: alignment film 12, 22: polarizing plate

100, 200: display panel 110, 210: insulating substrate

121: gate line 124: gate electrode

131: sustain electrode lines 133a, 133b, 133c, 133d: sustain electrode

140: gate insulating film 151, 154: semiconductor

161, 163, 165: ohmic contacts 171, 179: data line 173: source electrode 175: drain electrode

176 capacitive coupling electrode 180 insulating film

181, 182, and 185: contact holes 190a and 190b: pixel electrode 220: light blocking member 250: overcoat

270: common electrode 3: liquid crystal layer 310: liquid crystal molecules

The present invention relates to a thin film transistor array panel and a liquid crystal display including the same, and more particularly, to a thin film transistor array panel for dividing a pixel into multiple domains and a liquid crystal display including the same.

The liquid crystal display is one of the most widely used flat panel display devices. The liquid crystal display includes two display panels on which field generating electrodes, such as a pixel electrode and a common electrode, are formed, and a liquid crystal layer interposed therebetween. Is applied to generate an electric field in the liquid crystal layer, thereby determining the orientation of liquid crystal molecules in the liquid crystal layer and controlling the polarization of incident light to display an image.

Among them, the vertical alignment mode liquid crystal display in which the long axis of the liquid crystal molecules are arranged perpendicular to the upper and lower display panels without an electric field applied to the display panel is high in contrast ratio and easy to implement a wide viewing angle.

Means for implementing a wide viewing angle in a vertical alignment mode liquid crystal display include a method of forming a cutout in the field generating electrode and a method of forming a protrusion on the field generating electrode. Since the direction in which the liquid crystal molecules are inclined by the cutout and the protrusion can be determined, the wide viewing angle can be secured by dispersing the inclination directions of the liquid crystal molecules in various directions.

However, the liquid crystal display of the vertical alignment type has a problem in that the side visibility is inferior to the front visibility.

In addition, in the vertically aligned liquid crystal display, the long axes of the liquid crystal molecules are vertically arranged without applying a voltage, thereby ensuring a high contrast ratio to minimize leakage of light.

However, when the arrangement of the liquid crystal molecules is distorted due to the step difference of the signal line, a problem arises in that the luminance increases when displaying a dark color.

 The technical problem to be achieved by the present invention is to implement a thin film transistor array panel of a multi-domain liquid crystal display device having excellent visibility and a liquid crystal display device including the same.

Another object of the present invention is to provide a thin film transistor array panel capable of securing a high contrast ratio by blocking light leakage and a liquid crystal display including the same.

In order to solve this problem, the present invention divides the pixel electrode into at least two or more sub pixel electrodes and combines the sub pixel electrodes in a capacitive manner so that different potentials are applied. In this case, the coupling electrode for capacitive coupling has a boundary line parallel or perpendicular to the polarization axis direction of the polarizing plate.

The thin film transistor array panel according to the exemplary embodiment of the present invention is a thin film transistor having a drain electrode and a semiconductor, a drain electrode connected to a gate line, a data line insulated from and intersecting the gate line, and a gate electrode and a source electrode of the data line. A first pixel electrode and a first pixel connected directly to the drain electrode and a passivation layer covering the capacitive coupling electrode, the gate line, the data line, and the thin film transistor, each of which includes at least one bent portion and is connected to And a pixel electrode separated from the electrode and including a second pixel electrode overlapping the capacitive coupling electrode and capacitively connected to the first pixel electrode.

The coupling electrode is preferably formed by alternately connecting a first portion parallel to the gate line and a second portion parallel to the data line.

It is preferable to further include a storage electrode line having a storage electrode overlapping at least one of the pixel electrode, the coupling electrode and the drain electrode to form a storage capacitor.

The semiconductor may be linear along the data line, and the semiconductor except for the source electrode and the drain electrode may have the same planar shape as the data line and the drain electrode.

The liquid crystal display according to the exemplary embodiment of the present invention includes a thin film transistor having a drain electrode and a semiconductor, a drain electrode connected to a gate line, a data line insulated from and intersecting the gate line, and a gate electrode and a source electrode of the data line. A first pixel electrode and a first pixel connected directly to the drain electrode and a passivation layer covering the capacitive coupling electrode, the gate line, the data line, and the thin film transistor, each of which includes at least one bent portion and is connected to A thin film transistor array panel including a pixel electrode separated from the electrode and overlapping the capacitive coupling electrode, the pixel electrode including a second pixel electrode capacitively connected to the first pixel electrode, and facing the thin film transistor array panel. It includes a common electrode display panel formed.

The coupling electrode may be formed by alternately connecting a first portion parallel to the gate line and a second portion parallel to the data line, and may further include a polarizer attached to an outer surface of the thin film transistor array panel and the common electrode display panel.

It is preferable that the transmission axis of the polarizing plate is parallel or perpendicular to the first and second portions.

DETAILED DESCRIPTION Embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.

In the drawings, the thickness of layers, films, panels, regions, etc., are exaggerated for clarity. Like parts are designated by like reference numerals throughout the specification. When a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the other part being "right over" but also another part in the middle. On the contrary, when a part is "just above" another part, there is no other part in the middle.

Next, a thin film transistor array panel and a liquid crystal display including the same according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.

First, a liquid crystal display according to an exemplary embodiment of the present invention will be described in detail with reference to FIGS. 1 to 5.

FIG. 1 is a layout view illustrating a structure of a thin film transistor array panel for a liquid crystal display according to an exemplary embodiment. FIG. 2 is a layout view illustrating a structure of a common electrode display panel for a liquid crystal display according to an exemplary embodiment. 3 is a layout view illustrating a structure of a liquid crystal display device including the thin film transistor array panel of FIG. 1 and the thin film transistor array panel of FIG. 2, and FIG. 4 is a cross-sectional view taken along line IV-IV ′ of the liquid crystal display of FIG. 3. 5 is a circuit diagram showing the configuration of one pixel in the liquid crystal display according to the exemplary embodiment of the present invention.                     

The liquid crystal display according to the present exemplary embodiment includes a thin film transistor array panel 100, a common electrode display panel 200, and a liquid crystal layer 3 interposed between the two display panels 100 and 200.

First, the thin film transistor array panel 100 will be described in detail with reference to FIGS. 1, 3, and 4.

A plurality of gate lines 121 and a plurality of storage electrode lines 131 are formed on the insulating substrate 110.

The gate lines 121 mainly extend in the horizontal direction and are separated from each other, and transmit gate signals. Each gate line 121 includes a plurality of protrusions constituting the plurality of gate electrodes 124 and an end portion 129 having a large area for connecting another layer or an external device.

Each storage electrode line 131 extends mainly in the horizontal direction and is disposed between the gate lines 121 adjacent to each other. Each storage electrode line 131 extends in the horizontal direction and includes a plurality of sets of branches forming the first to fourth storage electrodes 133a, 133b, 133c, and 133d. The first storage electrode 133a and the second storage electrode 133b extend in the vertical direction, and the third and fourth storage electrodes 133c and 133d extend in an oblique direction and are disposed at both ends of the second storage electrode 133b. It is connected. The third and fourth sustain electrodes 133c have inverted symmetry with respect to the center line between two adjacent gate lines 121. A predetermined voltage such as a common voltage applied to the common electrode 270 of the common electrode display panel 200 of the liquid crystal display device is applied to the sustain electrode line 131.                     

The gate line 121 and the storage electrode line 131 are preferably made of aluminum-based metal, silver-based metal, copper-based metal, molybdenum-based metal, chromium, titanium, tantalum, or the like, and have a single film structure or a multilayer film structure. Can be. It may include a multilayer film, for example, two films of different physical properties, that is, a lower film and an upper film thereon. One conductive film is a low resistivity metal such as aluminum (Al) or an aluminum alloy such as aluminum (Ag) or a silver alloy such as silver (Ag) or silver alloy to reduce signal delay or voltage drop. It may be made of a copper-based metal such as copper (Cu) or a copper alloy. In contrast, other conductive films have excellent contact properties with other materials, particularly indium tin oxide (ITO) and indium zinc oxide (IZO), such as chromium, molybdenum (Mo), molybdenum alloys, tantalum (Ta), or titanium (Ti). ) And the like. Good examples of the two conductive films include chromium / aluminum-neodymium (Nd) alloys or molybdenum or molybdenum alloys / aluminum alloys.

In addition, the side surfaces of the gate line 121 and the storage electrode line 131 are inclined with respect to the surface of the substrate 110, and the inclination angle is preferably about 30-80 °.

A gate insulating layer 140 made of silicon nitride (SiN _x ) is formed on the gate line 121 and the storage electrode line 131.

A plurality of linear semiconductors 151 made of hydrogenated amorphous silicon (amorphous silicon is abbreviated a-Si) and the like are formed on the gate insulating layer 140. Each linear semiconductor 151 extends mainly in the longitudinal direction, from which a plurality of protrusions 154 extend toward the gate electrode 124. The protrusion 154 extends to an upper portion of the gate line 121 and the storage electrode line 131.

A plurality of linear and island ohmic contacts 161 and 165 made of a material such as n + hydrogenated amorphous silicon doped with a high concentration of n-type impurities such as silicide or phosphorus on the semiconductor 151. Is formed. The linear contact member 161 has a plurality of protrusions 163, and the protrusions 163 and the island-like resistive contact members 165 are paired and disposed on the semiconductor 154, centered on the gate electrode 124. Face each other.

Side surfaces of the semiconductor 151 and the ohmic contacts 161 and 165 are also inclined with respect to the surface of the substrate 110, and the inclination angle is preferably 30 to 80 °.

A plurality of data lines 171 and a plurality of drain electrodes 175 separated therefrom are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140, respectively.

The data line 171 mainly extends in the vertical direction and crosses the gate line 121 and the storage electrode line 131 and transmits a data voltage. Each data line 171 has a wide end portion 179 for connection with another layer or an external device.

Each drain electrode 175 includes an extension and has a capacitive coupling electrode 176 extending to the center of the pixel. In this case, the capacitive coupling electrode 176 has a vertical portion connected to the data line 171 and a horizontal portion parallel to the gate line 121 to form a step shape.                     

Each of the data lines 171 includes a plurality of protrusions, which are bent to partially surround one end portion of the drain electrode 175 positioned on the semiconductor 154 to form the source electrode 173. One gate electrode 124, one source electrode 173, and one drain electrode 175 together with the protrusion 154 of the semiconductor form one thin film transistor (TFT), and a channel of the thin film transistor. A channel is formed in the protrusion 154 between the source electrode 173 and the drain electrode 175.

The data line 171 and the drain electrode 175 preferably include a refractory metal such as chromium or molybdenum-based metal, tantalum and titanium, and a lower layer (not shown) such as a refractory metal and a low resistance material disposed thereon. It may have a multilayer film structure consisting of an upper film of (not shown).

Similar to the gate line 121 and the storage electrode line 131, the data line 171 and the drain electrode 175 are inclined at an angle of about 30-80 °, respectively.

The ohmic contacts 161 and 165 exist only between the semiconductor 151 below and the data line 171 and the drain electrode 175 above and serve to lower the contact resistance. The linear semiconductor 151 has a portion exposed between the source electrode 173 and the drain electrode 175 and not covered by the data line 171 and the drain electrode 175.

A passivation layer 180 is formed on the data line 171 and the drain electrode 175 and the portion of the semiconductor 151 that is not covered by them. The passivation layer 180 is a-Si: C: O, a-Si: O: F, which is formed of an organic material having excellent planarization characteristics and photosensitivity, and plasma enhanced chemical vapor deposition (PECVD). The low dielectric constant insulating material of 4.0 or less, or an inorganic material, such as silicon nitride and silicon oxide, is preferable. The passivation layer 180 may include a lower insulating layer made of an inorganic material and an upper insulating layer made of an organic material.

The passivation layer 180 is formed with a plurality of contact holes 182 and 185 respectively exposing the extension portion of the drain electrode 175 and the end portion 179 of the data line 171, and the gate insulating layer 140. ) And a plurality of contact holes 181 exposing the end portion 129 of the gate line 121. The contact holes 181, 182, and 185 may be made in various shapes such as polygons or circles. The area of the contact holes 181 and 182 is preferably about 0.5 mm × 15 μm or more and about 2 mm × 60 μm or less. The side walls of the contact holes 181, 182, 185, 186 are inclined or stepped at an angle of 30 ° to 85 °.

A plurality of pairs of first / second pixel electrodes 190a and 190b and a plurality of contact assistants 81 and 82 made of ITO or IZO are formed on the passivation layer 180. Alternatively, the first and second pixel electrodes 190a and 190b may be made of a transparent conductive polymer, and in the case of a reflective liquid crystal display device, the first and second pixel electrodes 190a and 190b may be opaque reflective metals. It can also be made. In this case, the contact assistants 81 and 82 may be made of a material different from the first and second pixel electrodes 190a and 190b, for example, ITO or IZO.

The first and second pixel electrodes 190a and 190b are physically and electrically connected to the drain electrode 175 through the contact hole 185 to receive the data voltage from the drain electrode 175. In this case, the second pixel electrode 190b overlaps the capacitive coupling electrode 176 and is capacitively coupled to the first pixel electrode 190a.

The first and second pixel electrodes 190a and 190b to which the data voltage is applied rearrange the liquid crystal molecules 310 of the liquid crystal layer 3 by generating an electric field together with the common electrode 270.

The first and second pixel electrodes 190a and 190b and the common electrode 270 form a capacitor (hereinafter, referred to as a “liquid crystal capacitor”) to maintain an applied voltage even after the thin film transistor is turned off. In order to enhance the voltage holding capability, there is another capacitor connected in parallel with the liquid crystal capacitor, which is called a storage capacitor. The storage capacitor is formed by overlapping the first / second pixel electrodes 190a and 190b with the storage electrode line 131 and the like, and in order to increase the capacitance of the storage capacitor, that is, the storage capacitance, the storage electrode line 131 is formed in the first / second pixel electrode 190a and 190b. By extending and expanding the drain electrodes 175 connected to the second pixel electrodes 190a and 190b, the distance between the terminals can be shortened and the overlapping area can be increased.

The pair of first and second pixel electrodes 190a and 190b are engaged with each other with a gap therebetween, and an outer boundary thereof has a substantially rectangular shape with a chamfered left corner.

The pair of first / second pixel electrodes 190a and 190b has a center cutout 91, a lower cutout 92a, and an upper cutout 92b, and the first / second pixel electrodes 190a and 190b. Is divided into a plurality of areas by these cutouts 91, 92a, 92b. The cutouts 91, 92a, and 92b have almost inverted symmetry with respect to a horizontal centerline that bisects the pixel electrode in parallel with the gate line 121, and the upper and lower cutouts 92a and 92b are connected to each other to form a first cut. A gap is formed between the pixel electrode 190a and the second pixel electrode 190b.

The lower and upper cutouts 92a and 92b extend obliquely from the right side to the left side of the pixel electrode, and are positioned on the lower half and the upper half with respect to the horizontal center line of the pixel electrode. The lower and upper cutouts 92a and 92b extend perpendicular to each other at an angle of about 45 degrees with respect to the gate line 121.

The center cutout 91 is disposed at the center of the second pixel electrode 190b and has an inlet at the right side. The inlet of the central incision 91 has a pair of hypotenuses substantially parallel to the lower incision 92a and the upper incision 92b, respectively.

Accordingly, the lower half of the pixel electrode is divided into two regions by the lower cutout 92a, and the upper half is also divided into two regions by the upper cutout 92b. In this case, the number of regions or the number of cutouts may vary depending on the size of the pixel, the ratio of the length of the horizontal side and the vertical side of the pixel electrode, the type and characteristics of the liquid crystal layer 3, and the inclination direction may also vary.

The contact auxiliary members 81 and 82 are connected to the end portions 129 and 179 of the data line 171 and the gate line 121 through the contact holes 181 and 182, respectively. The contact auxiliary members 81 and 82 complement and protect the adhesion between the end portions 179 and 129 of the data line 171 and the gate line 121 and the external device.

Next, the common electrode display panel 200 will be described with reference to FIGS. 2 to 4.

The light blocking member 220 is formed on the insulating substrate 210 made of transparent glass or the like. The light blocking member 220 has a plurality of openings facing the pixel electrode 190 and having substantially the same shape as the pixel electrode 190, and corresponding to the gate line 121 and the data line 171 and the thin film transistor. It is preferable that it consists of the part corresponding to.

A plurality of color filters 230 are also formed on the substrate 210 and are mostly located in an area surrounded by the light blocking member 230. The color filter 230 may extend in the vertical direction along the pixel electrode 190. The color filter 230 may display one of primary colors such as red, green, and blue.

An overcoat 250 is formed on the color filter 230.

The common electrode 270 formed of a transparent conductor such as ITO or IZO is formed on the overcoat 250.

The common electrode 270 has a plurality of sets of cutouts 71, 72a, and 72b.

The pair of cutouts 71, 72a, and 72b face one of the first and second pixel electrodes 190a and 190b, and the center cutout 71, the lower cutout 72a, and the upper cutout 72b. It includes. Each of the cutouts 71, 72a and 72b is disposed between adjacent cutouts 91, 92a and 92b of the first and second pixel electrodes 190a and 190b or between the cutouts 92a and 92b and the first pixel electrode 190a. ) Is placed between the chamfered hypotenuses. In addition, each of the cutouts 71, 72a, and 72b includes at least one diagonal line extending in parallel with the lower cutout 92a or the upper cutout 92b of the pixel electrode.

Each of the lower and upper cutouts 72a and 2b extends from the left side of the pixel electrode toward the upper or lower side and overlaps the side along the side of the pixel electrode from each end of the diagonal line. It includes a horizontal portion and a vertical portion forming an obtuse angle.

The central cutout 71 is a central horizontal portion extending from the left side of the pixel electrode in the horizontal direction, a pair of diagonal portions extending toward the right side of the pixel electrode at an oblique angle with the central horizontal portion at the end of the central horizontal portion, and From each end of the oblique portion, it extends overlapping with the right side along the right side of the pixel electrode and includes a vertical longitudinal portion forming an obtuse angle with the oblique portion.

The number and direction of the cutouts 71, 72a, and 72b may also vary depending on the design element, and the light blocking member 220 overlaps the cutouts 71, 72a, and 72b and is located near the cutouts 71, 72a, and 72b. Can block light leaks.

Vertical alignment layers 11 and 21 are coated on the inner surfaces of the display panels 100 and 200, and polarizing plates 12 and 22 are provided on the outer surfaces thereof. The transmission axes ↔, 의 of the two polarizing plates 11 and 21 are orthogonal to each other, and one transmission axis is parallel to the gate line 121. In the case of a reflective liquid crystal display, one of the two polarizing plates 12 and 22 may be omitted.

A phase retardation film may be interposed between the display panels 100 and 200 and the polarizers 12 and 22 to compensate for the delay value of the liquid crystal layer 3, respectively. The phase retardation film has birefringence and serves to reversely compensate for the birefringence of the liquid crystal layer 3. As the retardation film, a uniaxial or biaxial optical film can be used, and in particular, a negative uniaxial optical film can be used.                     

The liquid crystal display may also include a polarizer 12 and 22, a phase retardation film, display panels 100 and 200, and a backlight unit for supplying light to the liquid crystal layer 3.

The liquid crystal layer 3 has negative dielectric anisotropy, and the liquid crystal molecules 310 of the liquid crystal layer 3 are aligned such that their major axes are perpendicular to the surfaces of the two display panels in the absence of an electric field. Therefore, incident light does not pass through the quadrature polarizers 12 and 22 and is blocked.

The alignment layers 11 and 21 may be horizontal alignment layers.

Meanwhile, when the inclination direction of the liquid crystal molecules 310 and the transmission axis of the polarizers 12 and 22 are 45 degrees, the highest luminance can be obtained. In the present embodiment, the inclination direction of the liquid crystal molecules 310 in all domains is the gate line. The gate line 121 is perpendicular or horizontal to the edges of the display panels 100 and 200 at an angle of 45 ° with the 121. Therefore, in the present exemplary embodiment, when the transmission axes of the polarizers 12 and 22 are attached to be perpendicular or parallel to the edges of the display panels 100 and 200, the highest luminance can be obtained and the polarizers 12 and 22 can be manufactured at low cost. Can be.

When a common voltage is applied to the common electrode 270 and a data voltage is applied to the first and second pixel electrodes 190a and 190b, a primary electric field substantially perpendicular to the surface of the display panel is generated. The liquid crystal molecules 310 try to change the direction of the long axis perpendicular to the direction of the electric field in response to the electric field. Meanwhile, the cutouts 71, 72a, 72b, 91, 92a, and 92b of the common electrode 270 and the first and second pixel electrodes 190a and 190b and the first and second pixel electrodes 190a parallel thereto. , 190b) produces a horizontal component that distorts the main electric field to determine the inclination direction of the liquid crystal molecules. The horizontal component of the main electric field is perpendicular to the sides of the cutouts 71, 72a, 72b, 91, 92a, 92b and the sides of the first / second pixel electrodes 190a, 190b. In addition, the horizontal components of the main electric field at two opposite sides of the cutouts 71, 72a, 72b, 91, 92a, and 92b are opposite to each other.

Through these electric fields, the cutouts 71, 72a, 72b, 91, 92a, and 92b control the direction in which the liquid crystal molecules of the liquid crystal layer 3 are inclined. The liquid crystal molecules in each domain defined by adjacent cutouts 71, 72a, 76b, 91, 92a, and 92b or defined by the left hypotenuse of the cutouts 72a and 72b and the first pixel electrode 190a The inclinations 71, 72a, 72b, 91, 92a, 92b are inclined in a direction perpendicular to the longitudinal direction. The two longest sides of each domain are substantially parallel to each other, and form approximately ± 45 degrees with the gate line 121, and most of the liquid crystal molecules in the domain are inclined in four directions.

The width of the cutouts 91, 92a, 92b, 71, 72a, 72b is preferably about 9 μm to about 12 μm.

At least one cutout 91, 92a, 92b, 71, 72a, 72b may be replaced with a protrusion (not shown) or a depression (not shown). The protrusions may be made of organic or inorganic materials and may be disposed above or below the field generating electrodes 190a, 190b, and 270, and the width thereof is preferably about 5 μm to about 10 μm.

The distance from the boundary of the cutouts 91, 92a and 92b of the first and second pixel electrodes 190a and 190b to the boundary of the cutouts 71, 72a and 72b of the common electrode 270 adjacent thereto and the boundary of the pixel electrode. In this case, the distance between the adjacent common electrode 270 cutouts 71, 72a, and 72b is preferably about 12 μm to about 20 μm, and more preferably about 17 μm to about 19 μm. When the interval was set in such a range, the aperture ratio was decreased, but the response speed of the liquid crystal was increased, so that the necessary transmittance was obtained.

The electric field is a horizontal component perpendicular to the sides of the cutout and the sides of the first and second pixel electrodes 190a and 190b due to the cutout of the electrode 270 and the sides of the first and second pixel electrodes 190a and 190b. Has Therefore, the tilt direction of the liquid crystal molecules 310 of each subregion is different from each other, and thus the viewing angle is extended.

The shape and arrangement of the incisions 91, 92a, 92b, 71, 72a, 72b can be modified.

In addition, in the liquid crystal display device as in the present exemplary embodiment, the liquid crystal molecules arranged adjacent to the coupling electrode 176 are distorted due to the step of the coupling electrode 176, so that no voltage is applied or two electrodes are applied. Even when there is almost no potential difference between the 190 and 270, they are not vertically arranged with respect to the surface of the substrate 100 and 200 and are inclined at an arbitrary angle. However, since the boundary constituting the capacitive coupling electrode 176 is parallel or perpendicular to the transmission axes ↔ and 편광 of the polarizing plates 11 and 21, the transmission axes ↔ and 의 of the polarizing plates 11 and 21 are parallel to each other. Tilt parallel or vertical. Therefore, even if the arrangement of the liquid crystal molecules is distorted due to the step by the coupling electrode 176, the light passing through the polarizing plates 11 and 21 in the portion adjacent to the coupling electrode 176 hardly generates a phase delay. Therefore, light leakage is hardly generated around the coupling electrode 176 when displaying a dark color, thereby preventing the contrast ratio from being lowered.

In addition, by arranging the coupling electrode 176 to overlap the cutout 71 of the common electrode 270, it is possible to prevent the aperture ratio from being lowered.                     

In this case, the number or cycles of bending of the capacitive coupling electrode 176 may be changed according to the size of the pixel and the resolution of the photolithography process during the manufacturing process.

The liquid crystal display shown in FIGS. 1 to 4 can be represented by the equivalent circuit shown in FIG. 5.

Referring to FIG. 5, the liquid crystal display includes a plurality of gate lines, a plurality of data lines, and a plurality of pixels, and each pixel includes a pair of first and second subpixels and a coupling capacitor Ccp. Each subpixel includes a first / second liquid crystal capacitor Clca / Clcb and a first / second storage capacitor Csta / Cstb. The first and second liquid crystal capacitors Clca / Clcb are disposed on the first and second pixel electrodes 190a and 190b, the common electrode 270, and the first and second pixel electrodes 190a and 190b. ) And the first / second storage capacitor Csta / Cstb includes the first / second pixel electrodes 190a and 190b, the storage electrode line 131, and the insulators 140 and 180 therebetween. The thin film transistor Q is connected to the gate line, the data line to which the data voltage is applied, and the capacitors Clca and Csta. The coupling capacitor Ccp includes a capacitive coupling electrode 176, a capacitive auxiliary electrode 136 connected to the second pixel electrode 190b, and a dielectric 140 therebetween, and is connected to an output terminal of the thin film transistor Q. It is connected.

The operation of the pixel will now be described in detail.

When a gate-on voltage is applied to the gate line connected to the thin film transistor Q, the thin film transistor Q is turned on to transfer the data voltage to the first pixel electrode 190b. Since the second pixel electrode 190b is isolated and capacitively coupled to the first pixel electrode 190a through the coupling capacitor Ccp, the voltage of the second pixel electrode 190b changes due to capacitive coupling. Due to the capacitive coupling, the voltage value of the second pixel electrode 190b is smaller than the voltage value of the first pixel electrode 190a. This will be described in detail.

If the voltage across the first liquid crystal capacitor Clca is Va and the voltage across the second liquid crystal capacitor Clcb is Vb, according to the voltage division law,

Vb = Va × [Ccp / (Ccp + Clcb + Cstb)]

Since Ccp / (Ccp + Clcb + Cstb) cannot always be greater than 1, Vb is always smaller than Va. At this time, the voltage of the common electrode 270 for Clca and Clcb and the voltage of the sustain electrode line 131 for Csta and Cstb may be different. In this case, since the voltage of the common electrode 270 applied to Clca and Clcb is the same, The absolute value of the image signal voltage Va applied is always larger than the absolute value of the image signal voltage Vb applied to Clcb.

By adjusting the coupling capacitance Ccp, the ratio of the voltages Va and Vb can be effectively controlled. The coupling capacitor Ccp may be adjusted by changing the overlapping area or distance between the capacitive coupling electrode 176 and the second pixel electrode 190b. For example, the overlap area can be changed by changing the width of the coupling electrode 176 and the distance can be changed by placing the coupling electrode 176 on the same layer as the gate line 121.

When a non-zero voltage is applied to the liquid crystal capacitors Clca and Clcb, an electric field approximately perpendicular to the surfaces of the display panels 100 and 200 is generated, and the liquid crystal molecules 310 respond to the electric field so that their major axis is perpendicular to the electric field direction. I want to change that direction. Since the strengths of the electric fields in the first liquid crystal capacitor Clca and the second liquid crystal capacitor Clcb are different, the liquid crystal molecules 310 in the first and second liquid crystal capacitors Clca and Clcb may receive different forces. According to different tilt angles. Therefore, side visibility is improved.

The area ratio of the second pixel electrode 190b through which the high or low pixel voltage is transmitted with respect to the first pixel electrode 190a through which the image signal is directly transmitted is in a range of 1: 0.85-1: 1.15, and the first pixel Two or more second pixel electrodes 190b may be disposed to be capacitively coupled to the electrodes 190a.

The area of the first pixel electrode 190a is preferably larger than the area of the second pixel electrode 190b, but preferably not more than about six times the area of the second pixel electrode 190b.

Meanwhile, in another embodiment, a voltage whose absolute value is always higher than the voltage of the first pixel electrode 190a may be applied to the second pixel electrode 190b, which may be applied to the second pixel electrode 190b such as a common voltage. This is achieved by capacitively coupling the first pixel electrode 190a while an arbitrary voltage is applied.

The shape and position of the coupling electrode 176 may also be changed.

6 is a layout view illustrating a structure of a liquid crystal display according to another exemplary embodiment. FIG. 7 is a cross-sectional view of the liquid crystal display of FIG. 6 taken along the line VII-VII ′.

6 and 7, the liquid crystal display according to the present exemplary embodiment also includes a thin film transistor array panel 100, a common electrode display panel 200, and a liquid crystal layer interposed between the two display panels 100 and 200. 3) and a pair of polarizers 12 and 22 attached to the outer surfaces of the two display panels 100 and 200.

The layered structures of the display panels 100 and 200 according to the present exemplary embodiment are substantially the same as those of FIGS. 1 to 4.

Referring to the thin film transistor array panel 100, a plurality of gate lines 121 including the gate electrode 124 and a plurality of storage electrode lines including the first to fourth storage electrodes 133a, 133b, 133c, and 133d are described. A plurality of linear ohmic contacts 131 are formed on the substrate 110 and include a gate insulating layer 140, a plurality of linear semiconductors 151 including protrusions 154, and a plurality of linear resistive contact members including protrusions 163. 161 and the plurality of island resistive contact members 165 are sequentially formed. A plurality of data lines 171 including the source electrode 173 and a plurality of drain electrodes 175 having the coupling electrode 176 are formed on the ohmic contacts 161 and 165, and the passivation layer 180 is formed thereon. A plurality of contact holes 181, 182, and 185 are formed in the passivation layer 180 and the gate insulating layer 140. A plurality of first / second pixel electrodes 190a and 190b and a plurality of contact auxiliary members 81 and 82 are formed on the passivation layer 180, and an alignment layer 11 is coated thereon.

Referring to the common electrode display panel 200, the light blocking member 220, the plurality of color filters 230, the overcoat 250, the common electrode 270, and the alignment layer 21 are formed on the insulating substrate 210. have.

Unlike the liquid crystal display of FIGS. 1 to 4, the linear semiconductor 151 has a shape substantially the same as that of the data line 171, the drain electrode 171, and the ohmic contacts 161 and 165 thereunder. However, the protrusion 154 has a portion not covered by the data line 171 and the drain electrode 175, such as a portion between the source electrode 173 and the drain electrode 175.

In addition, unlike the previous embodiment, the coupling electrode 176 has a bent portion of four caps, through which the coupling electrode 176 may overlap the cutout 71 of the common electrode 270 more widely.

In the method of manufacturing the thin film transistor array panel according to the exemplary embodiment of the present invention, the data line 171, the drain electrode 175, the semiconductor 151, and the ohmic contacts 161 and 165 are formed in one photo process. .

The photoresist pattern used in the photolithography process has a different thickness depending on the position, and there may be various methods of varying the thickness of the photoresist pattern depending on the position, for example, a transparent area and a light shielding area in the photomask. In addition to the light blocking area, there is a method of providing a translucent area. The translucent region is provided with a slit pattern, a lattice pattern, or a thin film having a medium transmittance or a medium thickness. When using the slit pattern, it is preferable that the width of the slits and the interval between the slits are smaller than the resolution of the exposure machine used for the photographic process. Another example is to use a photoresist film that can be reflowed. That is, a thin portion is formed by forming a reflowable photoresist pattern with a normal exposure mask having only a transparent region and a light shielding region and then reflowing to allow the photoresist film to flow down into a region where no residue is left. In this way, a one-time photographic process can be reduced, thereby simplifying the manufacturing method.

Many of the above-described features of the liquid crystal display of FIGS. 1 to 4 may be applied to such an embodiment.

8 is a layout view illustrating a structure of a liquid crystal display according to another exemplary embodiment. FIG. 9 is a cross-sectional view of the liquid crystal display of FIG. 8 taken along the line IX-IX ′.

8 and 9, the liquid crystal display according to the present exemplary embodiment also includes a thin film transistor array panel 100, a common electrode display panel 200, and a liquid crystal layer 3 inserted between the two display panels 100 and 200. And a pair of polarizers 12 and 22 attached to outer surfaces of the two display panels 100 and 200.

The layered structure of the display panels 100 and 200 according to the present exemplary embodiment is substantially the same as the layered structure of the display panels 100 and 200 illustrated in FIGS. 1 to 4.

Referring to the thin film transistor array panel 100, a plurality of gate lines 121 and a plurality of storage electrode lines 131 including the gate electrode 124 are formed on the substrate 110, and the gate insulating layer 140 is disposed thereon. ), A plurality of linear semiconductors 151 and a plurality of ohmic contacts 161 and 165 are formed in this order. A plurality of data lines 171 and a plurality of drain electrodes 175 including the source electrode 173 are formed on the ohmic contacts 161 and 165 and the gate insulating layer 140, and the passivation layer 180 is disposed thereon. A plurality of contact holes 181, 182, and 185 are formed in the passivation layer 180 and the gate insulating layer 140. A plurality of first and second pixel electrodes 190a and 190b and a plurality of contact auxiliary members 81 and 82 are formed on the passivation layer 180, and an alignment layer 11 is formed thereon.

Referring to the common electrode display panel 200, the light blocking member 220, the overcoat 250, the common electrode 270, and the alignment layer 21 are formed on the insulating substrate 210.

Unlike FIGS. 1 to 4, the color filters 230 are disposed on the thin film transistor array panel 100 and are disposed under the passivation layer 180. Each color filter 230 preferably has an opening that exposes the drain electrode 175.

As described above, the pixel electrodes are divided and applied to each other, thereby improving side visibility of the liquid crystal display and thereby expanding the viewing angle.

In addition, since the coupling electrode forming the coupling capacitance has a step shape, even if a step caused by the coupling electrode occurs, light leakage occurring in the vicinity of the coupling electrode may be minimized, thereby preventing the contrast ratio from being reduced.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights. In particular, the arrangement of the cutouts formed in the pixel electrode and the common electrode may be variously modified.

Claims (9)

Gate Line, A data line insulated from and intersecting the gate line; A thin film transistor connected to the source electrode of each of the gate line and the data line and having a drain electrode and a semiconductor, A capacitive coupling electrode connected to the drain electrode and including at least one bent portion to form a step shape; A passivation layer covering the gate line, the data line, and the thin film transistor; A pixel including a first pixel electrode directly connected to the drain electrode and a second pixel electrode separated from the first pixel electrode and overlapping the capacitive coupling electrode and capacitively connected to the first pixel electrode electrode Thin film transistor array panel comprising a. In claim 1, The coupling electrode is a thin film transistor array panel formed by alternately connecting a first portion parallel to the gate line and a second portion parallel to the data line. In claim 1, And a storage electrode line having a storage electrode overlapping at least one of the pixel electrode, the coupling electrode, and the drain electrode to form a storage capacitor. In claim 1, And the semiconductor is linear along the data line. In claim 4, The semiconductor, except between the source electrode and the drain electrode, has the same planar shape as the data line and the drain electrode. A gate line, a data line insulated from and intersecting the gate line, a thin film transistor having a drain electrode and a semiconductor, connected to a source electrode of each of the gate line and the data line, and connected to the drain electrode, and at least one or more A capacitive coupling electrode having a bent portion, a protective layer covering the gate line, the data line and the thin film transistor, and a first pixel electrode directly connected to the drain electrode and the first pixel electrode. A thin film transistor array panel including a pixel electrode overlapping the capacitive coupling electrode and including a second pixel electrode connected to the first pixel electrode in a capacitive manner; A common electrode panel facing the thin film transistor array panel and having a common electrode formed thereon; Liquid crystal display comprising a. In claim 6, The coupling electrode is a thin film transistor array panel formed by alternately connecting a first portion parallel to the gate line and a second portion parallel to the data line. In claim 7, And a polarizing plate attached to an outer surface of the thin film transistor array panel and the common electrode display panel. In claim 8, The transmission axis of the polarizer is parallel to or perpendicular to the first and second portions.

Images