KR20060043534A - 트렌치 내에 독립적인 제어 가능한 제어 게이트를 갖는 매립형 비트 라인 불휘발성 부동 게이트 메모리 셀, 및 그 어레이, 및 형성 방법 - Google Patents

트렌치 내에 독립적인 제어 가능한 제어 게이트를 갖는 매립형 비트 라인 불휘발성 부동 게이트 메모리 셀, 및 그 어레이, 및 형성 방법 Download PDF

Info

Publication number
KR20060043534A
KR20060043534A KR1020050019259A KR20050019259A KR20060043534A KR 20060043534 A KR20060043534 A KR 20060043534A KR 1020050019259 A KR1020050019259 A KR 1020050019259A KR 20050019259 A KR20050019259 A KR 20050019259A KR 20060043534 A KR20060043534 A KR 20060043534A
Authority
KR
South Korea
Prior art keywords
region
trench
floating gate
gate electrode
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1020050019259A
Other languages
English (en)
Korean (ko)
Inventor
다나 리
보미 첸
소랩 키아니안
Original Assignee
실리콘 스토리지 테크놀로지 인크
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/797,296 external-priority patent/US7307308B2/en
Application filed by 실리콘 스토리지 테크놀로지 인크 filed Critical 실리콘 스토리지 테크놀로지 인크
Publication of KR20060043534A publication Critical patent/KR20060043534A/ko
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6733—Multi-gate TFTs

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)
KR1020050019259A 2004-03-09 2005-03-08 트렌치 내에 독립적인 제어 가능한 제어 게이트를 갖는 매립형 비트 라인 불휘발성 부동 게이트 메모리 셀, 및 그 어레이, 및 형성 방법 Withdrawn KR20060043534A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/797,296 2004-03-09
US10/797,296 US7307308B2 (en) 2003-04-07 2004-03-09 Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation

Publications (1)

Publication Number Publication Date
KR20060043534A true KR20060043534A (ko) 2006-05-15

Family

ID=35085603

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020050019259A Withdrawn KR20060043534A (ko) 2004-03-09 2005-03-08 트렌치 내에 독립적인 제어 가능한 제어 게이트를 갖는 매립형 비트 라인 불휘발성 부동 게이트 메모리 셀, 및 그 어레이, 및 형성 방법

Country Status (4)

Country Link
JP (1) JP2005260235A (https=)
KR (1) KR20060043534A (https=)
CN (1) CN1691336A (https=)
TW (1) TW200601461A (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9293204B2 (en) * 2013-04-16 2016-03-22 Silicon Storage Technology, Inc. Non-volatile memory cell with self aligned floating and erase gates, and method of making same
CN110010606B (zh) * 2018-01-05 2023-04-07 硅存储技术公司 衬底沟槽中具有浮栅的双位非易失性存储器单元
CN121925959A (zh) * 2023-10-04 2026-04-24 株式会社半导体能源研究所 半导体装置

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4868629A (en) * 1984-05-15 1989-09-19 Waferscale Integration, Inc. Self-aligned split gate EPROM
IT1227989B (it) * 1988-12-05 1991-05-20 Sgs Thomson Microelectronics Matrice di celle di memoria eprom con struttura a tovaglia con migliorato rapporto capacitivo e processo per la sua fabbricazione
DE69432568T2 (de) * 1991-08-29 2004-02-26 Hyundai Electronics Industries Co., Ltd. Selbstjustierende flash-eeprom-zelle mit doppelbit-geteiltem gat
US5278439A (en) * 1991-08-29 1994-01-11 Ma Yueh Y Self-aligned dual-bit split gate (DSG) flash EEPROM cell
JPH05211338A (ja) * 1991-10-09 1993-08-20 Mitsubishi Electric Corp 不揮発性半導体装置
JP3403877B2 (ja) * 1995-10-25 2003-05-06 三菱電機株式会社 半導体記憶装置とその製造方法
US5963806A (en) * 1996-12-09 1999-10-05 Mosel Vitelic, Inc. Method of forming memory cell with built-in erasure feature
US6952034B2 (en) * 2002-04-05 2005-10-04 Silicon Storage Technology, Inc. Semiconductor memory array of floating gate memory cells with buried source line and floating gate

Also Published As

Publication number Publication date
JP2005260235A (ja) 2005-09-22
CN1691336A (zh) 2005-11-02
TW200601461A (en) 2006-01-01

Similar Documents

Publication Publication Date Title
US7307308B2 (en) Buried bit line non-volatile floating gate memory cell with independent controllable control gate in a trench, and array thereof, and method of formation
US6952034B2 (en) Semiconductor memory array of floating gate memory cells with buried source line and floating gate
US6756633B2 (en) Semiconductor memory array of floating gate memory cells with horizontally oriented floating gate edges
US7315056B2 (en) Semiconductor memory array of floating gate memory cells with program/erase and select gates
US6906379B2 (en) Semiconductor memory array of floating gate memory cells with buried floating gate
JP3615765B2 (ja) リードオンリメモリセル装置の製造方法
US9892790B2 (en) Method of programming a continuous-channel flash memory device
CN100440514C (zh) 非易失浮栅存储单元及其阵列以及其形成方法
US6873006B2 (en) Semiconductor memory array of floating gate memory cells with burried floating gate and pointed channel region
CN101174652B (zh) 自对准方法及用该方法制造的存储器阵列
US20100133602A1 (en) Non-volatile memory cell with buried select gate, and method of making same
US7190018B2 (en) Bi-directional read/program non-volatile floating gate memory cell with independent controllable control gates, and array thereof, and method of formation
US6822287B1 (en) Array of integrated circuit units with strapping lines to prevent punch through
US7151021B2 (en) Bi-directional read/program non-volatile floating gate memory cell and array thereof, and method of formation
KR20000076852A (ko) 반도체 기억장치 및 그 제조방법
KR20060043534A (ko) 트렌치 내에 독립적인 제어 가능한 제어 게이트를 갖는 매립형 비트 라인 불휘발성 부동 게이트 메모리 셀, 및 그 어레이, 및 형성 방법
US20070096222A1 (en) Low voltage nanovolatile memory cell with electrically transparent control gate

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20050308

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid