KR20060040156A - Data processing apparatus for accessing bulk direct memory to dmacontroller connecting multiplex channel and bulk direct memory access method thereof - Google Patents

Abstract

Disclosed are an information processing apparatus capable of a bulk DMA operation in a DMA controller having a plurality of channels and a method of operating the bulk DMA. The information processing apparatus counts the memory in which the print target data is stored, the number of times of access of the memory, and equals a preset number of accesses, and generates a timer tick, and accesses the memory, and sets a predetermined priority among the plurality of connected channels. And a DMA controller for controlling the memory to input and output data to be output to the priority channel, and controlling the memory to input and output data to be printed by changing to a next priority channel among a plurality of connected channels when a timer tick is generated in the timer. . As a result, since only a time for reading the DCB list stored in the memory or the SFR at a time is taken, not only the DMA operation processing time is reduced, but also the overall performance is improved.

DMA, Multichannel, Bulk

Description

Data processing apparatus for accessing bulk direct memory to DMAController connecting multiplex channel and bulk direct memory access method according to DMA controller with multiple channels.

1 is a block diagram of an information processing apparatus according to an embodiment of the present invention;

2 is a specific block diagram of a DMA controller provided in the information processing apparatus;

3 is a schematic diagram showing the structure of a memory map included in an information processing apparatus;

4 is a flowchart provided to explain a method of operating a Bulk DMA in an information processing apparatus according to an embodiment of the present invention; and

5 is a diagram illustrating an example of a bulk DMA process according to a bulk DMA operation method.

Explanation of symbols on the main parts of the drawings

10 bus 20 central processing unit

30: DMA controller 32: channel controller

34: DMA control register 40: I / O part

50: Bus Arbiter 60: Memory

70: timer

The present invention relates to a method of operating a bulk DMA (Direct Memory Access) of an information processing apparatus, and more particularly, to a method of operating a bulk DMA of an information processing apparatus capable of storing and reading data by direct memory access. .

Direct Memory Access (hereinafter, referred to as 'DMA') operation is an operation in which direct data transfer is performed between a memory connected to a bus and an input / output device without being controlled by the CPU through a central processing unit (CPU). The I / O device is connected to the information processing device to form each channel and requests data stored in the memory or provides data to be stored in the memory. The information provider (IP), universal serial bus (USB), HDD ( Hard Disk Drive).

The information processing apparatus can store the data input from the channel as a bitmap in the memory through one DMA operation. Alternatively, the information processing apparatus can read out data stored as a bitmap in the memory through one DMA operation at the request of a channel.

The information processing apparatus performs a DMA operation according to the set DMA control block (hereinafter referred to as 'DCB'). The DCB consists of a DMA count register, a register for storing the start address of the DMA, a register for storing the end address of the DMA, and a register for storing the address of the instruction to be executed in the next step.

The information processing apparatus performs the DMA operation according to the set DCB, and stores the data received from the channel from the position of the start address to the end address of the memory. Alternatively, the information processing apparatus performs a DMA operation in accordance with the DCB set by the request of the channel, and reads out the data stored from the start address to the end address of the memory.

However, in the conventional information processing apparatus in which a plurality of input / output devices are connected to perform a DMA operation through a plurality of channels, when a plurality of channels require a large amount of DMA operation, one DMA operation is performed after one DCB setup. Was performed. In order to perform the next DMA operation, the information processing apparatus could perform the DMA operation after the DCB setup again after an interrupt indicating that the ongoing DMA operation is completed.

Therefore, every DCB must include a register that controls the interrupt. In addition, when a large amount of DMA operations is required, the information processing apparatus had to perform as many interrupt service routines as the required number of DMA operations.

Therefore, all DCBs must contain a register to control interrupts, which not only wastes storage space but also requires a DCB setup and interrupt service routine processing for a large number of required DMA operations, thereby increasing processing time of DMA operations. This can happen.

Accordingly, an object of the present invention is to provide an information processing apparatus capable of performing bulk DMA operation in a DMA controller having a plurality of channels that enables subsequent generation of DCB setting and DMA operation to be processed next without interrupt service routine processing, and the bulk DMA operation thereof. In providing a method.

An information processing apparatus according to the present invention for achieving the above object includes a memory for storing data to be printed, a timer for counting the number of times of access of the memory, and generating a timer tick when the number of times of access is equal to a preset number of times, and the memory. Accessing the controller to control the memory to input and output the print target data to a predetermined priority channel among a plurality of connected channels, and when the timer tick occurs in the timer, to the next preset priority channel among the plurality of connected channels. And a DMA controller for controlling the memory to input and output the data to be printed.

The DMA controller may further include a channel controller configured to control the plurality of connected channels such that the preset priority channel is changed to the preset next priority channel when the timer tick is generated in the timer, and the print target data is stored in the DMA controller. Preferably, the memory device includes a DMA control register in which a start address, an end address, a count value, and a control signal of the memory to be input / output are stored.

The memory may be at least one of an SFR, an SRAM, and an SDRAM, and a timer table in which the predetermined number of accesses is recorded, and a priority table in which the priority is recorded, are stored in the SFR.

On the other hand, the Bulk DMA operation of the information processing apparatus including a memory in which the print target data of the present invention is stored, accessing the memory, inputting and outputting the print target data through a predetermined priority channel among a plurality of connected channels; And when a predetermined timer tick occurs, changing the predetermined priority channel among the plurality of connected channels to a preset next priority channel to access the memory to input and output the data to be printed.

Preferably, the predetermined timer tick is generated when the number of times of access of the memory is counted and equal to a predetermined number of times of access.

Hereinafter, with reference to the drawings will be described in detail the present invention.

1 is a block diagram of an information processing apparatus according to an embodiment of the present invention.

Referring to FIG. 1, the information processing apparatus includes a bus 10, a central processing unit 20, a DMA control unit 30, an input / output unit 40, a bus intermediator 50, a memory 60, and a timer 70. ).

The bus 10 includes a central processing unit 20, a DMA control unit 30, an input / output unit 40, a bus intermediator 50, a memory 60, a timer 70, and an input / output unit constituting an information processing device. It is a path or transmission path of information that connects the devices and transmits control signals, data to be printed, and information between the above devices and the input / output devices.

The central processing unit (CPU) 20 controls the connection and disconnection with the bus 10, and is a master having a bus access right, and controls the bus usage of other devices.

The DMA controller 30, like the central processing unit 20, is a master having a bus access right, and transmits data to be printed by performing a DMA operation without the control of the central processing unit 20. FIG.

In the single mode, the DMA controller 30 performs one DMA operation and transmits the print target data after one DCB setup. In the bulk mode, the DMA controller 30 sets up all the DCBs at once to perform all the DMA operations required by a plurality of channels, and then transmits the print target data by performing all one DMA operations.

A plurality of connection devices are connected to the input / output unit (I / O) 40 to form a channel for each connection device. The input / output unit 40 inputs and outputs data to be printed on a channel formed by the DMA operation of the DMA controller 30.

The bus arbiter 50 sends a signal requesting the use of the bus by the central processing unit 20 and the DMA controller 30 to allocate the use of the bus to receive the signal.

The memory 60 stores data to be printed, a DCB list, a timer table for controlling the number of DMA operations in one channel being performed, and a priority table for controlling priorities of a plurality of channels.

The memory 60 includes a Special Function Regiser (SFR), a Read Only Memory (ROM), a Static Random Access Memory (SRAM), and a Synchronous Dynamic Random Access Memory (SDRAM). The SFR stores a timer table and a priority table.

The timer 70 counts the number of DMA operations in one channel being performed in the bulk mode, and generates a timer tick when the timer 70 is equal to the number of DMA operations set in the timer table stored in the SFR.

2 is a specific block diagram of a DMA controller provided in the information processing apparatus.

Referring to FIG. 2, the DMA controller 30 includes a channel controller 32, a DMA control register 34, a data controller 36, and an address controller 38.

The channel controller 32 controls the channel of the connected devices connected to the input / output unit 40 to perform a large amount of DMA operation according to the priority table stored in the SFR. When the timer tick is generated by the timer 70, the channel controller 32 changes the channel on which the DMA operation is currently performed to the next channel according to the priority table.

In addition, if the priority table is not set, the channel controller 32 sequentially controls the channels. If the timer tick is not set, the channel controller 32 completes the DMA operation of the current channel and sequentially changes the current channel to the next channel.

The DMA control register 34 stores a DCB list read from the memory 60. The DMA control register 34 also stores the generated global control block (GCB) based on the DCB list read to perform a large amount of DMA operations required by a plurality of channels.

The GCB is a register that controls the entire DMA operation, a register that stores the start address of the first DCB, a register that stores the current DMA start address, a register that stores the current DMA end address, a current DMA count register, and a register that controls the current DMA operation. , And a register for requesting an interrupt.

The data control unit 36 transmits a control signal for instructing the input / output of the print target data to the bus 10 to the memory 60. The address controller 38 transmits a control signal for commanding the address output to the bus 10.

3 is a schematic diagram showing the structure of a memory map included in the information processing apparatus.

Referring to FIG. 3, the memory 60 is allocated ROMs from addresses P to Q, SFRs are allocated to R to S, SRAMs are allocated to S to T, and SDRAMs are allocated to U to FFFFFF.                     

The DCB list may be allocated to any area of the memory 60 and may be stored in the form of an annular linked list. The timer table stored in the SFR exists by the maximum number of DCBs, and the priority table exists by the number of channels connected to the input / output unit 40.

4 is a flowchart provided to explain a method for operating a Bulk DMA in an information processing apparatus according to an embodiment of the present invention.

Referring to FIG. 4, the DMA controller 30 initializes a previous DMA operation to perform a new DMA operation (S100). The DMA controller 30 initializes the DMA control register 34 to remove the stored DCB.

The DMA controller 30 determines whether a bulk mode capable of performing a large amount of DMA operations is selected (S110). The bulk mode is a mode in which all DMA operations required by a plurality of channels connected to the input / output unit 40 are performed at a time.

If the bulk mode is not selected, the DMA controller 30 performs one DMA operation after one DCB setup in a single mode (S115).

When the bulk mode is selected, the DMA controller 30 reads all the DCB lists stored in the memory 60 (S120). The DMA controller 30 requests the bus intermediator 50 to use the bus 10, and when the use of the bus 10 is permitted, the DMA controller 30 controls the bus 10 to store all of the memories stored in the memory 60. Read the list of DCBs.

The DMA controller 30 updates all the read DCB lists to the DMA control register 34 (S130).                     

The channel controller 32 of the DMA controller 30 determines whether priority is set to the channel connected to the input / output unit 40 (S140). The channel controller 32 may know the priority by looking at the priority table stored in the SFR.

If the priority is set, the DMA controller 30 moves to the DCB of the channel set to the highest priority according to the priority table (S150). The DMA controller 30 moves to the first DCB of the stored start address according to a register which stores the start address of the first DCB of the GCB stored in the DMA control register 34.

If the priority is not set, the DMA controller 30 moves to the DCB of the first channel (S155). The DMA controller 30 moves to the first DCB of the stored start address according to a register which stores the start address of the first DCB of the GCB stored in the DMA control register 34.

The DMA controller 30 performs a DMA operation according to the first DCB moved (S160). The DMA controller 30 registers the entire DMA operation of the GCB stored in the DMA control register 34, a register which stores the current DMA start address, a register which stores the current DMA end address, a current DMA count register, and the present. Data is transferred directly between the memory 60 and the channel in accordance with a register controlling the DMA operation.

The DMA controller 30 determines whether the DMA operation of the current channel is completed (S170). There are various ways in which the DMA controller 30 determines whether the DMA operation of the current channel is completed.

One of them is that when the timer 70 is activated and the timer tick is generated by the timer 70, the DMA controller 30 determines that the DMA operation of the current channel is completed.

The timer 70 counts the number of DMA operations in the current channel where the DMA operation is being performed, and compares the counted DMA operations with the number of DMA operations set in the timer table stored in the SFR. As a result of the comparison, the timer 70 generates a timer tick when the counted number of DMA operations equals the set number of DMA operations. After the timer tick is generated, the timer 70 initializes and counts the number of DMA operations of the next channel where the DMA operation is performed again.

On the other hand, if the timer 70 is deactivated, the DMA controller 30 performs up to the DMA operation of the last DCB of the current channel, and determines that the DMA operation of the current channel is completed.

If it is determined that the DMA operation of the current channel is completed, the DMA controller 30 determines whether the bulk mode is terminated (S180). The DMA controller 30 ends the bulk mode when a register for requesting an interrupt is included in the GCB stored in the DMA control register 34.

If the GCB does not include a register for requesting an interrupt, the channel controller 32 changes the channel on which the DMA operation is completed to the next channel and moves to the DCB of the next channel (S190). In step S140, if the priority is set, the channel controller 32 changes the channel having completed the DMA operation to the next priority channel according to the priority table stored in the SFR. In step S140, if the priority is not set, the channel controller 32 sequentially changes the channel on which the DMA operation is completed to the second channel.                     

5 is a diagram illustrating an example of a bulk DMA process according to a bulk DMA operation method.

Referring to FIG. 5, in FIG. 5A, the priority is set in order of channel 0, channel 1, channel 2, and channel 3 according to the priority table, and the bulk DMA processing without the timer table is set. Is one example.

Since the timer table is not set, the DMA controller 30 performs the DMA operation of the last DCB of channel 0 according to the priority table. Next, the DMA controller 30 performs the DMA operation of the last DCB of the channel 1 of the next priority according to the priority table, and performs the DMA operation in the order of channel 2 and channel 3 according to the priority.

FIG. 5B is an example of Bulk DMA processing in which priority is set in order of channel 0, channel 1, channel 2, and channel 3 according to the priority table, and the timer table is set to 2 ticks. .

The DMA controller 30 performs a DMA operation on channel 0 according to the priority table. At this time, the timer 70 counts the number of DMA operations performed, and generates a timer tick when the counted number of DMA operations is equal to 2 ticks set in the timer table. When the timer tick is generated, the channel controller 32 of the DMA controller 30 changes channel 0 to channel 1 of the next priority. The DMA controller 30 changes the channel according to the priority every two ticks, and performs the DMA operation of the DCB of the channel 3. After that, returning to channel 0 again, the DMA controller 30 repeats the above operation, and performs the DMA operation of the last DCB of all channels.

As described above, according to the present invention, since only a time for reading the DCB list stored in the memory or the SFR at a time is required, the DMA operation processing time is reduced, and the overall performance is improved.

In addition, although the preferred embodiment of the present invention has been shown and described above, the present invention is not limited to the specific embodiments described above, but the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be understood from the technical spirit or the prospect of the present invention.

Claims (5)

A memory in which print target data is stored; A timer that counts the number of accesses of the memory and generates a timer tick when the number of accesses of the memory is equal to a preset number of accesses; and Accessing the memory and controlling the memory to input and output the print target data to a predetermined priority channel among a plurality of connected channels, and when the timer tick is generated in the timer, set a next priority among the plurality of connected channels. And a DMA controller for changing the channel to control the memory to input and output the data to be printed. The method of claim 1, The DMA control unit, A channel controller configured to control the plurality of connected channels such that the preset priority channel is changed to the preset next priority channel when the timer tick is generated in the timer; and And a DMA control register in which a start address, an end address, a count value, and a control signal of the memory to which the print target data is to be input / output are stored. The method of claim 1, The memory, At least one of SFR, SRAM, and SDRAM, And a timer table in which the predetermined number of times of access is recorded, and a priority table in which the priority is recorded, in the SFR. An information processing apparatus including a memory in which print target data is stored, Accessing the memory and inputting / outputting the print target data through a predetermined priority channel among a plurality of connected channels; and And when the predetermined timer tick occurs, changing the predetermined priority channel among the plurality of connected channels to a preset next priority channel to access the memory to input and output the data to be printed. Bulk DMA operation method of an information processing device. The method of claim 4, wherein The predetermined timer tick is, And counting the number of times of access of the memory and generating the same number of times of access.

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