KR20060039961A - Method and apparatus for enhancing reception performance of satellite broadcasting using chip equalization algorithm - Google Patents

Abstract

According to the present invention, a first bit signal is calculated using first region pilot data included in a satellite broadcast signal received through a tuner, and a first corresponding to the difference of a reference pilot signal calculated using previously recognized pilot data. A first equalizer updating the default tap coefficient to the first tap coefficient by using an error value; A second error value corresponding to a difference between the reference pilot signal calculated using the previously recognized pilot data after generating a reconstructed pilot signal by using the satellite broadcast signal received after a first tap coefficient and a preset delay time; A second equalizer which updates the first tap coefficients with a second tap coefficients by using; Satellite broadcasting using a chip equalization technique comprising a detector for restoring broadcast data using the satellite broadcast signal received after a second tap coefficient and a predetermined double delay time, and delivering the recovered broadcast data to a broadcast channel decoder. The present invention relates to a method and a device for improving reception performance. The BER performance is excellent, and more broadcast channels can be secured in the same communication environment.

Equalizer, Digital Broadcast, Satellite, Receiver

Description

Method and apparatus for improving reception performance of satellite broadcasting using chip equalization technique             

1 is a diagram illustrating a general satellite broadcasting system.

2 is a diagram illustrating a configuration of a general satellite broadcast transmission system.

3 is a diagram illustrating a configuration of a general satellite broadcast receiving system.

4 is a diagram illustrating a satellite broadcast receiving system according to an embodiment of the present invention.

5 illustrates a frame structure of a general baseband transmission signal.

6 is a view showing the configuration of a first equalizing unit according to an embodiment of the present invention.

7 is a view showing the configuration of a second equalizing unit according to an embodiment of the present invention.

8 is a diagram illustrating a configuration of an equalizer for performing a tap update using a control data section according to an embodiment of the present invention.

9 is a view showing the configuration of a detection unit according to an embodiment of the present invention.

10 illustrates a transform step size LMS algorithm using a moving average for tap coefficient updating according to an embodiment of the present invention.

11 is a graph comparing Uncoded BER performance of a conventional rake receiver and a conventional chip equalizer.

12 is a graph comparing Uncoded BER performance of the present invention and a conventional chip equalizer.

The present invention relates to a method and apparatus for improving satellite broadcast reception performance using a chip equalization technique. In particular, the present invention has better bit error rate (BER) performance and secures a larger number of broadcast channels than a conventional rake receiver. In addition, the present invention relates to a method and apparatus for improving satellite broadcast reception performance using a chip equalization technique having better channel tracking performance than a conventional chip equalization technique in mobile reception.

Recently, user demand for digital broadcasting that provides high quality audio and video services is increasing. Accordingly, digital audio broadcasting (DAB) services are being implemented in Europe and the United States, and research and development for the implementation of terrestrial and satellite digital multimedia broadcasting (DMB) services are also underway in Korea. .

1 is a diagram illustrating a general satellite broadcasting system.

Referring to FIG. 1, a satellite broadcasting system includes a broadcasting station 100, a satellite base station 110, a satellite 120, a satellite control station 130, a broadcast receiving terminal 140 (hereinafter referred to as a receiver), a gap filler, 150).

The satellite base station 110 receives broadcast data provided from each broadcasting station 100 and transmits the broadcast data to the satellite 120 through the uplink transmission path of the Ku band (12.5 to 18 GHz). There may be a plurality of broadcasting stations 100 transmitting broadcast data to the satellite 120 through one or more satellite base stations 110.

The satellite 120 amplifies a broadcast signal of the Ku band received from the satellite base station 110 and converts the signal into a signal of the S band. The converted broadcast signal is transmitted along with the Ku band signal toward the service area.

The satellite control station 130 monitors and controls the operating state of the satellite.

In the satellite broadcast service area, the receiver 140 receives a broadcast signal from the satellite 120 to reproduce a broadcast. However, at a point where signal attenuation is severe due to shadowing or blocking due to a building or a shield, the gap filler 150 relays and transmits a broadcast signal. The gap filler 150 receives the Ku band TDM signal from the satellite 120 and converts the Ku band TDM signal into an S band Code Division Multiplexing (CDM) signal. The receiver 140 in the satellite broadcasting service region demodulates and reproduces a signal having a high intensity among the S band CDM signals received from the satellite 120 and the S band CDM signals received via the gap filler 150. The receiver 140 may be a portable terminal (eg, a mobile communication terminal, a personal digital assistant (PDA), etc.) or a terminal inside a vehicle.

2 is a diagram illustrating a configuration of a general satellite broadcast transmission system.

As shown in FIG. 2, the satellite broadcasting transmission system includes a Reed Solomon encoder (RS Encoder 210a, ..., 210n, 210m), a byte interleaver (Byte Interleaver 220a, ..., 220n, 220m), a convolutional encoder. (Convolutional Encoder 230a, ..., 230n, 230m), a bit interleaver (Bit Interleaver 240a, ..., 240n), and a CDM modulator 250. The transmission system can transmit up to 63 channels of broadcast data using different orthogonal spreading codes for independent broadcasting for each broadcasting station and / or content, and transmits reception synchronization data and control data through a pilot channel. The error correction encoding method uses a concatenated code that connects a Reed-Solomon code (RS code) and a convolutional code, and an error distribution method includes bytes and bits. ) Interleaving method is used. As the outer code, the Reed-Solomon code is divided into a transmission channel and a pilot channel, and the transmission channel uses RS 204 and 188, and the pilot channel uses RS 96 and 80. As the inner code, the convolutional code uses the constraint length K = 7 and r = 2/3, 3/4, 5/6, 7 through code rate r = 1/2 and puncturing the code. Generate a variable code rate of / 8. In the pilot channel, a code rate r = 1/2 code is used. Signals subjected to channel encoding are modulated by the CDM modulator 250. At this time, a 64-bit Walsh code is used to distinguish different broadcast channels, and a 2048-bit m-sequence using a 12-speed shift register is used for a spreading sequence. The modulation scheme uses a QPSK scheme with a roll-off coefficient of 0.22 in a broadcast channel and a BPSK scheme in a pilot channel.

3 is a diagram illustrating a configuration of a general satellite broadcast receiving system.

As shown in FIG. 3, the satellite broadcasting reception system includes a tuner 310a and 310b, a CDM demodulator 320, a bit deinterleaver (Bit Deinterleaver 330a and 330b), a Viterbi decoder (Viterbi Decoder 340a and 340b), The byte deinterleaver 350a and 350b, the Reed Solomon decoders RS Decoder 360a and 360b, the multiplexer MUX 370, and the like are included. Although FIG. 3 illustrates a case where a plurality of tuners 310a and 310b are provided, antenna diversity may not be used in consideration of the size and portability of the portable terminal.

The CDM demodulator 320 is composed of an antenna and a rake synthesizer. The CDM demodulator 320 is synthesized by MRC (Maximal Ratio Combining) according to signal strength and delay through a rake finger, and used as a Walsh code of a desired broadcast channel. Despread.

The output signal of the CDM demodulator 320 is divided into a broadcast channel signal and a pilot channel signal. The broadcast channel signal is restored to audio data and video signals through a channel decoding process, and the pilot channel signal is subjected to a pilot channel decoding process. It is used as control data of 140.

Satellite digital multimedia broadcasting (DMB) using the above-described satellite broadcast transmission system and satellite broadcast reception system may cover a larger area than terrestrial DMB. In addition, as described above, the gap filler 150 is additionally used in a downtown area having a poor reception environment. However, in the shadow area used by the gap filler, the spreading signal orthogonality of the received signal is lost due to the delay and the frequency spread of the received signal due to the multipath channel environment, and the multi-user interface (MUI: Multi-user Interface) is generated. The information is not restored correctly. This problem is a cause of limiting the number of broadcast service channels.

The rake receiver used to solve the above problems guarantees satisfactory performance in the case of a single signal, but has many limitations in performance in the case of multiple signals such as satellite DMB. That is, the rake receiver loses the orthogonality of the spread code by the multipath fading channel, which limits the broadcast channel capacity.

In addition, a data-aided linear receiver and a blind linear receiver that use only a single signal spread code and can be used in a downlink terminal have been proposed, and the performance of the corresponding reception algorithm approaches the minimum mean square error (MMSE) performance. There is a limitation that cannot be applied because there is no cyclostationarity in the symbol unit.

In addition, since the transmission signal of the satellite DMB downlink system is simultaneously transmitted through CDM (Code Division Mulplexing) and reaches the receiving end of the same multipath channel, the MUI of the received signal is generated only by a single channel. Therefore, since it is possible to restore orthogonality of spreading codes and minimize MUI using a single channel equalizer, zero-forcing and MMSE chip equalizers have been proposed. In addition, various equalizer algorithms have been proposed to enable fast fading multipath channel tracking due to discontinuous chip sequences. However, the conventional equalizer algorithms are not suitable for satellite DMB systems. For example, the adaptive equalizer using the blind algorithm has a problem in that the convergence performance is degraded in an environment having a large number of signals, and the adaptive equalizer based on Griffith's algorithm has a problem in that the tracking performance is degraded in a fast fading channel.

Accordingly, an object of the present invention for solving the above problems is the satellite broadcasting reception performance using a chip equalization technique that has excellent Bit Error Rate (BER) performance and can secure more broadcast channels in the same communication environment. It is to provide a method and apparatus for improvement.

Another object of the present invention is to provide a method and apparatus for improving satellite broadcast reception performance using a chip equalization technique having better channel tracking performance than a conventional chip equalization technique in mobile reception.

In order to achieve the above objects, according to an aspect of the present invention, in the chip equalizer of the satellite broadcast receiver for recovering the broadcast data signal corresponding to the selected channel from the received satellite broadcast signal, the satellite broadcast signal received through a tuner Computing a first bit signal using the first region pilot data included in the first bit signal, and the difference between the reference pilot signal calculated using pilot data previously recognized corresponding to the first bit signal and the first region pilot data. A first equalizer for updating the default tap coefficients to the first tap coefficients using the corresponding first error values; After generating the reconstructed pilot signal using the satellite broadcast signal received through the tuner after the first tap coefficient and the predetermined delay time elapsed, the reconstructed pilot signal and the first region pilot data are previously recognized. A second equalizer for updating the first tap coefficient to a second tap coefficient by using a second error value corresponding to a difference of a reference pilot signal calculated using pilot data; And a detector for restoring broadcast data using the satellite broadcast signal received through the tuner after the second tap coefficient and a preset double delay time, and delivering the recovered broadcast data to a broadcast channel decoder. The first region pilot data is provided with a chip equalizer of a satellite broadcasting receiver including a pilot symbol (PS) and a unique word (D1), and the chip coefficient updating method and the chip coefficient updating apparatus described above are provided.

을 이용하여 갱신할 수 있다. 여기서,

는 갱신된 스텝 사이즈,

는 직전의 스텝 사이즈,

는

중 임의의 값을 가지는 상수 변수,

는

중 임의의 값을 가지는 상수 변수,

는 추정 에러 전력을 의미한다.At least one of the first equalizer and the second equalizer of the chip equalizer may calculate a step size for updating the tap coefficient.

Can be updated using. here,

Is the updated step size,

Is the previous step size,

Is

Constant variable with any value of

Is

Constant variable with any value of

Means estimated error power.

At least one of the first equalizer and the second equalizer of the chip equalizer uses the maximum step size when the step size updated by the equation is equal to or larger than a preset maximum step size, and the updated step. When the size is less than or equal to the preset minimum step size, the minimum step size can be used.

에 의해 산출될 수 있다. 여기서,

는

중 임의의 값을 가지는 가중 변수,

는 이전 단계들에서 입력된 에러값들의 평균값,

는 현재 산출된 에러값으로 상기 제1 에러값 또는 상기 제2 에러값을 나타낸다.The estimated error power is

Can be calculated by here,

Is

A weighted variable with any value of,

Is the average of the error values entered in the previous steps,

Denotes the first error value or the second error value as a currently calculated error value.

Any one of the first equalizer and the second equalizer calculates a second bit signal using second area pilot data included in the satellite broadcast signal, and determines the second bit signal and the second bit signal. update the first tap coefficient or the second tap coefficient to a third tap coefficient by using a third error value corresponding to the difference of the decision directed value, and update the third tap coefficient to the second equalizer or the The second area pilot data may be transmitted to a detector, and the second area pilot data may include D2 (frame counter) to D51.

The first equalizer is the satellite broadcast formed of 64 blocks in which Walsh codes and PN code sequence combinations used for a common pilot corresponding to 64 chips are shifted at chip unit intervals in order to update the tap coefficients. Receiving a signal; Generating a recovery bit signal by multiplying the default tap coefficients corresponding to each of the 64 blocks; Updating a default tap coefficient to a first tap coefficient using a first error value corresponding to a difference between the first bit signal corresponding to the sum of the restored bit signals and the reference pilot signal; And transferring the first tap coefficient to the second equalizer.

The second equalizer is the satellite broadcast formed of 64 blocks in which Walsh codes and PN code sequence combinations used in a common pilot corresponding to 64 chips are shifted at chip unit intervals in order to update the tap coefficients. Receiving a signal; Restoring a channel compensated pilot signal by summing respective multiplication values calculated by multiplying the first tap coefficients corresponding to each of the 64 blocks; Generating the reconstructed pilot signal by multiplying the channel compensated pilot signal by a spread code; Updating the first tap coefficient to a second tap coefficient using a second error value corresponding to the difference between the restored pilot signal and the reference pilot signal; And transferring the second tap coefficient to a detector.

According to a preferred embodiment of the present invention, a chip equalizer of a satellite broadcast receiver for recovering a broadcast data signal corresponding to a selected channel from a received satellite broadcast signal, the first signal included in the satellite broadcast signal received through a tuner A first bit signal is calculated using area pilot data, and a first error corresponding to a difference between a reference pilot signal calculated using pilot data previously recognized corresponding to the first bit signal and the first area pilot data. A first equalizer for updating tap coefficients using a value, wherein the first area pilot data are a pilot symbol (PS) and a unique word (D1); After generating the reconstructed pilot signal by using the tap coefficient updated by the first equalizer and the satellite broadcast signal received through the tuner after a preset delay time has elapsed, the reconstructed pilot signal and the first region pilot data are generated. A second equalizer which re-updates the updated tap coefficients using a second error value corresponding to a difference of a reference pilot signal calculated using pilot data previously recognized in correspondence with the corresponding pilot data; And restoring broadcast data by using the tap coefficient updated by the second equalizer and the satellite broadcast signal received through the tuner after a preset double delay time, and transmitting the restored broadcast data to the broadcast channel decoding unit. And a detector configured to calculate a second bit signal using second area pilot data included in the satellite broadcast signal, wherein the first equalizer and the second equalizer The tap coefficient is updated again by using a third error value corresponding to the difference of the decision directed value of the 2-bit signal, and then the updated tap coefficient is transmitted to the second equalizer or the detector, and the second region is updated. The pilot data is provided with a chip equalizer of the satellite broadcast receiver including D2 (frame counter) to D51, and the chip coefficient updating method and the chip coefficient updating apparatus described above are provided.

을 이용하여 갱신할 수 있다. 여기서,

는 갱신된 스텝 사이즈,

는 직전의 스텝 사이 즈,

는

중 임의의 값을 가지는 상수 변수,

는

중 임의의 값을 가지는 상수 변수,

는 추정 에러 전력을 나타낸다.At least one of the first equalizer and the second equalizer of the chip equalizer may calculate a step size for updating the tap coefficient.

Can be updated using. here,

Is the updated step size,

The previous step size,

Is

Constant variable with any value of

Is

Constant variable with any value of

Denotes the estimated error power.

At least one of the first equalizing unit and the second equalizing unit uses the maximum step size when the step size updated by the above equation is equal to or greater than a preset maximum step size, and the updated step size is the minimum set in advance. When it is less than a step size, the said minimum step size can be used.

에 의해 산출될 수 있다. 여기서,

는

중 임의의 값을 가지는 가중 변수,

는 이전 단계들에서 입력된 에러값들의 평균값,

는 현재 산출된 에러값으로 상기 제1 에러값 또는 상기 제2 에러값을 나타낸다.The estimated error power is

Can be calculated by here,

Is

A weighted variable with any value of,

Is the average of the error values entered in the previous steps,

Denotes the first error value or the second error value as a currently calculated error value.

According to another aspect of the present invention, a tap coefficient updating method for updating a tap coefficient of a chip equalizer, the method comprising: sequentially storing input error values; Calculating an average error value by giving a weight corresponding to immediately preceding error values except for the last error value inputted; Calculating an estimated error power by giving a weight corresponding to each of the average error value and the last error value; Calculating an update step size by giving a weight corresponding to each of the estimated error power and the current step size; There is provided a tap coefficient updating method of a chip equalizer including calculating an update tap coefficient by using the update step size and a current tap coefficient, and a chip equalizer and equalization enabling the tap coefficient updating method to be performed. An apparatus and a program are provided.

에 의해 산출될 수 있다. 여기서,

는 갱신 스텝 사이즈,

는 현재 스텝 사이즈,

는

중 임의의 값을 가지는 상수 변수,

는

중 임의의 값을 가지는 상수 변수,

는 상기 추정 에러 전력을 나타낸다.The update step size is

Can be calculated by here,

Is the update step size,

Is the current step size,

Is

Constant variable with any value of

Is

Constant variable with any value of

Denotes the estimated error power.

The maximum step size is used when the update step size calculated by the above formula is equal to or larger than the preset maximum step size, and when the calculated update step size is less than or equal to the preset minimum step size, the minimum step size is used. When the calculated update step size is less than or equal to the maximum step size and more than the minimum step size, the calculated update step size may be used.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a diagram illustrating a satellite broadcast receiving system according to an exemplary embodiment of the present invention, and FIG. 5 is a diagram illustrating a frame structure of a general baseband transmission signal. 6 is a view showing the configuration of the first equalizing unit according to an embodiment of the present invention, Figure 7 is a view showing the configuration of a second equalizing unit according to an embodiment of the present invention. 8 is a diagram illustrating a configuration of an equalizer for performing a tap update using a control data section according to an exemplary embodiment of the present invention, and FIG. 9 is a diagram illustrating a configuration of a detector according to an exemplary embodiment of the present invention. .

Referring to FIG. 4, the chip equalizer 410 according to the present invention may include a first equalizer 420, a first bit delay unit 425, a second equalizer 430, and a second equalizer 430. And a bit delay unit 435 and a detector 440. The equalizer tap g (i) update is sequentially performed in the first equalizer 420 and the second equalizer 430 by using a pilot signal corresponding to Walsh code 0. That is, the pilot data (ie, PS and D1) recognized by the receiver 140 are used by both the first equalizer 420 and the second equalizer 430 for updating the equalizer tap g (i). And other control data (ie, D2 to D51) are used only by either equalizer 420 or 430.

The frame structure of the baseband transmission signal of the gap filler 150 which transmits a broadcast signal to a downtown shadow area is illustrated in FIG. 5. As shown in Fig. 5, the frame structure consists of a basic frame of 12.75 ms. The six basic frames make up a 76.5ms super frame. Each broadcast channel is a QPSK signal composed of 816 bytes (6528 bits), and is composed of 408 bytes of I (In-Phase) channel and Q (Quadrature-Phase) channel. The pilot channel assigned to Walsh code 0 is used for frame synchronization and transmission of control data, and a pilot symbol (PS) and control data (Di) are configured in units of 125 ms. One pilot channel frame consists of 102 blocks composed of 32 bits (ie, 125 ms, 2048 chips). That is, one pilot channel frame is composed of all 51 pilot symbols PS and 51 control data Di (where i = 1, 2, ..., 51). The first control data of the pilot channel, D1, is a unique word for frame synchronization. The pilot symbols are sent in the order of “11111111 11111111 11111111 11111111”, and the unique word D1 is sent in the order of “01101010 10110101 01011001 10001010”. The pilot symbol PS and the unique word D1 are pilot data already recognized by the receiver 140.

Hereinafter, a process of updating an equalizer tap and reconstructing a broadcast signal of a requested channel will be described with reference to FIGS. 6 to 9.

6 shows a configuration of the first equalizing unit 420. Each component of the first equalizer 420 is not necessarily implemented in a hardware configuration, but may be implemented in the form of a software program or in the form of a System on Chip (SoC).

Referring to FIG. 6, the first equalizer 420 obtains channel information by using pilot data (that is, pilot symbol PS and unique word D1) that recognizes a pilot signal included in a received broadcast signal. The tap coefficient is updated using the obtained channel information. That is, the first equalizer 420 updates the tap coefficient by using the received signal error power (that is, the difference between the pilot signal and the received pilot signal recognized by the receiver). The first equalizer 420 is a chip unit delay unit (610a, 610b, ..., 610n-hereinafter, 610), the first multipliers (620a, 620b, ..., 620n-620) Tab update unit including first adders 630a, 630b, ..., 630n-referred to as 630, and a plurality of second multipliers 642a, 642b, ..., 642n-referred to as 642). 640, a second adder 650, an adder 660, and a step size adjusting unit 670.

를 칩 단위 지연기(610)를 이용하여 칩 길이(

)만큼 지연하여 각각 상응하는 제1 곱셈기(620)로 입력한다. 여기서 i는 비트 신호의 순번을 의미한다 또한, N-1+n은 i번째 비트 신호 내의 칩 순번을 의미하고, N은 스프레딩 팩터(Spreading Factor)로서 64이며, n은 0부터 63 중의 임의의 숫자이고, N-1+n의 값이 64가 되면 다시 1로 인식된다. 수신 비트 신호는 64개의 칩에 해당하는 공통 파일럿(common pilot)에 사용된 왈쉬(Walsh) 부호와 유사 잡음 코드(PN code : Pseudorandom Noise code) 시퀀스 조합을 칩 단위 간격으로 이동된 64개의 블록으로 형성되며, 한 블록의 합은 하나의 비트 단위가 된다. 이와 같이 생성된 비트 신호 64개가 입력되는 것이다.The first equalizer 420 receives the received bit signal spread by the Walsh code.

By using the chip unit delay unit 610

Delay by) and input to the corresponding first multiplier 620, respectively. Where i denotes the sequence number of the bit signal, and N-1 + n denotes the chip sequence number in the i-th bit signal, N is 64 as a spreading factor, and n is any of 0 to 63. It is a number, and when N-1 + n becomes 64, it is recognized as 1 again. The received bit signal is formed of 64 blocks shifted at chip-by-chip intervals using a Walsh code and a Pseudorandom Noise code (PN code) sequence combination used in a common pilot corresponding to 64 chips. The sum of one block is one bit unit. 64 bit signals generated in this way are input.

)를 순차적으로 곱하여 출력한다.The first multiplier 620 is a spreading code consisting of a Walsh 0 code and a PN code used for the pilot signal on the correspondingly delayed received bit signal.

) And multiply sequentially.

)를 구한다. 채널 정보를 포함하는 복원된 파일럿 신호(

)를 구하기 위하여 하기 의 수학식 1이 적용될 수 있다.The first adder 630 adds 64 multiplied values sequentially input from the corresponding first multiplier 620 to restore the pilot signal including the channel information.

) A reconstructed pilot signal containing channel information (

Equation 1 below can be applied to find.

)를 현재 설정된 각각의 탭 계수

과 곱하여 제2 가산기(650)로 전달한다. 당해 탭 계수는 1 x n 벡터인

을 나타낸다.Subsequently, the second multiplier 642 may each use a reconstructed pilot signal (including the channel information input from the corresponding first adder 630).

Each tap coefficient currently set

It multiplies by and transfers it to the second adder 650. The tap coefficient is a 1 xn vector

Indicates.

)를 산출하여 덧셈기(660)로 전달한다. 제2 가산기(650)는 비트 신호(

)를 산출하기 위하여 하기 수학식 2를 이용할 수 있다. The second adder 650 adds N values input from each second multiplier 642 to add a bit signal (

) Is calculated and transferred to the adder 660. The second adder 650 is a bit signal (

Equation 2 can be used to calculate

)는 음수 형태로 입력된다. 덧셈기(660)는 이미 알고있는 파일럿 데이터(즉, 파일럿 심볼(PS) 및 유니크 워드(D1))를 이용하여 산출된 기준 파일럿 신호(

)와 제2 가산기(650)로부터 입력되는 비트 신호(

)의 차를 이용하여 제1 에러값(

)을 산출한다. 제1 에러 값(

)을 산출하기 위해 하기 수학식 3이 이용될 수 있다.At this time, the bit signal transmitted to the adder 660 (

) Is entered in negative form. The adder 660 may calculate a reference pilot signal calculated by using known pilot data (that is, the pilot symbol PS and the unique word D1).

) And the bit signal input from the second adder 650

By using the difference of the first error value (

) Is calculated. First error value (

Equation 3 may be used to calculate

)를 갱신하고, 갱신된 스텝 사이즈()를 탭 업데이트부(640)로 전달한다. 스텝 사이즈 조절부(670)에서 스텝 사이즈(

)를 갱신하는 방법에 대해서는 이후 관련 도면을 참조하여 상세히 설명한다.Then, the calculated first error value is transmitted to the step size adjusting unit 670. The step size adjusting unit 670 uses a step size LMS (WMAVS LMS: LMS Algorithm using Weighted Moving-Average) to convert the step size (WMAVS LMS).

), And the updated step size ( ) Is transmitted to the tap update unit 640. In the step size adjusting unit 670, the step size (

) Will be described in detail later with reference to the accompanying drawings.

)를 이용하여 각각의 제2 곱셈기(642)에 상응하는 탭 계수를 갱신한다. 탭 업데이트부(640)가 탭 계수를 갱신하기 위하여 하기 수학식 4가 이용될 수 있다.The tap update unit 640 receives the step size (received from the step size controller 670).

) Is used to update the tap coefficient corresponding to each second multiplier 642. Equation 4 may be used to update the tap coefficient by the tap update unit 640.

는 스텝 사이즈의 켤레 복소수를 의미한다.here,

Denotes a complex conjugate of step size.

In addition, the tap update unit 640 transmits the updated tap coefficient to the tap update unit 720 of the second equalizer 430.

The configuration of the second equalizing unit 430 is shown in FIG. 7. Each component of the second equalizer 430 is not necessarily implemented as a hardware configuration, but may be implemented in the form of a software program or in the form of a System on Chip (SoC).

Referring to FIG. 7, the second equalizer 430 compensates for and removes channel information carried on the pilot signal by using the tap coefficient updated by the first equalizer 420, and then restores the pilot signal to restore the pilot signal. The channel coefficients remaining in the data are obtained again to update the tap coefficients again. The second equalizer 430 is a chip unit delay unit 710a, 710b, ..., 710n-hereinafter referred to as 710, a plurality of first multipliers 725a, 725b, ..., 725n-below Tap update unit 720 including 725), first adders 730a, 730b, ..., 730n-referred to as 730, and second multipliers 740a, 740b, ..., 740n-740 And a second adder 750, an adder 760, and a step size adjusting unit 770.

) 후에 입력받는다. 제2 등화부(430)는 왈쉬 부호에 의해 확산된 수신 비트 신호

를 칩 단위 지연기(710)를 이용하여 칩 길이(

)만큼 지연하여 각각 상응하는 제1 곱셈기(725)로 입력한다.The second equalizer 430 compares the same received bit signal to the first equalizer 420 by the first bit delay unit 425.

After input. The second equalizer 430 receives the received bit signal spread by the Walsh code.

By using the chip unit delay unit 710

Delays by) and inputs them to the corresponding first multipliers 725.

를 이용하여 곱셈값을 산출한다. 이때, 제1 곱셈기(725)는 n을 0부터 63에서 1씩 순차적으로 증가시킴으로써 64개의 곱셈값을 산출하여 각각 상응하는 제1 가산기(730)로 전달한다. The first multiplier 725 receives the tap coefficient received from the first equalizer 420.

Calculate the multiplication using. In this case, the first multiplier 725 calculates 64 multiplication values by sequentially increasing n from 0 to 63 by 1, and transmits the 64 multipliers to corresponding first adders 730.

)를 복원한다. 채널 보상된 파일럿 신호(

)를 복원하기 위하여 하기 수학식 5가 이용될 수 있다.The first adder 730 is a channel-compensated pilot signal by summing 64 multiplication values input from the corresponding first multiplier 725.

Restore). Channel compensated pilot signal (

Equation 5 may be used to restore

The first adder 730 then delivers the reconstructed channel compensated pilot signal to the corresponding second multiplier 740, respectively.

)에 왈쉬 0번 부호 및 PN 시퀀스로 이루어진 확산 부호

를 각각 곱한다. The second multiplier 740 is a channel compensated pilot signal (

Spreading code consisting of Walsh 0 code and PN sequence

Multiply by.

, 이하 복원 파일럿 신호라 칭함)를 생성한다. 제2 가산기(750)가 복원 파일럿 신호를 생성하기 위하여 하기 수학식 6을 이용할 수 있다.Subsequently, the second adder 750 adds the multiplication values (ie, 64 multiplication values) received from the respective second multipliers 740 to compensate and remove the channel information, and restores the pilot signal (

, Hereinafter referred to as a reconstructed pilot signal. The second adder 750 may use Equation 6 to generate a reconstructed pilot signal.

)와 덧셈기(760)로부터 입력되는 복원 파일럿 신호(

)의 차를 이용하여 제2 에러값(

)을 산출한다. 이어서 산출된 제2 에러값을 스텝 사이즈 조절부(770)로 전달한다. 스텝 사이즈 조절부(670)는 가중치 이동 평균을 이용한 변환 스텝 LMS(WMAVS LMS : LMS Algorithm using Weighted Moving-Average)를 이용하여 스텝 사이즈(

)를 갱신하고, 갱신된 스텝 사이즈(

)를 탭 업데이트부(720)로 전달한다. 스텝 사이즈 조절부(770)에서 스텝 사이즈(

)를 갱신하는 방법에 대해서는 이후 관련 도면을 참조하여 상세히 설명한다. The second adder 750 transfers the reconstructed pilot signal calculated using the above equation to the adder 760. At this time, the reconstructed pilot signal transmitted to the adder 760 is input in a negative form. The adder 760 uses the pilot data (ie, the pilot symbol PS and the unique word D1) that are already known to the reference pilot signal (

) And a reconstructed pilot signal input from the adder 760

Using the difference of the second error value (

) Is calculated. Next, the calculated second error value is transmitted to the step size adjusting unit 770. The step size adjusting unit 670 uses a step size LMS (WMAVS LMS: LMS Algorithm using Weighted Moving-Average) to convert the step size (WMAVS LMS).

), And the updated step size (

) Is transmitted to the tap update unit 720. In the step size adjusting unit 770, the step size (

) Will be described in detail later with reference to the accompanying drawings.

)를 이용하여 제1 곱셈기(725)에 상응하는 탭 계수를 갱신한다. 탭 업데이트부(720)가 탭 계수를 갱신하기 위하여 하기 수학식 7이 이용될 수 있다.The tap update unit 720 receives the step size (received from the step size controller 770).

) To update the tap coefficient corresponding to the first multiplier 725. Equation 7 may be used to update the tap coefficient by the tap update unit 720.

In addition, the tap update unit 720 transmits the updated tap coefficient to the detector 440 to recover the broadcast channel. In this case, the pilot signal may be immediately transmitted to the Viterbi decoder 340b.

Until now, the chip equalizer 410 according to the present invention performs the tap coefficient updating process in two steps by using pilot data (that is, the pilot symbol PS and the unique word D1) already recognized by the receiver 140. Explained.

However, the pilot signal used for satellite DMB further includes a control data section (ie, a D2 to D51 section). However, since the signal of the control data section cannot be recognized in advance by the receiver 140, a decision directed technique is applied.

8 shows the configuration of an equalizer for updating tap coefficients using signals in the control data section. That is, the equalizer for updating the tap coefficient by using the signal of the control data section may be applied very similarly to the configuration of the first equalizer 420 or the second equalizer 430 described above. FIG. 8 illustrates a case where the first equalizer 420 is applied very similarly.

)을 생성하여 기준 비트 신호로 이용한다. 그리고, 비트 신호 판정값(

)과 제2 가산기(650)로부터 입력되는 비트 신호(

)의 차를 이용하여 제3 에러값(

)을 산출한다. 산출 된 제3 에러값은 탭 업데이트부(670)로 전달되고, 탭 업데이트부(670)는 가중치 이동 평균을 이용한 변환 스텝 LMS(WMAVS LMS)를 이용하여 스텝 사이즈(

)를 갱신하고, 갱신된 스텝 사이즈(

)를 탭 업데이트부(640)로 전달한다. 또한, 탭 업데이트부(640)는 업데이트된 탭 계수를 검출기(440)로 전달한다. 물론, 도 8에 도시된 등화부가 제1 등화부(420)와 통합되어 구성된 경우 업데이트된 탭 계수는 제2 등화부(430)를 경유하여 검출기(440)로 전달될 것이다. 또한, 이 경우 제1 등화부(420)는 도 6을 참조하여 설명한 탭 계수 업데이트 및 도 8을 참조하여 설명한 탭 계수 업데이트를 통해 각각 업데이트된 탭 계수를 순차적으로 또는 하나의 탭 계수로 갱신하여 제2 등화부(430)로 전달할 수 있다.However, since the signal of the control data section cannot be recognized in advance by the receiver 140, the equalizer further includes a determiner 810 for decision directed. That is, the equalizer uses the determiner 810 to determine the bit signal determination value (

) Is used as a reference bit signal. Then, the bit signal determination value (

) And a bit signal input from the second adder 650

Using the difference of the third error value (

) Is calculated. The calculated third error value is transmitted to the tap update unit 670, and the tap update unit 670 uses a step size (WMAVS LMS) using a conversion step LMS (WMAVS LMS) using a weighted moving average.

), And the updated step size (

) Is transmitted to the tap update unit 640. In addition, the tap update unit 640 transmits the updated tap coefficient to the detector 440. Of course, if the equalizer shown in FIG. 8 is configured to be integrated with the first equalizer 420, the updated tap coefficient will be transmitted to the detector 440 via the second equalizer 430. In this case, the first equalizer 420 updates the tap coefficients updated sequentially or with one tap coefficient through the tap coefficient update described with reference to FIG. 6 and the tap coefficient update described with reference to FIG. 8. It may be delivered to the two equalizer 430.

From the above description, those skilled in the art will appreciate that the equalizer shown in FIG. 8 may be integrated with the first equalizer 420. In addition, as described above, the equalizer shown in FIG. 8 may be integrated with the second equalizer 430. That is, the chip equalizer 410 according to the present invention may further include a one-step process for updating the tap coefficient by using the signal of the control data interval.

를 이용하여 수신 비트 신호

의 채널 정보를 보상 및 제거한 후 수신자가 원하는 방송 채널에 상응하는 확산 신호

를 곱하여 더함으로써 원하는 방송 신호를 복원한다. 이하 검출기(440)의 동작을 구체적으로 설명한다.9 illustrates a configuration of a detector 440 for reconstructing broadcast data by using the tap coefficient received from the second equalizer 430. The detector 440 receives the tap coefficient received from the second equalizer 430.

Receive bit signal using

After compensating and removing the channel information of the receiver, the spread signal corresponding to the broadcast channel desired by the receiver

Multiply by to restore the desired broadcast signal. Hereinafter, the operation of the detector 440 will be described in detail.

Referring to FIG. 9, the detector 440 may include a chip unit delay unit 910a, 910b,..., 910n-910, plural first multipliers 920a, 920b,... 920n-referred to as 920, the tap coefficient applying unit 925, the first adders (930a, 930b, ..., 930n-referred to as 930), the second multipliers (940a, 940b, ..., ...) 940n-hereafter referred to as 940), a second adder 950, and a determiner 960.

) 후에 입력받는다. 이는 제1 등화부(420) 및 제2 등화부(430)에서의 탭 계수 업데이트를 위한 시간을 보상하기 위한 것이다. 검출기(440)는 왈쉬 부호에 의해 확산된 수신 비트 신호

를 칩 단위 지연기(910)를 이용하여 칩 길이(

)만큼 지연하여 각각 상응하는 제1 곱셈기(920)로 입력한다.The detector 440 has the same received bit signal as the first equalizer 420 at twice the delay time predetermined by the second bit delay unit 435 (

After input. This is to compensate for the time for tap coefficient update in the first equalizer 420 and the second equalizer 430. Detector 440 receives received bit signal spread by Walsh code

By using the chip unit delay unit 910

Delay by) and input to the corresponding first multiplier 920, respectively.

를 이용하여 곱셈값을 산출한다. 이때, 제1 곱셈기(725)는 n을 0부터 63에서 1씩 순차적으로 증가시킴으로써 64개의 곱셈값을 산출하여 각각 상응하는 제1 가산기(930)로 전달한다. The first multiplier 920 receives the tap coefficient received from the second equalizer 430.

Calculate the multiplication using. In this case, the first multiplier 725 calculates 64 multiplication values by sequentially increasing n from 0 to 63 by 1, and delivers the 64 multiplication values to the corresponding first adder 930.

를 복원한다. 채널 보상된 데이터 신호

를 복원하기 위하여 하기 수학식 8이 이용될 수 있다.The first adder 930 is a channel-compensated data signal corresponding to the broadcast channel to be restored by summing 64 multiplication values input from the corresponding first multiplier 920, respectively.

Restore it. Channel compensated data signal

Equation 8 may be used to restore the equation.

The first adder 730 then delivers the channel compensated reconstruction data signal to the corresponding second multiplier 940, respectively.

에 복원하고자 하는 방송 채널에 상응하는 확산 부호

를 각각 곱한다. The second multiplier 940 is channel compensated data signal

Spread code corresponding to the broadcast channel to be restored to

Multiply by.

, 이하 복원 데이터 신호라 칭함)를 생성한다. 제2 가산기(950)는 복원 데이터 신호를 생성하기 위하여 하기 수학식 9를 이용할 수 있다.Subsequently, the second adder 960 adds the multiplication values (that is, 64 multiplication values) received from the respective second multipliers 940 to compensate and remove the channel information, and restore and restore the data signal (

, Hereafter referred to as a reconstruction data signal. The second adder 950 may use Equation 9 to generate a reconstructed data signal.

The second adder 950 transfers the reconstructed data signal calculated using the above equation to the determiner 960. The determiner 960 transmits a determination value corresponding to the input reconstruction data signal to the bit deinterleaver 330a. The determiner 960 may use Equation 10 to generate and output a decision value.

10 is a diagram illustrating a transform step size LMS algorithm using a moving average for tap coefficient updating according to an exemplary embodiment of the present invention, and FIG. 11 is a diagram illustrating a conventional rake receiver and a conventional chip equalizer. 12 is a graph comparing Uncoded BER performance, and FIG. 12 is a graph comparing Uncoded BER performance of the present invention and a conventional chip equalizer.

Referring to FIG. 10, a tap update unit 640 or 720 that performs a transform step size LMS (Least Mean Square) algorithm using a moving average for tap coefficient updating may include a storage unit 1010 and a plurality of first multipliers 1020a. , 1020b, ..., 1020n-hereinafter referred to as 1020), adder 1030, first multiplier 1035, first adder 1040, second multiplier 1045, third multiplier 1050, second Adder 1055, squarer 1060, fourth multiplier 1065, fifth multiplier 1070, third adder 1075, comparator 1080, sixth multiplier 1085, fourth adder 1090 It includes.

와 곱하여져 가산기(1030)로 입력된다. 가산기(1030)는 복수의 제1 곱셈기(1020)로부터 입력되는 곱셈값을 합산하여 합산 에러값

을 생성한다. 제1 곱셈기(1035)는 가산기(1030)에 의해 생성된 합산 에러값

을 각 가중치 인자들의 합의 역수

를 곱하여 평균 에러값

를 생성한다. 제1 곱셈기(1035)에 의해 생성된 평균 에러값은 하기 수학식 11과 같이 표현될 수 있다.The storage unit 1010 stores an error value (ie, a first error value or a second error value) input from the adder 660 or 760. Each error value stored in the storage unit 1010 is respectively weighted by the first multiplier 1020.

It is multiplied by and is input to the adder 1030. The adder 1030 adds multiplication values input from the plurality of first multipliers 1020 to add up an error value.

Create The first multiplier 1035 has a sum error value generated by the adder 1030.

Is the inverse of the sum of the weighting factors.

Multiply by the mean error

Create The average error value generated by the first multiplier 1035 may be expressed by Equation 11 below.

의 차(즉,

)를 생성하여 제2 곱셈기(1045)와 제3 곱셈기(1050)로 전달한다. 여기서 가중 변수

는

중 임의의 값이다.The first adder 1040 is a random number (eg, 1) and a weighting factor.

Difference (i.e.

) Is generated and transmitted to the second multiplier 1045 and the third multiplier 1050. Where weight variables

Is

Is any value.

The second multiplier 1045 multiplies the value input from the first adder 1040 by the average error value and transmits the multiplier to the second adder 1055. In addition, the third multiplier 1050 multiplies the currently input error value by a weighted variable and transmits the multiplier to the second adder 1055.

를 산출한 후, 제곱기(1060)로 전달한다. 제2 덧셈기(1055)에 의해 산출된 추정 에러 전력

은 하기 수학식 12와 같이 표시될 수 있다.The second adder 1055 adds the values input from the second multiplier 1045 and the third multiplier 1050 to estimate the error power.

After calculating the result, it passes to the squarer (1060). Estimated Error Power Calculated by Second Adder 1055

May be represented by Equation 12 below.

를 추정 에러 전력의 제곱값에 곱한 후 제3 덧셈기(1075)로 전달한다. 여기서, 제1 상수 변수

는

인 상수값이다. 또한 제5 곱셈기(1070)는 종전의 스텝 사이즈

에 제2 상수 변수

를 곱한 후 제3 덧셈기(1075)로 전달한다. 여기서 제2 상수 변수

는

중 임의의 값이다.Squarer 1060 squares the estimated error power and passes it to fourth multiplier 1065. The fourth multiplier 1065 is a first constant variable

Is multiplied by the square of the estimated error power and then passed to the third adder 1075. Where the first constant variable

Is

Is a constant value. In addition, the fifth multiplier 1070 is a conventional step size

On the second constant variable

After multiplying by and passes to a third adder (1075). Where the second constant variable

Is

Is any value.

를 산출한다. 변환 스텝 사이즈

는 하기 수학식 13과 같이 표시될 수 있다.The third adder 1075 adds the multiplication values input from the fourth multiplier 1065 and the fifth multiplier 1070 to convert the step size.

To calculate. Conversion step size

May be represented by Equation 13 below.

The comparator 1080 determines whether the conversion step size input from the third adder 1075 satisfies a predetermined condition and outputs a determination value. If the conversion step size is equal to or greater than a predetermined maximum value, the maximum value is output. When the conversion step size is equal to or smaller than a predetermined minimum value, the minimum value is output. If the conversion step size falls within a range of a predetermined maximum value and minimum value, the input conversion step size is output. That is, when the estimated error power is large, the step size is increased to increase the convergence speed, and when the estimated error power is small, the step size is reduced to minimize misadjustment. This step size variation can speed up channel estimation.

The output transform step size is multiplied by the received bit signal in the sixth multiplier 1085 and then summed with the previous tap coefficient in the fourth adder 1090 to generate an updated tap coefficient.

As described above, the transform step size LMS algorithm using the moving average for updating the tap coefficient according to the present invention stores an error obtained in the chip equalization process in a space of length L, and differs in the stored error value. By multiplying and adding the weighted values, information about past errors, not instantaneous errors, can be considered.

FIG. 11 shows a graph of uncoded BER results of a conventional Rake receiver and a conventional chip equalizer in a 6-path IMT multipath Rayleigh fading environment. In the case of the Rake receiver, perfect channel estimation is assumed. In the case of the conventional chip equalizer, the most optimized value of BER is used among the step sizes used in the LMS.

Compared to the average BER before the error floor appears in the Rake receiver 30 broadcast channel, the conventional chip equalizer has a gain of about 5 dB. In addition, the BER performance of the 63 equalizer channels of the chip equalizer is comparable to that of the 30 broadcast channels of the rake receiver. Therefore, it can be seen that there is a gain of 33 broadcast channels when using the conventional chip equalizer.

는

을 사용하고 0.001 샘플 간격의 인터폴레이션을 하였다. 또한, 본 발명에 따른 칩 등화기는 각각의 파라미터값으로서 가중 변수

는 0.8, 제1 상수 변수

는 0.02, 제2 상수 변수

는 0.9, 길이 L은 5, 스텝 사이즈의 최소값

은 0.005, 스텝 사이즈의 최대값

는 0.05가 적용되었다. FIG. 12 illustrates a graph of uncoded BER results when a conventional chip equalizer and a chip equalizer according to the present invention are applied to a mobile receiving system traveling at 50 km per hour. Where the Doppler frequency is 122.4 Hz, Doppler spread

Is

And interpolation of 0.001 sample intervals. In addition, the chip equalizer according to the present invention is a weighted variable as each parameter value.

Is 0.8, the first constant variable

Is 0.02, the second constant variable

Is 0.9, the length L is 5, the minimum value of the step size

Is 0.005, the maximum step size

0.05 was applied.

As shown in FIG. 12, the error floor of the conventional chip equalizer is increased in the case of a mobile object reception of 50 km per hour, but the chip equalizer of the present invention is almost unchanged. The 45 broadcast channels of the conventional equalizer and the 63 broadcast channels of the chip equalizer according to the present invention show the same performance. In other words, it can be seen that the chip equalizer according to the present invention has a performance similar to that of the 30 broadcast channel Rake receiver in a 63 broadcast channel environment, and is better than the conventional chip equalizer due to the low error floor.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the method and apparatus for improving satellite broadcast reception performance using the chip equalization technique according to the present invention have excellent Bit Error Rate (BER) performance and can secure more broadcast channels in the same communication environment. There is an advantage.

In addition, the present invention has an advantage of better channel tracking performance than conventional chip equalization techniques in mobile reception.

Claims (14)

In the chip equalizer of the satellite broadcast receiver for recovering the broadcast data signal corresponding to the selected channel from the received satellite broadcast signal, A first bit signal is calculated using first region pilot data included in the satellite broadcast signal received through a tuner, and pilot information previously recognized corresponding to the first bit signal and the first region pilot data is used. A first equalizer for updating the default tap coefficients to the first tap coefficients by using a first error value corresponding to the difference of the reference pilot signal calculated by using a first tap coefficient; After generating the reconstructed pilot signal using the satellite broadcast signal received through the tuner after the first tap coefficient and the predetermined delay time elapsed, the reconstructed pilot signal and the first region pilot data are previously recognized. A second equalizer for updating the first tap coefficient to a second tap coefficient by using a second error value corresponding to a difference of a reference pilot signal calculated using pilot data; And And a detector for restoring broadcast data using the satellite broadcast signal received through the tuner after the second tap coefficient and a preset double delay time, and delivering the recovered broadcast data to a broadcast channel decoding unit. And the first region pilot data includes a pilot symbol (PS) and a unique word (D1). The method of claim 1, At least one of the first equalizer and the second equalizer may include: a chip equalizer of the satellite broadcast receiver for updating the step size for updating the tap coefficient by using the following equation;

here,

Is the updated step size,

Is the previous step size,

Is

Constant variable with any value of

Is

Constant variable with any value of

Represents the estimated error power. The method of claim 2, At least one of the first equalizing unit and the second equalizing unit uses the maximum step size when the step size updated by the above equation is equal to or greater than a preset maximum step size, and the updated step size is the minimum set in advance. The chip equalizer of the satellite broadcasting receiver using the minimum step size when the step size is smaller than the step size. The method of claim 2, The estimated error power of the chip equalizer of the satellite broadcasting receiver calculated by the following equation;

here,

Is

A weighted variable with any value of,

Is the average of the error values entered in the previous steps,

Is a currently calculated error value and is the first error value or the second error value. The method of claim 1, Any one of the first equalizer and the second equalizer calculates a second bit signal using second area pilot data included in the satellite broadcast signal, and determines the second bit signal and the second bit signal. update the first tap coefficient or the second tap coefficient to a third tap coefficient by using a third error value corresponding to the difference of the decision directed value, and update the third tap coefficient to the second equalizer or the Send it to the detector, And the second area pilot data includes D2 (frame counter) to D51. The method of claim 1, The first equalizer to update the tap coefficient, Receiving the satellite broadcast signal formed of 64 blocks having Walsh codes and PN code sequence combinations used in a common pilot corresponding to 64 chips and shifted at chip unit intervals; Generating a recovery bit signal by multiplying the default tap coefficients corresponding to each of the 64 blocks; Updating a default tap coefficient to a first tap coefficient using a first error value corresponding to a difference between the first bit signal corresponding to the sum of the restored bit signals and the reference pilot signal; And And transmitting the first tap coefficients to the second equalizer. The method of claim 1, The second equalizer to update the tap coefficient, Receiving the satellite broadcast signal formed of 64 blocks in which Walsh codes and PN code sequence combinations used in a common pilot corresponding to 64 chips are shifted at chip unit intervals; Restoring a channel compensated pilot signal by summing respective multiplication values calculated by multiplying the first tap coefficients corresponding to each of the 64 blocks; Generating the reconstructed pilot signal by multiplying the channel compensated pilot signal by a spread code; Updating the first tap coefficient to a second tap coefficient using a second error value corresponding to the difference between the restored pilot signal and the reference pilot signal; And And transmitting said second tap coefficient to a detector. In the chip equalizer of the satellite broadcast receiver for recovering the broadcast data signal corresponding to the selected channel from the received satellite broadcast signal, A first bit signal is calculated using first region pilot data included in the satellite broadcast signal received through a tuner, and pilot information previously recognized corresponding to the first bit signal and the first region pilot data is used. A first equalizer for updating the tap coefficient by using a first error value corresponding to the difference of the reference pilot signal calculated by the first pilot data, wherein the first region pilot data are a pilot symbol (PS) and a unique word (D1). ; After generating the reconstructed pilot signal by using the tap coefficient updated by the first equalizer and the satellite broadcast signal received through the tuner after a preset delay time has elapsed, the reconstructed pilot signal and the first region pilot data are generated. A second equalizer which re-updates the updated tap coefficients using a second error value corresponding to a difference of a reference pilot signal calculated using pilot data previously recognized in correspondence with the corresponding pilot data; And Restoring broadcast data using the tap coefficient updated by the second equalizer and the satellite broadcast signal received through the tuner after a preset double delay time, and transmitting the restored broadcast data to a broadcast channel decoding unit. Including a detector, Any one of the first equalizer and the second equalizer calculates a second bit signal using second area pilot data included in the satellite broadcast signal, and determines the second bit signal and the second bit signal. update the tap coefficients again using a third error value corresponding to the difference of the decision directed value, and then transmit the updated tap coefficients to the second equalizer or the detector; And the second area pilot data includes D2 (frame counter) to D51. The method of claim 8, At least one of the first equalizer and the second equalizer may include: a chip equalizer of the satellite broadcast receiver for updating the step size for updating the tap coefficient by using the following equation;

here,

Is the updated step size,

Is the previous step size,

Is

Constant variable with any value of

Is

Constant variable with any value of

Represents the estimated error power. The method of claim 9, At least one of the first equalizing unit and the second equalizing unit uses the maximum step size when the step size updated by the above equation is equal to or greater than a preset maximum step size, and the updated step size is the minimum set in advance. The chip equalizer of the satellite broadcasting receiver using the minimum step size when the step size is smaller than the step size. The method of claim 9, The estimated error power of the chip equalizer of the satellite broadcasting receiver calculated by the following equation;

here,

Is

A weighted variable with any value of,

Is the average of the error values entered in the previous steps,

Is a currently calculated error value and is the first error value or the second error value. In the tap coefficient updating method of updating the tap coefficient of the chip equalizer, Sequentially storing the input error values; Calculating an average error value by giving a weight corresponding to immediately preceding error values except for the last error value inputted; Calculating an estimated error power by giving a weight corresponding to each of the average error value and the last error value; Calculating an update step size by giving a weight corresponding to each of the estimated error power and the current step size; And calculating an update tap coefficient using the update step size and the current tap coefficient. The method of claim 12, The update step size is a tap coefficient updating method of the chip equalizer calculated using the following equation;

here,

Is the update step size,

Is the current step size,

Is

Constant variable with any value of

Is

Constant variable with any value of

Denotes the estimated error power. The method of claim 13, The maximum step size is used when the update step size calculated by the above formula is equal to or larger than the preset maximum step size, and when the calculated update step size is less than or equal to the preset minimum step size, the minimum step size is used. And the calculated update step size is used when the calculated update step size is less than the maximum step size and more than the minimum step size.

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