KR19990066518A - Mode conversion control device of adaptive equalizer - Google Patents

Abstract

The present invention relates to an adaptive equalizer, and to provide a mode conversion control apparatus for controlling the conversion of the decision unit and the step size coefficient value in consideration of convergence of the equalizer. The apparatus according to the present invention comprises: a first calculating unit for obtaining power of a symbol value output from the determining unit; A second arithmetic unit for obtaining the power of the difference (error value) between the symbol value output from the determination unit and the finite shock response filtered signal, and the error power scaled by multiplying the power of the error value output from the second arithmetic unit by a predetermined scale factor; And a comparator for comparing the signal output from the first operation unit with the signal output from the multiplier to output a signal for controlling the generation of the operation mode and the step size coefficient of the decision unit. Therefore, the equalizer can be adaptively applied to a signal with high interference or a signal with little interference, thereby providing an equalizer with improved convergence capability.

Description

Mode conversion control device of adaptive equalizer

The present invention relates to a mode conversion control apparatus for an adaptive equalizer, and more particularly, to a mode conversion apparatus for an adaptive equalizer for converting a determination mode and a step size coefficient generation mode of an adaptive equalizer in consideration of equalizer convergence.

In communication systems, the biggest obstacle to reliable communication is the interference between symbols. Accordingly, an equalizer is provided at a receiving end of a communication system to remove interference between symbols and correctly recover a received signal. The adaptive equalizer is a kind of such equalizer. The adaptive equalizer removes interference or noise between symbols by obtaining an inverse function of a channel while adaptively processing a reference signal and an equalizer output.

FIG. 1 is a block diagram of a conventional adaptive equalizer using a nonlinear finite impulse response (FIR) filter, and linear coupling with past values through an FIR filter 101 when an input signal to equalize is applied. Output the generated value. The output value is transmitted to the decision device 102. The determination unit 102 detects and outputs the symbol closest to the applied signal. The output signal is output as an equalized output signal and is also transmitted to the subtractor 103. The subtractor 103 detects the difference between the signal before being applied to the determination unit 102 and the signal output from the determination unit 102 as an error value e. The detected error value is sent to multiplier 105.

The multiplier 105 multiplies the α, which is the step size coefficient of the equalizer provided from the step size coefficient generation unit 104, and the error value e transmitted from the subtractor 103, and transmits the result to the coefficient updater 106. The coefficient updater 106 generates a new equalizer coefficient by calculating a value [alpha] xe multiplied by the error value transmitted from the multiplier 105 and the output step size information and the previous equalizer coefficient value. At this time, the operation used is performed by subtracting the signal transmitted from the multiplier 105 from the previous equalizer count value. The FIR filter 101 then performs FIR filtering on the input signal using the new equalizer coefficients provided from the coefficient updater 106.

In performing the adaptive equalization as described above, the decision unit 102 operates in a quadrature phase shift keying (QPSK) mode initially, and then a quadrature amplitude modulation mode (QAM) mode is applied by a mode conversion control signal applied after a specific time elapses. Is converted to. At this time, the specific time is a time set in consideration of the QAM mode to be converted. However, when an unexpected signal with a lot of interference is received, the operation mode of the decision unit 102 is converted to the QAM mode and the equalizer diverges before being equalized to an appropriate level. In order to prevent the divergence phenomenon, delaying the mode conversion time of the decision unit 102 causes a long convergence time even when receiving a signal with little interference, resulting in a relatively low convergence capability of the equalizer.

In addition, the step size coefficient generator 104 also generates a large value of the step size coefficient in the early stage so as to achieve rapid convergence, but as a mode conversion control signal applied after a specific time has elapsed, as in the determination unit 102. A small step size coefficient is generated to reduce the error of the result of the equalizer. However, the mode conversion is also performed after a specific time has elapsed. Therefore, as described above, when the degree of interference of the input signal is severe (that is, some input signals have a lot of interference, and some input signals have little interference). It is a factor that lowers the convergence ability of the equalizer.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned shortcomings, and provides a mode conversion control apparatus of an adaptive equalizer that controls conversion of a determination mode and a step size coefficient generation mode in consideration of convergence of an equalizer in an adaptive equalizer. Its purpose is to.

In order to achieve the above object, a mode conversion control apparatus of an adaptive equalizer according to the present invention includes a decision unit for determining a symbol value of a finite shock response filtered signal while the QPSK mode and the QAM mode are selectively operated according to the degree of convergence. A subtractor for detecting an error value by subtracting a signal value from the impact response filtered signal and the determination unit, and multiplying a predetermined step size coefficient and an error value to provide an update coefficient for finite impact response filtering. An adaptive equalizer, comprising: a first multiplier, comprising: a first arithmetic unit for performing a predetermined arithmetic operation on a symbol value to obtain power of a symbol value output from the deciding unit; A second calculator configured to perform a predetermined operation on the error value in order to convert the error value output from the subtractor to a level comparable with the signal output from the first calculator; A second multiplier for multiplying a signal output from the second calculator by a predetermined scale factor to obtain a scaled error power; By comparing the power of the symbol value output from the first operation unit with the scaled error power output from the second multiplier, if the scaled error power is greater than the signal power, the operation mode of the determination unit is set to the QPSK mode and controlled. If the scaled error power is not greater than the power of the signal, the determining unit includes a comparator for outputting a signal for controlling to operate in the QAM mode.

1 is a block diagram of a conventional adaptive equalizer,

2 is a block diagram of an adaptive equalizer having a mode conversion control device implemented according to an embodiment of the present invention.

3 is a block diagram of an adaptive equalizer having a mode conversion control device implemented in another embodiment according to the present invention.

<Description of the symbols for the main parts of the drawings>

101: finite impact response (FIR) filter 102: Decision Device

103: subtractor 104: step size coefficient generator

105, 203: Multiplier 106: Coefficient updater

200: mode conversion controller 201: first square root calculation unit

202: second square root calculator 204: comparator

301: first absolute value calculator 302: second absolute value calculator

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 is a block diagram of an adaptive equalizer having a mode conversion control device implemented according to an embodiment of the present invention. The same finite shock response (hereinafter, referred to as FIR) filter 101 as shown in FIG. 1 is determined. The signal output from the unit 102, the subtractor 103, the step size coefficient generator 104, the multiplier 105, the coefficient updater 106, and the determiner 102 and the error value output from the subtractor 103 It is composed of a mode conversion control device 200 for controlling the mode conversion of the determination unit 102 and the step size coefficient generation unit 104 by using a.

The apparatus according to the present invention thus configured is operated as follows.

First, at the beginning of the operation, the decision unit 102 is set to the QPSK mode to increase the accuracy of the determination as shown in Fig. 1, and the step size coefficient generation unit 104 is set such that a large value of? Is provided. When the input signal to be equalized in the set state is applied, it is applied to the FIR filter 101 and transmits the filtered signal to the determination unit 102 as shown in FIG. 1. At this time, the initial equalizer coefficient set in the FIR filter 101 is '1' only for the main tap, and '0' for the rest.

The determination unit 102 operates in the QPSK mode and outputs a close symbol value. The output symbol value is transmitted to the subtractor 103 and the mode conversion control apparatus 200, respectively. The subtractor 103 detects the difference between the signal output from the FIR filter 101 and the signal output from the determination unit 102 as shown in FIG. 1, and transmits the difference to the multiplier 105 and the mode conversion controller 200, respectively. do.

The mode conversion controller 200 includes a first square root calculator 201, a second square root calculator 202, a multiplier 203, and a comparator 204 to determine the decision unit 102 and the convergence state of the equalizer. The mode conversion timing of the step size coefficient generator 104 is controlled.

That is, when the corresponding symbol value is transmitted from the determination unit 102, the square operation is performed through the first square root calculator 201 to obtain a signal power of the corresponding signal. The power of the obtained signal is transmitted as one input signal of the comparator 204. The error signal output from the subtractor 103 is applied to the second square root calculator 202. The second square root calculator 202 performs a square arithmetic operation on the applied error signal so that the error signal has a level of a signal that can be compared with a signal output from the first square root calculator 201. The error signal processed by the square root operation is transmitted to the multiplier 203. The multiplier 203 multiplies the square root operation error signal by the applied scale factor β to obtain a scaled error power. The obtained scaled error power is transmitted to another input signal of the comparator 204. At this time, the scale factor β is set according to the mode of the QAM signal (Consetellation), the structure of the receiver, and the like.

The comparator 204 compares the power of the symbol value transmitted from the first square root calculating unit 201 with the scaled error power transmitted from the multiplier 203 and determines the scaler 102 if the scaled error power is greater than the power of the symbol value. And the step size coefficient generator 104 output a mode conversion control signal so that the initial operation mode is maintained. However, as a result of the comparison, if the scaled error power is not greater than the power of the symbol value, the operation mode of the determination unit 102 is a QAM mode, and the step size coefficient generated from the step size coefficient generation unit 104 is a mode such that a small value is generated. Output the conversion control signal.

Accordingly, the determination unit 102 is converted to the QAM mode and operated, and the step size coefficient generator 104 generates a small step size coefficient to delay the convergence of the equalizer earlier than the initial stage, and operates to reduce the resultant error.

3 is a block diagram of an adaptive equalizer having a mode conversion controller according to another embodiment of the present invention, wherein the first square root calculator 201 and the second square root calculator 202 shown in FIG. This is an example implemented by the first absolute value calculator 301 and the second absolute value calculator 302.

That is, the mode conversion control apparatus 300 shown in FIG. 3 is transmitted to the first absolute value calculator 301 when the symbol value output from the determiner 102 is applied. The first absolute value calculator 301 calculates the power of the symbol value by calculating an absolute value of the applied symbol value. The power of the obtained symbol value is transmitted as one input signal of the comparator 304. On the other hand, the error value output from the subtractor 103 is applied to the second absolute value calculator 302. The second absolute value calculating section 302 is applied to the error value applied so that the signal output from the first absolute value calculating section 301 and the error value output from the subtractor 103 can be compared with the second square root calculating section 202 described above. Calculate the absolute value of. The calculation result is transmitted to the multiplier 303.

The multiplier 303 multiplies the signal output from the second absolute value calculating section 302 with the step size coefficient and transmits it as another input signal of the comparator 304. The comparator 304 also controls the operation mode of the determination unit 102 and the step size coefficient generation unit 104 by comparing the two signals input as shown in FIG.

As can be seen in the above-described two embodiments, the square root calculation units 201 and 202 in the mode conversion control apparatus 200 and the absolute value calculation units in the mode conversion control apparatus 300 do not depart from the spirit of the present invention. 301 and 302 may be implemented by other computing means.

As described above, the present invention provides an apparatus for controlling the point of change of the operation mode and the step size coefficient generation mode of the decision unit in consideration of convergence of the equalizer, so that when a signal with less interference is applied, it converges compared with the conventional method. If the time is short and a signal with a lot of interference is applied, the convergence of the equalizer can be more guaranteed, thereby improving the convergence capability of the adaptive equalizer.

Claims (3)

Determination unit for determining the symbol value of the finite shock response filtered signal while the QPSK mode and QAM mode is selectively operated according to the degree of convergence, the error value by subtracting the finite shock response filtered signal and the symbol value output from the determination unit An adaptive equalizer configured to include a subtractor for detecting a first multiplier for multiplying a predetermined step size coefficient and the error value to be used for updating the equalization coefficient for the finite shock response filtering, A first calculating unit which performs a predetermined calculation on the symbol value to obtain power of the symbol value output from the determining unit; A second operation unit which performs a predetermined operation on the error value to convert the error value output from the subtractor to a level comparable with the signal output from the first operation unit; A second multiplier for multiplying a signal output from the second calculator by a predetermined scale factor to obtain a scaled error power; When the scaled error power is greater than the power of the signal by comparing the power of the symbol value output from the first calculator with the scaled error power output from the second multiplier, the operation mode of the determination unit is the QPSK. An adaptive equalizer comprising a comparator configured to operate in a mode, and to output a signal for controlling the decision unit to be operated in the QAM mode when the scaled error power is not greater than the power of the signal. Mode conversion control device. The method of claim 1, wherein the comparator controls the predetermined step size coefficient to generate a predetermined large value when the scaled error power is greater than the power of the symbol value, and the scaled error power is increased. And a step size coefficient having a value smaller than the predetermined large value is generated when the symbol value is not larger than the power of the symbol value. The apparatus of claim 1, wherein the first operation unit and the second operation unit are configured to calculate a square root or an absolute value with respect to an input signal, respectively.