JP2000049665A - Receiver and sampling method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the deviation between the optimum timing of an equalizer and the sampling timing of an AD converter without increasing the arithmetic quantity of the equalizer. SOLUTION: A changeover switch 125 is controlled and switched with a control signal c2, an error signal outputted by a digital computing element 123 at the end of the former half of a training period is stored in a memory 126, and an error signal at the end of the training period is stored in a memory 127. A decision unit 129 decides which of the errors at the end of the former half of the training period and at the end of the training period is larger and controls a changeover switch 130. Consequently, when the error at the end of the former half of the training period is larger, a sampling clock is outputted to an AD converter 101 as it is and when not, the sampling clock is delayed by a 1/2 sampling cycle through a delay unit 131 and outputted to the AD converter 101.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a receiving device and a sampling method used in a wireless communication system.

[0002]

2. Description of the Related Art A receiving device mounted on a wireless communication device such as a portable telephone or a car telephone converts an analog signal into a digital signal by sampling the analog signal with an AD converter, and a digital signal waveform with an equalizer. To reduce the effect of inter-signal interference.

[0003] The configuration and operation of a conventional receiving apparatus will be described below with reference to a block diagram shown in FIG. Note that a decision feedback equalizer is used as an equalizer of the receiving device.

An analog signal received by the receiving apparatus shown in FIG. 10 is converted into a digital signal by a sampling process based on a sampling clock in an AD converter 1 and output to an equalizer 2. The digital signal input to the equalizer 2 is delayed by one sampling period by passing through the delay unit 11, the delay unit 12, and the delay unit 13, respectively.

The digital signal is multiplied by a tap coefficient signal k1 in a digital multiplier 14. Similarly, the input signal delayed by one sampling period is multiplied by the tap coefficient signal k2 in the digital multiplier 15, and
The input signal delayed by the sampling period is multiplied by the tap coefficient signal k3 in the digital multiplier 16, and the input signal delayed by 3 sampling periods is converted by the digital multiplier 17
Is multiplied by the tap coefficient signal k4.

The signals multiplied by the tap coefficient signal are added by a digital adder 18, and the added signal (hereinafter referred to as “addition signal”) is output to a decision unit 19 and a digital subtractor 23. . Then, in the decision unit 19,
The signal transmitted from the transmitter is estimated based on the power value of the addition signal. The estimated signal (hereinafter, referred to as an “estimated signal”) is output to another device, passed through a delay unit 20 and delayed by one sampling period, and then, in a digital multiplier 21, a tap coefficient signal. The signal is multiplied by k5 and input to the digital adder 18.

Here, in general, a transmitter for mobile communication comprises:
A known training signal sequence is inserted before the message of the transmission signal. On the other hand, the equalizer in the receiver stores the same training reference signal sequence as the training signal sequence to adapt to the channel characteristics, and uses the training reference signal sequence while receiving the training signal sequence. To perform equalization processing. Hereinafter, a period during which a training signal sequence is received is referred to as a training period, and a period during which a message is received is referred to as a message period.

By controlling the changeover switch 22 with the control signal c1, the reference signal for training is input to the digital subtractor 23 during the training period, and the estimated signal is input to the digital subtractor 23 during the message period. Is done.

The digital subtracter 23 subtracts the training reference signal or the estimated signal from the added signal to indicate a decision error (hereinafter referred to as an "error signal").
Is calculated and output to the coefficient updating unit 24.

[0010] Then, the coefficient updating unit 24 performs LMS (Le
ast Mean Square (RLS) algorithm and RLS (Recursive L
The tap coefficient signal is calculated from the input signal and the error signal using a predetermined algorithm such as an east square algorithm, and the updated tap coefficient signals k1 to k5 are output to the respective multipliers.

[0011]

Here, if the sampling timing of the AD converter deviates greatly from the optimum timing in the equalizer, the error rate characteristic deteriorates. As a countermeasure, a method of correcting the sampling timing shift by shortening the sampling period to twice the symbol rate can be considered.

However, when the sampling period is shortened,
Since the amount of calculation in the equalizer increases and the size of the apparatus increases, it is not practical to adopt the above method for a communication apparatus of digital mobile communication.

SUMMARY OF THE INVENTION The present invention has been made in view of the above point, and it is possible to reduce the difference between the optimal timing in the equalizer and the sampling timing in the AD converter without increasing the amount of calculation in the equalizer, and to improve the It is an object of the present invention to provide a receiving apparatus and a sampling method that can obtain an excellent error rate characteristic.

[0014]

Means for Solving the Problems In order to solve the above problems, the present invention has taken the following means. The invention relating to the receiving apparatus according to claim 1 is an equalizing means for performing an equalizing process using an error signal obtained by subtracting a received signal from an estimated transmission path characteristic, and a sampling timing and an equalizing process based on the error signal. Determining means for determining a deviation from the optimum timing, a delay means for controlling a delay amount of a sampling clock based on the determination result of the determining means, and performing AD conversion using the sampling clock having a controlled delay amount. A configuration including AD conversion means is adopted.

According to a fourteenth aspect of the present invention, an equalization process is performed using an error signal obtained by subtracting a received signal from an estimated transmission path characteristic, and a sampling timing and an equalization process are performed based on the error signal. A method of determining a deviation from the optimal timing, controlling the delay amount of the sampling clock based on the determination result, and performing AD conversion using the sampling clock whose delay amount is controlled is adopted.

With these configurations, the timing of the sampling clock in the AD conversion can be adjusted, so that the deviation between the optimum timing in the equalizer and the sampling timing in the AD converter can be reduced without increasing the amount of calculation in the equalizer. However, it is possible to reduce the deterioration of the error rate characteristics.

According to a second aspect of the present invention, in the receiving apparatus according to the first aspect, the delay means reduces the sampling clock by サ ン プ リ ン グ sampling when it is determined that the sampling timing deviates from the optimum timing of the equalization processing. A configuration for delaying the period is adopted.

According to a third aspect of the present invention, in the receiving apparatus according to the first or second aspect, the determining means determines whether the error signal at the end of the training period is larger than the error signal at the end of the first half of the training period. A configuration is adopted in which it is determined that the timing is shifted from the optimal timing of the equalization processing.

According to a fifteenth aspect of the present invention, in the sampling method according to the fourteenth aspect, a method of delaying the sampling clock by a half sampling period when it is determined that the sampling timing is deviated from the optimum timing of the equalization processing. Take.

According to a sixteenth aspect of the present invention, in the sampling method according to the fourteenth or fifteenth aspect, if the error signal at the end of the training period is larger than the error signal at the end of the first half of the training period, the sampling timing is equalized. A method is used in which it is determined that there is a deviation from the optimal timing of the processing.

According to these configurations, the difference between the sampling timing and the optimal timing of the equalization processing is at most 1
The sampling rate can be reduced to ４ sampling period, and the deterioration of the error rate characteristic can be reduced.

According to a fourth aspect of the present invention, there is provided the receiving apparatus according to the first or second aspect, further comprising integrating means for integrating the error signal, wherein the determining means determines whether the integrated value of the error signal in the latter half of the training period is equal to the training value. If the error signal is larger than the integrated value of the error signal in the first half of the period, it is determined that the sampling timing is shifted from the optimal timing of the equalization processing.

According to a seventeenth aspect of the present invention, in the sampling method according to the fourteenth or fifteenth aspect, if the integrated value of the error signal in the second half of the training period is larger than the integrated value of the error signal in the first half of the training period, the sampling timing A method of determining that the timing is shifted from the optimal timing of the equalization processing is adopted.

With these configurations, the sampling timing can be controlled based on the integrated value of the error signal, so that the error rate characteristics can be further improved.

According to a fifth aspect of the present invention, in the receiving apparatus according to the first or second aspect, when the error signal in the message period is larger than the first threshold value, the sampling timing is set to an optimum timing of the equalization processing. Is determined to be shifted from.

The invention according to claim 18 is the sampling method according to claim 14 or 15, wherein when the error signal in the message period is larger than the first threshold, the sampling timing is shifted with respect to the optimal timing of the equalization processing. A method is used to determine that

With these configurations, the sampling timing can be controlled by one control signal, so that the device can be simplified. The control of the sampling timing by these configurations is effective when a sufficient training signal period cannot be secured.

According to a sixth aspect of the present invention, there is provided the receiving apparatus according to the first or second aspect, further comprising integrating means for integrating the error signal, wherein the determining means determines that the integrated value of the error signal during the training period is equal to the first threshold value. If it is larger, a configuration is adopted in which it is determined that the sampling timing is shifted from the optimal timing of the equalization processing.

According to a nineteenth aspect of the present invention, in the sampling method according to the fourteenth or fifteenth aspect, when the integrated value of the error signal during the training period is larger than the first threshold value, the sampling timing is set to the optimal timing of the equalization processing. A method of determining that the position is shifted is adopted.

With these configurations, since the sampling timing can be controlled based on the integrated value of the error signal, the error rate characteristics can be further improved.

According to a seventh aspect of the present invention, in the receiving apparatus according to the first or second aspect, there is provided a counter for adding the number of times the error signal in the message period has exceeded the first threshold value, and the determining means comprises: When the number of times the counter has added is larger than the second threshold, a configuration is adopted in which it is determined that the sampling timing is shifted from the optimal timing of the equalization processing.

According to a twentieth aspect of the present invention, in the sampling method according to the fourteenth or fifteenth aspect, the number of times that the error signal exceeds the first threshold during the message period is added, and the added value is larger than the second threshold. In this case, a method of determining that the sampling timing is shifted from the optimal timing of the equalization processing is adopted.

According to these configurations, the sampling timing can be controlled based on the added value of the number of times the error signal exceeds the threshold value, so that the error rate characteristic can be further improved.

According to an eighth aspect of the present invention, in the receiving apparatus according to any one of the fifth to seventh aspects, the judging means comprises a plurality of thresholds depending on whether the error signal in the message period exceeds a third threshold. Is adopted to select the first threshold value from.

According to a ninth aspect of the present invention, in the receiver according to any one of the fifth to seventh aspects, the determining means uses a previous error signal as a first threshold value.

According to a twenty-first aspect of the present invention, in the sampling method according to any one of the eighteenth to twentieth aspects, a plurality of threshold values are set to first threshold values depending on whether an error signal in a message period exceeds a third threshold value. Take the method of selecting.

According to a twenty-second aspect of the present invention, in the sampling method according to any one of the eighteenth to twentieth aspects, a method is employed in which a previous error signal is used as a first threshold value.

With these configurations, the threshold value, which is a control reference for the sampling timing, can be switched finely, so that the error rate characteristics can be further improved.

According to a tenth aspect of the present invention, in the receiving apparatus according to any one of the third to ninth aspects, the determining means converts the error signal at the end of the first half of the training period from the error signal at the end of the training period. The absolute value after subtraction is the fourth
It is determined whether or not the absolute value is greater than the threshold value, and the delay means delays the sampling clock by １ ／ sampling period when the absolute value is determined to be greater than the fourth threshold value.

According to a twenty-third aspect of the present invention, in the sampling method according to any one of the sixteenth to twenty-second aspects, the absolute value obtained by subtracting the error signal at the end of the first half of the training period from the error signal at the end of the training period. Is the fourth
Determining whether the absolute value is greater than a threshold value,
When it is determined that the sampling clock is larger than the threshold value, a method of delaying the sampling clock by 1/4 sampling period is adopted.

With these arrangements, the difference between the sampling timing and the optimum timing of the equalization processing is at most 1
/ 8 sampling period, and the deterioration of the error rate characteristic can be reduced.

According to an eleventh aspect of the present invention, there is provided a communication terminal including the receiving device according to any one of the first to ninth aspects and performing wireless communication.

According to a twelfth aspect of the invention relating to a base station apparatus, the receiving apparatus according to any one of the first to ninth aspects is mounted, and adopts a configuration for performing wireless communication.

According to a thirteenth aspect of the present invention, there is provided a wireless communication system in which the receiving device according to any one of the first to ninth aspects is mounted on at least one of a communication terminal device and a base station device that perform wireless communication. take.

[0045]

Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. In the following description, a decision feedback equalizer is used as an equalizer.

In the following description, an LMS algorithm is used as a coefficient updating algorithm. The update tap coefficient W (n) in the LMS algorithm is calculated based on the input signal X
(n), an error signal e (n), a correction coefficient u (0 <u <1), and a natural number n are obtained by the following equation (1).

W (n) = W (n−1) + uX (n) e (n) (1) Further, each control signal and each threshold in the following description are set in advance by a user or the like, and are shown in each drawing. Is output to the equalizer from the control unit that is not used.

(Embodiment 1) FIG.1 is a block diagram showing a configuration of a receiving apparatus according to Embodiment 1 of the present invention.

In the receiving apparatus shown in FIG. 1, an AD converter 101 performs sampling processing on a received analog signal based on a sampling clock and converts the analog signal into a digital signal. The equalizer 102 shapes the waveform of the digital signal output from the AD converter 101 to reduce the influence of inter-signal interference.

Hereinafter, the internal configuration of the equalizer 102 will be described. Delay device 111, delay device 112 and delay device 113
Delays the input signal by one sample period. The digital multiplier 114 multiplies the input signal by a tap coefficient signal k1. The digital multiplier 115 multiplies the input signal delayed by one sample period by the tap coefficient signal k2. The digital multiplier 116 multiplies the input signal delayed by two sample periods by the tap coefficient signal k3. Digital multiplier 117
Is obtained by adding a tap coefficient signal k to the input signal delayed by three sample periods.
Multiply by four.

The digital adder 118 adds a plurality of signals multiplied by each tap coefficient signal (hereinafter, referred to as a signal).
"Addition signal"). The determiner 119 estimates the signal transmitted from the transmitter based on the power value of the added signal or the like, and outputs an estimated signal (hereinafter, referred to as an “estimated signal”). The delay unit 120 delays the estimation signal by one sample period, and the digital multiplier 121 multiplies the estimation signal delayed by one sample period by the tap coefficient signal k5 and outputs the result to the adder 118.

The change-over switch 122 selects a training reference signal during a training period and an estimated signal during a message period according to the control signal c1,
The selected signal is output to the digital subtractor 123.

The digital subtractor 123 subtracts the training reference signal or the estimated signal from the added signal to calculate a signal representing a decision error (hereinafter referred to as “error signal”). Output.

The coefficient updating unit 124 receives the input signal, the error signal, and the correction coefficient, calculates tap coefficients by an LMS algorithm, and outputs tap coefficient signals k1 to k5 to the respective multipliers.

The switch 125 outputs an error signal at the end of the first half of the training period to the memory 126 and outputs an error signal at the end of the training period to the memory 127 according to the control signal c2. The memory 126 stores the error signal at the end of the first half of the training period.
7 stores the error signal at the end of the training period.

The digital subtractor 128 outputs a signal obtained by subtracting the error signal at the end of the training period from the error signal at the end of the first half of the training period (hereinafter, referred to as “error subtraction signal”) to the decision unit 129.

The determiner 129 determines, based on the error subtraction signal, the larger error between the end of the first half of the training period and the end of the training period. Then, the determiner 129 outputs a control signal based on the determination result (hereinafter, referred to as “determination control signal”) to the changeover switch 130.

The switch 130 outputs a sampling clock to the AD converter 101 in the first half of the training period and outputs a sampling clock to the delay unit 131 in the second half of the training period in response to the control signal c2 in the training period. Also, the changeover switch 130
Outputs a sampling clock to the AD converter 101 in the message period when the error at the end of the first half of the training period is smaller than the error at the end of the training period by the determination control signal, and otherwise outputs the sampling clock. Output to the delay unit 131.

The delay unit 131 delays the input sampling clock by サ ン プ リ ン グ sampling period, and outputs the result to the AD converter 101.

Next, sampling processing and equalization processing of the receiving apparatus according to the first embodiment will be described. The analog signal received by the receiving device is converted into a digital signal by an AD converter 101 by a sampling process based on a sampling clock, and output to an equalizer 102.

The digital signal input to the equalizer 102 is delayed by one sampling period by passing through the delay units 111, 112, and 113, respectively.

The digital signal is multiplied by a tap coefficient signal k 1 in a digital multiplier 114. Similarly, the input signal delayed by one sampling period is multiplied by the tap coefficient signal k2 in the digital multiplier 115,
The input signal delayed by two sampling periods is multiplied by a tap coefficient signal k3 in a digital multiplier 116, and the input signal delayed by three sampling periods is multiplied by a tap coefficient signal k4 in a digital multiplier 117.

Each signal multiplied by the tap coefficient signal is added by a digital adder 118, and the added signal is output to a decision unit 119 and a digital subtractor 123.

Then, the decision unit 119 estimates the signal transmitted from the transmitter based on the power value of the added signal, outputs the estimated signal to other devices, and sets the delay unit 120
, And is delayed by one sampling period, multiplied by the tap coefficient signal k5 in the digital multiplier 121, and output to the digital adder 118.

The changeover switch 12 is controlled by the control signal c1.
2 so that the training reference signal is supplied to the digital subtractor 123 during the training period.
Is output to the digital subtractor 123 during the message period. Then, the digital subtractor 123 subtracts the training reference signal or the estimation signal from the added signal to calculate an error signal, and outputs the error signal to the coefficient updating unit 124 and the switch 125.

Then, in the coefficient updating section 124, the tap coefficient is calculated by the LMS algorithm using the digital signal, the error signal and the correction coefficient, and the updated tap coefficient signals k1 to k5 are output to the respective multipliers. .

The changeover switch 12 is controlled by the control signal c2.
5, the error signal is stored in the memory 126 at the end of the first half of the training period, and is stored in the memory 127 at the end of the training period.

Then, the digital subtracter 128 subtracts the error signal at the end of the training period from the error signal at the end of the first half of the training period, and outputs the signal to the decision unit 129. It is determined whether the error at the end of the first half of the training period or the error at the end of the training period is larger. Then, a determination control signal based on the determination result is output to the changeover switch 130.

The sampling clock is output to the AD converter 101 in the first half of the training period by controlling the changeover switch 130 with the control signal c2 in the training period, and is output to the delay unit 131 in the second half of the training period. . Also, the sampling clock is
In the message period, by controlling the changeover switch 130 with the determination control signal, the error at the end of the first half of the training period is output to the AD converter 101 when the error at the end of the training period is smaller than the error at the end of the training period. Is output to the delay unit 131.

The sampling clock input to the delay unit 131 is output to the AD converter 101 after being delayed by a 1/2 sampling period.

As described above, AD during the message period
By controlling the sampling timing of the converter 101 based on the error signal of the equalizer, it is possible to reduce the deviation of the sampling timing, which was conventionally １ ／ sampling period, to １ ／ sampling period. Good error rate characteristics can be obtained.

(Embodiment 2) FIG. 2 is a block diagram showing a configuration of a receiving apparatus according to Embodiment 2. The receiving device shown in FIG. 2 has a configuration in which an integrator 201 is added to the receiving device of FIG. Note that, in the receiving apparatus of FIG.
1 are denoted by the same reference numerals as in FIG. 1 and description thereof is omitted.

The digital subtractor 123 outputs the error signal to the coefficient updating section 124 and the integrator 201. Integrator 2
01 integrates the input error signal and outputs the integrated value to the changeover switch 125.

The changeover switch 125 outputs the integrated value of the error signal in the first half of the training period to the memory 126 and the integrated value of the error signal in the second half of the training period to the memory 127 in response to the control signal c2. The memory 126 stores the integrated value of the error signal in the first half of the training period, and the memory 127 stores the error signal of the integrated value in the second half of the training period.

The digital subtracter 128 outputs to the decision unit 129 a signal obtained by subtracting the integrated value of the error signal in the latter half of the training period from the integrated value of the error signal in the first half of the training period.

The determiner 129 determines whether the integrated value of the error signal in the first half of the training period is greater than the integrated value of the error in the second half of the training period, and outputs a determination control signal to the changeover switch 130.

As described above, by controlling the sampling timing of the AD converter 101 based on the integrated value of the error signal, the error rate characteristic can be further improved as compared with the receiving apparatus of the first embodiment.

(Embodiment 3) FIG.3 is a block diagram showing a configuration of a receiving apparatus according to Embodiment 3. The receiving apparatus shown in FIG. 3 is different from the receiving apparatus shown in FIG.
, A digital subtractor 302, a decision unit 303, a changeover switch 304, and a delay unit 305. Note that, in the receiving device of FIG. 3, portions common to those of the receiving device illustrated in FIG. 1 are denoted by the same reference numerals as in FIG. 1 and description thereof is omitted.

The digital subtractor 128 outputs the error subtraction signal to the decision unit 129 and the absolute value detector 301.

The changeover switch 130 outputs the sampling clock to the AD converter 101 in the first half of the training period and outputs the sampling clock to the changeover switch 304 in the second half of the training period in accordance with the control signal c2 in the training period. Changeover switch 1
30 outputs a sampling clock to the AD converter 101 when the error at the end of the first half of the training period is smaller than the error at the end of the training period according to the determination control signal in the message period; Is output to the changeover switch 304.

The absolute value detector 301 outputs the absolute value of the error subtraction signal to the digital subtractor 302. The digital subtractor 302 outputs a value obtained by subtracting the threshold value t1 from the absolute value of the error subtraction signal to the determiner 303.

The decision unit 303 decides whether or not the absolute value of the error subtraction signal is larger than the threshold value t1, and outputs a control signal based on the decision result to the changeover switch 304. The changeover switch 304 outputs the sampling clock to the delay unit 131 when the absolute value of the error subtraction signal is larger than the threshold value t1 by the control signal input from the determination unit 303, and outputs the sampling clock to the delay unit 305 otherwise. Output.

The delay unit 305 delays the input sampling clock by １ ／ sampling period, and outputs it to the AD converter 101.

As described above, by controlling the delay amount of the sampling timing based on the absolute value of the error signal, the error rate characteristic can be further improved as compared with the receiving apparatus of the first embodiment.

(Embodiment 4) FIG. 4 is a block diagram showing a configuration of a receiving apparatus according to Embodiment 4. The receiver shown in FIG. 4 is different from the receiver of FIG. 1 in that a changeover switch 125, a memory 126, and a memory 127 are used instead of the switch 125.
A configuration in which a connection switch 401 is added is adopted. FIG.
In this receiver, the same reference numerals as in FIG. 1 denote the same parts as in the receiver shown in FIG. 1, and a description thereof will be omitted.

The digital subtractor 123 outputs the error signal to the coefficient updating section 124 and the digital subtractor 128. The digital subtractor 128 calculates a threshold value t2 from the error signal.
Is output to the decision unit 129.

The decision unit 129 decides whether or not the error is larger than the threshold value t2, and outputs a decision control signal to the connection switch 40.
Output to 1. The connection switch 401 is connected during the message period by the control signal c1, and outputs a determination control signal to the changeover switch 130.

The changeover switch 130 does not control the changeover of the changeover switch 130 during the training period. The switch 130 outputs the sampling clock to the AD converter 101 when the error signal is smaller than the threshold value t2 during the message period, and outputs the sampling clock to the delay unit 131 otherwise.

Thus, the delay amount of the sampling timing can be controlled by one control signal, so that the device can be simplified. The receiving apparatus shown in FIG. 4 is effective when a training signal period cannot be sufficiently secured.

(Embodiment 5) FIG.5 is a block diagram showing a configuration of a receiving apparatus according to Embodiment 5. The receiver shown in FIG. 5 employs a configuration in which an integrator 501 is added to the receiver shown in FIG. Note that, in the receiving apparatus of FIG.
4 are denoted by the same reference numerals as in FIG. 4 and description thereof is omitted.

Digital subtracter 123 outputs the error signal to coefficient updating section 124 and integrator 501. Integrator 5
01 integrates the error signal and outputs the integrated value to the digital subtractor 128. The digital subtractor 128 subtracts the signal obtained by subtracting the threshold value t2 from the integrated value of the error signal to determiner 1
29.

As described above, by controlling the sampling timing of AD converter 101 based on the integrated value of the error signal, it is possible to further improve the error rate characteristic as compared with the receiving apparatus of the fourth embodiment.

(Embodiment 6) FIG.6 is a block diagram showing a configuration of a receiving apparatus according to Embodiment 6. The receiving apparatus shown in FIG. 6 differs from the receiving apparatus shown in FIG.
, A digital subtractor 602, a decision unit 603, a changeover switch 604, and a delay unit 605. Note that, in the receiving device of FIG. 6, portions that are the same as those of the receiving device shown in FIG.

The digital subtracter 128 outputs a signal obtained by subtracting the threshold value t2 from the error signal to the decision unit 129 and the absolute value detector 601.

The absolute value detector 601 subtracts the absolute value of the signal obtained by subtracting the threshold value t2 from the error signal into a digital subtractor 602.
Output to The digital subtractor 602 outputs a value obtained by subtracting the threshold value t3 from the absolute value of the signal obtained by subtracting the threshold value t2 from the error signal to the determiner 603.

The decision unit 603 decides whether or not the absolute value of the signal obtained by subtracting the threshold value t2 from the error signal is larger than the threshold value t3, and switches the control signal based on the decision result to the changeover switch 604.
Output to

The changeover switch 604 outputs a sampling clock to the delay unit 131 when the absolute value of the signal obtained by subtracting the threshold value t2 from the error signal is larger than the threshold value t3 according to the control signal input from the decision unit 603. In this case, the sampling clock is output to the delay unit 305.

The delay unit 605 delays the input sampling clock by １ ／ sampling period and outputs the result to the AD converter 101.

As described above, by controlling the delay amount of the sampling timing based on the value of the error signal, the error rate characteristic can be further improved as compared with the receiving apparatus of the fourth embodiment.

(Seventh Embodiment) FIG. 7 is a block diagram showing a configuration of a receiving apparatus according to the seventh embodiment. The receiving apparatus shown in FIG. 7 is different from the receiving apparatus shown in FIG.
A configuration in which a digital subtractor 702 and a decision unit 703 are added is adopted. Note that, in the receiving device of FIG. 7, the same components as those of the receiving device shown in FIG. 4 are denoted by the same reference numerals as in FIG.

The connection switch 401 is connected during the message period by the control signal c 1, and outputs a judgment control signal to the counter 701. The counter 701 counts the number of times that the error signal is determined to be larger than the threshold value t2 by the determiner 129 (hereinafter, referred to as “number of determinations”) based on the determination control signal, and outputs the number of determinations to the digital subtractor 702. The digital subtractor 702 calculates the threshold value t4
Is output to the decision unit 703.

The determiner 703 determines whether or not the number of determinations is greater than a threshold value t4, and outputs a control signal based on the determination result to the switch 704. The changeover switch 130 is
When the number of determinations is smaller than the threshold value t4 by the control signal input from the determination unit 703, the sampling clock is set to AD.
The sampling clock is output to the converter 101, and otherwise, the sampling clock is output to the delay unit 131.

As described above, by controlling the sampling timing of AD converter 101 based on the number of times that the error signal is determined to be greater than threshold value t2, the error rate characteristic is further improved as compared with the receiving apparatus of the fourth embodiment. can do.

(Eighth Embodiment) FIG. 8 is a block diagram showing a configuration of a receiving apparatus according to an eighth embodiment. The receiving apparatus shown in FIG. 8 is different from the receiving apparatus shown in FIG.
01, a determiner 802, and a changeover switch 803 are added. Note that, in the receiving apparatus of FIG.
4 are denoted by the same reference numerals as in FIG. 4 and description thereof is omitted.

The digital subtractor 123 outputs the error signal to the coefficient updating section 124, the digital subtractor 128, and the digital subtractor 801. Digital subtractor 801
Is a signal obtained by subtracting the threshold value t5 from the error signal.
Output to 2. The determiner 802 determines whether the error is greater than the threshold value t5, and outputs a determination control signal to the changeover switch 803.

The changeover switch 803 outputs the threshold value t2-1 to the digital subtractor 128 when the error signal is larger than the threshold value t5 by the control signal input from the decision unit 802, and sets the threshold value t2-2 otherwise. Digital subtractor 1
28.

The digital subtractor 128 subtracts the threshold value t2-1 or the threshold value t2-2 from the error signal to determine
9 is output.

As described above, by variably controlling the threshold value used for controlling the sampling timing of AD converter 101, the error rate characteristic can be further improved as compared with the receiving apparatus of the fourth embodiment.

(Embodiment 9) FIG.9 is a block diagram showing a configuration of a receiving apparatus according to Embodiment 9. The receiving apparatus shown in FIG. 9 is different from the receiving apparatus shown in FIG.
And a memory 902 are added. Note that FIG.
In this receiver, the same reference numerals as in FIG. 4 denote the same parts as in FIG. 4, and a description thereof will be omitted.

The digital subtractor 123 outputs the error signal to the coefficient updating unit 124, the digital subtractor 128, and the connection switch 901.

The connection switch 901 is connected when a judgment control signal is input, outputs an error signal to the memory 902 during connection, and is disconnected after one burst period has elapsed after connection.
The memory 902 temporarily stores the input error signal,
When a new error signal is input, the stored previous error signal is output to the digital subtractor 128.

The digital subtractor 128 outputs a signal obtained by subtracting the previous error signal from the error signal to the decision unit 129.

As described above, by using the previous error signal as the threshold used for controlling the sampling timing of AD converter 101, the error rate characteristic can be further improved as compared with the receiving apparatus of the fourth embodiment.

Although the above embodiments have been described using a decision feedback equalizer as an equalizer, the present invention is not limited to this, and uses a maximum likelihood sequence estimation type equalizer. Can obtain the same effect.

Further, in the present invention, it is possible to appropriately combine the above-described embodiments, for example, by increasing the number of correction coefficients input to the coefficient updating unit, changing the number of delay units and multipliers, and the like. It is also possible to construct a gasifier.

In each of the above embodiments, the LMS algorithm has been described as the coefficient updating algorithm of the equalizer. However, the present invention is not limited to this.
The same effect can be obtained by using another algorithm such as the LS algorithm. Further, in multiplying the correction coefficient, a bit shift circuit can be used instead of the multiplier.

[0117]

As described above, according to the receiver and the sampling method of the present invention, the timing of the sampling clock can be controlled, and the error rate characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a receiving apparatus according to Embodiment 1 of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a receiving apparatus according to Embodiment 2.

FIG. 3 is a block diagram showing a configuration of a receiving device according to a third embodiment.

FIG. 4 is a block diagram showing a configuration of a receiving apparatus according to Embodiment 4.

FIG. 5 is a block diagram showing a configuration of a receiving apparatus according to Embodiment 5.

FIG. 6 is a block diagram illustrating a configuration of a receiving device according to a sixth embodiment.

FIG. 7 is a block diagram showing a configuration of a receiving apparatus according to a seventh embodiment.

FIG. 8 is a block diagram showing a configuration of a receiving apparatus according to an eighth embodiment.

FIG. 9 is a block diagram showing a configuration of a receiving apparatus according to a ninth embodiment.

FIG. 10 is a block diagram showing a configuration of a conventional receiving apparatus.

[Explanation of symbols]

 Reference Signs List 101 AD converter 102 Equalizer 125 Changeover switch 126, 127 Memory 128 Digital subtractor 129 Judge 130 Changeover switch 131 Delay unit 201 Integrator 301 Absolute value detector 401 Connection switch 501 Integrator 601 Absolute value detector 701 Counter 801 Digital subtractor 802 Judgment device 803 Changeover switch 901 Connection switch 902 Memory

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J064 AA01 BC06 BC08 BC14 BC24 BD02 5K046 AA05 EE02 EE06 EE47 EF02 EF13 EF46 PP09

Claims (23)

[Claims] An equalizer for performing an equalization process using an error signal obtained by subtracting a received signal from an estimated transmission path characteristic, and a shift between a sampling timing and an optimum timing of the equalization process based on the error signal. A determination unit; a delay unit configured to control a delay amount of the sampling clock based on a determination result of the determination unit; and an AD conversion unit configured to perform an AD conversion using the sampling clock whose delay amount is controlled. A receiving device, characterized in that: 2. The receiving apparatus according to claim 1, wherein the delay means delays the sampling clock by a half sampling period when it is determined that the sampling timing is different from the optimum timing of the equalization processing. . 3. The determining means determines that the sampling timing is shifted from the optimal timing of the equalization processing when the error signal at the end of the training period is larger than the error signal at the end of the first half of the training period. The receiving device according to claim 1 or 2, wherein 4. An integrating means for integrating an error signal,
If the integrated value of the error signal in the latter half of the training period is larger than the integrated value of the error signal in the first half of the training period, the determination means determines that the sampling timing is shifted from the optimal timing of the equalization processing. The receiving device according to claim 1 or 2. 5. The method according to claim 1, wherein the determining unit determines that the sampling timing is shifted from the optimal timing of the equalization processing when the error signal in the message period is larger than the first threshold. Item 3. The receiving device according to Item 2. 6. An integrating means for integrating an error signal,
3. The method according to claim 1, wherein when the integrated value of the error signal during the training period is larger than the first threshold value, the determination unit determines that the sampling timing is shifted from the optimal timing of the equalization processing. The receiving device according to the above. 7. An error signal in a message period is a first error signal.
A counter for adding the number of times exceeding the threshold, wherein the determining means determines that the sampling timing is shifted from the optimal timing of the equalization processing when the number of times the counter adds is larger than the second threshold. The receiving device according to claim 1 or 2, wherein 8. The method according to claim 5, wherein the determining means selects the first threshold from a plurality of thresholds according to whether the error signal in the message period exceeds the third threshold. The receiving device according to the above. 9. The receiving apparatus according to claim 5, wherein said determining means sets a previous error signal as a first threshold value. 10. The determining means determines whether or not an absolute value obtained by subtracting the error signal at the end of the first half of the training period from the error signal at the end of the training period is larger than a fourth threshold value. 10. The receiving device according to claim 3, wherein when the value is determined to be larger than the fourth threshold value, the sampling clock is delayed by １ ／ sampling cycle. 11. A communication terminal device comprising the receiving device according to claim 1 and performing wireless communication. 12. A base station device comprising the receiving device according to claim 1 and performing wireless communication. 13. A wireless communication system comprising the receiving device according to claim 1 mounted on at least one of a communication terminal device and a base station device performing wireless communication. 14. Equalization processing is performed using an error signal obtained by subtracting a received signal from estimated transmission path characteristics, and a deviation between a sampling timing and an optimum timing of the equalization processing is determined based on the error signal. A sampling method, comprising: controlling a delay amount of a sampling clock based on the determination result; and performing AD conversion using the sampling clock whose delay amount is controlled. 15. The sampling method according to claim 14, wherein the sampling clock is delayed by a half sampling period when it is determined that the sampling timing deviates from the optimum timing of the equalization processing. 16. If the error signal at the end of the training period is larger than the error signal at the end of the first half of the training period, it is determined that the sampling timing is shifted from the optimal timing of the equalization processing. 16. The sampling method according to claim 14 or 15. 17. When the integrated value of the error signal in the latter half of the training period is larger than the integrated value of the error signal in the first half of the training period, it is determined that the sampling timing is shifted from the optimal timing of the equalization processing. The sampling method according to claim 14, wherein the sampling method is performed. 18. The method according to claim 14, wherein when the error signal in the message period is larger than the first threshold value, it is determined that the sampling timing is shifted from the optimal timing of the equalization processing. Sampling method. 19. The apparatus according to claim 14, wherein when the integrated value of the error signal during the training period is larger than the first threshold value, it is determined that the sampling timing is shifted from the optimum timing of the equalization processing. 15. The sampling method according to 15. 20. Addition of the number of times that the error signal exceeds the first threshold value in the message period, and when this addition value is larger than the second threshold value, it is determined that the sampling timing is shifted from the optimal timing of the equalization processing. The sampling method according to claim 14, wherein the sampling is performed. 21. The sampling method according to claim 18, wherein a first threshold is selected from a plurality of thresholds depending on whether an error signal in a message period exceeds a third threshold. . 22. The sampling method according to claim 18, wherein a previous error signal is used as a first threshold value. 23. It is determined whether an absolute value obtained by subtracting an error signal at the end of the first half of the training period from an error signal at the end of the training period is larger than a fourth threshold value, and the absolute value is larger than the fourth threshold value. 23. The sampling method according to claim 16, wherein the sampling clock is delayed by a 1/4 sampling period when it is determined that the sampling time has elapsed.