KR20060037476A - Method for calculating of a detecting apparatus - Google Patents

Abstract

In the method of calibrating the process inspection apparatus in order to accurately output the defect occurrence coordinates, first, the workpiece is inspected by the reference inspection apparatus to detect the defect, thereby obtaining a first defect coordinate list. The actual inspection device inspects the workpiece to obtain a second bad coordinate list. A coordinate error distribution chart is obtained by comparing the first bad coordinates and the second bad coordinates, respectively. Subsequently, the coordinate deflection of the actual inspection device is corrected through the coordinate error distribution. According to the above method, the error can be easily detected by minimizing the error of the bad coordinate.

Description

Method for calculating of a detecting apparatus

1 is a plan view showing a case where a detected defective coordinate is spaced apart from an actual defect position.

2 is a flowchart illustrating a method for correcting a bad coordinate according to an embodiment of the present invention.

3 is a graph illustrating an error between the X and Y axis first defective coordinates and the actual X and Y axis positions of the reference inspection apparatus.

4 is a graph showing an error between the X and Y axis second defective coordinates and the X and Y axis positions of actual defects.

5 and 6 are X- and Y-axis error distributions in the form of a wafer map.

7A is an X-axis error distribution diagram in the form of a wafer map.

7b to 7c are error distribution diagrams of the Y-axis and the X-axis of the chip during X-axis deflection.

The present invention relates to a method for correcting a semiconductor inspection device. More particularly, the present invention relates to a method of correcting defect coordinates accurately output in a semiconductor inspection apparatus.

In recent years, as the degree of integration of semiconductor devices increases, even minute defects, which have not been largely problematic in the past, cause malfunctions of semiconductor devices and have a fatal adverse effect on reliability of semiconductor devices. Examples of defects that may occur in the semiconductor device include particles, voids, dislocations, stacking faults, and interface faults.

Therefore, defects on the surface are inspected and measured before or after performing a unit process for manufacturing a semiconductor device. To this end, it is required to introduce a defect inspection apparatus that can accurately inspect the defects, and the fine control technology for the inspection apparatus determines the performance of the semiconductor device.

In general, a defect occurring in the semiconductor device is detected by comparing a predetermined region of a chip with an adjacent region of the chip to determine whether they are identical to each other. In addition, the detected defect can be directly confirmed by an electron microscope or an optical microscope. By identifying the defects directly, it is possible to know the true and upside of the detected defects, and to classify the defect types to identify process problems.

However, since the coordinate accuracy of the inspection apparatus is not high, the position of coordinates (hereinafter, referred to as defective coordinates) recognized as defective by the inspection apparatus does not exactly match the actual defect position generated on the substrate.                         

When the size of the defect is large, such as a few μm, the defect can be identified at a relatively low magnification, so that the defect can be easily detected even if the defect coordinates and the actual defect position in the inspection apparatus do not exactly match.

However, when the size of the defect is very fine, the defect can be identified only under high magnification, and thus, when the defect coordinates and the actual defect position in the inspection apparatus do not exactly match, it is not easy to grasp the position of the fine defect. .

1 is a plan view illustrating a case where a detected defective coordinate is spaced apart from an actual defective position.

Referring to FIG. 1, since the first defect coordinate 12 detected by the inspection apparatus is hardly spaced apart from the actual defect occurrence position 10, the defect may be detected even when using a microscope with a high magnification. However, since the second defective coordinate 12 detected by another inspection apparatus is greatly spaced apart from the actual defective position 10, the defect is not detected because it is out of the defective position in a microscope with a high magnification. Therefore, it is not easy to confirm an actual defect by the said 2nd defect coordinate.

As a result, the detected defects are often not recognized and the detected defects are frequently recognized as false data. In order to minimize this, the operator shifts the coordinates in which the defects are generated manually by a certain direction and detects the defects, and thus the time required for checking the defects is greatly increased.

Accordingly, an object of the present invention is to provide a method for calibrating a process inspection apparatus to accurately output a defect occurrence coordinate.

According to the inspection apparatus correction method of the present invention for achieving the above object, first, by inspecting the workpiece in the reference inspection apparatus to detect the defect of the workpiece to secure the first defect coordinate list. The actual inspection device inspects the workpiece to obtain a second bad coordinate list. A coordinate error distribution is obtained by comparing the first bad coordinates and the second bad coordinates, respectively. Subsequently, the defective coordinates of the inspection apparatus are corrected by correcting the coordinate deflection of the actual inspection apparatus through the coordinate error distribution.

The workpiece includes a wafer on which semiconductor devices are formed.

According to this method, accurate defective coordinates can be obtained in the actual inspection apparatus. For this reason, the defect which generate | occur | produced in the said workpiece can be confirmed easily.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a flowchart illustrating a method for correcting a bad coordinate according to an embodiment of the present invention.

Referring to FIG. 2, a wafer in which a semiconductor device manufacturing process is performed in a reference inspection device is inspected to detect defects occurring in the wafer. Then, the first defect coordinate list of the X-axis and the Y-axis of the position where the defect is generated is obtained. (S10) The types of the defects include particles, voids, dislocations, Stacking faults and interface faults.

The reference inspection device refers to a specific inspection device capable of outputting defective coordinates with relatively no error in a defective portion generated in a wafer as compared with other inspection devices. Therefore, the first defective coordinates output from the reference inspection apparatus serves as a reference for checking the degree of error of the defective coordinates output from the inspection apparatuses other than the reference inspection apparatus. Therefore, the reference inspection apparatus should be selected from the ones in which the coordinate error range between the defective X and Y coordinates and the actual defective position can be inspected within 2 μm in the positive direction and the negative direction, respectively. Preferably, the error range of the bad coordinates should be selected from those that can be inspected within 1 μm in the positive direction and the negative direction, respectively.

Specifically, the inspection apparatus using a TDI detector (Time Delay Integration detector) is suitable as the reference inspection apparatus because the error of the bad coordinates is very small because the movement of the stage is slow and the defect signal is inspected by the reflection method.

Next, by obtaining a second defective coordinate by calibrating the center of the first defective coordinates, the range of coordinate errors between actual defective positions is further reduced (S20).

3 is a graph showing an error between the X-axis and Y-axis first defect coordinates and the actual X-axis and Y-axis position in the reference inspection device, Figure 4 is a second X-axis and Y-axis after the correction of the center value It is a graph showing the error between the bad coordinates and the X and Y axis positions of the actual bad. In FIG. 3 and FIG. 4, the X-axis is divided by the position where the defect of the wafer is generated and the Y-axis represents the separation distance of each defect coordinate. Reference numeral 30 in FIG. 3 denotes an X-axis bad coordinate error, and reference numeral 32 denotes a Y-axis bad coordinate error. Reference numeral 30a in FIG. 4 denotes an X-axis bad coordinate error, and reference numeral 32a denotes a Y-axis bad coordinate error.

Referring to FIG. 3, it can be seen that the X and Y axis first defective coordinates and the X and Y axis positions of the actual defect are shifted in a predetermined direction. Therefore, as shown in FIG. 4, the first X-axis bad coordinates may move from left to right, and the first Y-axis bad coordinates may move from bottom to top to reduce an error. As described above, it can be seen that the error between the second defective coordinates on the X axis and the Y axis after the center value correction and the actual defective position can be inspected within 1.0 μm in the positive direction and the negative direction, respectively.

Next, the semiconductor wafer inspected by the reference inspection apparatus is introduced into a process inspection apparatus different from the reference inspection apparatus. The process inspection apparatus inspects the semiconductor wafer to secure a third defective coordinate list.

A coordinate error distribution chart is obtained by comparing the second defective coordinates and the corresponding third defective coordinates, respectively. (S40) The coordinate error distribution chart is a map so that the coordinate error distribution can be easily known for each position of the wafer. It can be represented in the form of or a chip (chip).

Specifically, the coordinate error distribution map in the form of a map may be formed by the following method.

First, a wafer map is formed in accordance with the shape of the semiconductor device formed on the wafer.                     

In the wafer map,

X variable = X axis bad coordinate in chip + bad chip number × X axis pitch of chip

Y variable = Y axis bad coordinates on chip + bad chip number × Y axis pitch of chip

Becomes

The third defective coordinate of the X axis corresponding to the second defective coordinate of the X axis is subtracted to obtain a difference as a coordinate error.

Each error section for grasping the level of the coordinate error is prepared, and the error section corresponding to the obtained error is grasped.

For example, the interval for determining the coordinate error level may be divided based on a tolerance of a field of view of a magnification of a conventionally used electron microscope. That is, when the tolerance is ± 2.5㎛, the first interval is less than -2.5㎛, the second interval is more than -2.5㎛ less than + 2.5㎛, the third interval within + 2.5㎛ range Can be specified. Then, it is checked which section corresponds to the coordinate error.

In addition, dotting is performed by distinguishing which section the coordinate error corresponds to a position where a defect occurs in the wafer map.

5 and 6 are X- and Y-axis error distributions in the form of a wafer map. In Fig. 5 and Fig. 6, the marked part is a coordinate error section of -6 to -2.5 μm, the marked part is a coordinate error section of -2.5 to +2.5 μm, and the marked part is a coordinate of +2.5 to +6 μm. Error interval                     

Referring to FIG. 5, the process analysis device shows positive deflections at the left and right sides of the wafer in the X-axis direction. In addition, referring to FIG. 6, it can be seen that the process analyzer does not show the deflection of coordinates in the Y-axis direction within an almost allowable error.

On the other hand, by viewing the entire wafer as one chip, the coordinate error distribution can also be represented in the form of a chip.

Specifically, the coordinate error distribution chart of the chip shape may be formed by the following method.

In the coordinate error distribution chart,

X variable = X axis bad coordinates in chip

Y variable = Y axis bad coordinate in the chip.

Then, the X-axis third defective coordinate corresponding to the X-axis second defective coordinate is subtracted to obtain the difference as the coordinate error.

Sections for distinguishing the level of the coordinate error are respectively provided, and the section to which the obtained coordinate error corresponds is grasped. Specifically, the first section may be specified as -2.5 µm or less, the second section is greater than -2.5 µm and less than +2.5 µm, and the third section may be +2.5 µm or more. In addition, the coordinate error corresponds to which section.

In addition, dotting is performed by distinguishing which section the coordinate error corresponds to a position where a defect occurs.                     

FIG. 7A is an X-axis error distribution diagram in the form of a wafer map, and FIGS. 7B to 7C are error distribution diagrams of the Y-axis and the X-axis of the chip during X-axis deflection. 7A to 7C, the marked part is a coordinate error section of -6 to -2.5 μm, the marked part is a coordinate error section of -2.5 to +2.5 μm, and the marked part is a coordinate of +2.5 to +6 μm. Error interval 7A-7C are the results obtained on the same wafer.

Referring to FIG. 7A, the wafer does not show severe deflection of coordinates in the X-axis direction. However, referring to FIG. 7B, the wafer shows an error tendency for each region in the Y-axis height direction. This can be seen as a swath propensity. In addition, referring to FIG. 7C, the wafer does not exhibit any tendency of error in the X-axis width direction.

By analyzing the coordinate error distribution chart obtained by the above method, it is possible to grasp the tendency of the coordinate deflection of the inspection apparatus. In addition, by identifying the coordinate deflection, it is possible to determine a problem of the inspection apparatus and to devise a method of correcting a bad coordinate.

Then, the process inspection apparatus is calibrated so that the coordinate deflection of the process inspection apparatus can be corrected. Thus, more accurate defect coordinates can be obtained through the process inspection apparatus. (S50)

As described above, according to the present invention, the inspection apparatus can be corrected to accurately output the defect occurrence coordinates. For this reason, detection of the said defect can be made easier, and the characteristic of a semiconductor device can be improved.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified without departing from the spirit and scope of the invention described in the claims below. And can be changed.

Claims (6)

Inspecting the workpiece by a reference inspection device to detect a defect and to obtain a first defect coordinate list; Inspecting the workpiece in an actual inspection device to obtain a second bad coordinate list; Comparing the first and second bad coordinates, respectively, to obtain a coordinate error distribution map; And And correcting the coordinate deflection of the actual inspection device through the coordinate error distribution. The inspection apparatus according to claim 1, wherein the reference inspection apparatus is a device in which the coordinate error range between the X and Y coordinates where the defect is inspected and the actual defective position is within 1 µm in the positive direction and the negative direction, respectively. Method of correction. The method of claim 1, further comprising correcting the first bad coordinates after securing the first bad coordinates list. The method of claim 1, wherein the coordinate error distribution chart is output in the form of a wafer map or a chip. The method according to claim 4, wherein the coordinate error distribution chart in the form of the wafer map is output to have a form displayed on the wafer map so as to be divided by coordinate error levels. The method of claim 4, wherein the coordinate error distribution chart of the chip shape is output to have a shape in which the wafer is shaped into one chip and displayed on the chip so as to be classified according to the level of the coordinate error.

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