KR20060035287A - Apparatus and method for updating isp - Google Patents

Abstract

The present invention relates to an apparatus and method for updating an ISP using an auxiliary memory. The ISP updating apparatus according to the present invention has an interface for exchanging data with an external device and has a microcomputer for processing TV application programs, a main memory for storing programs and related data started by the microcomputer, and A secondary memory for storing update-related data from the outside when the microcomputer is executing a program, a memory control IC for outputting write and read operation control signals of the main memory and the secondary memory according to the control of the microcomputer; And a start signal generator for outputting a signal for starting the memory control IC according to the control of the microcomputer.

According to the present invention, the microcomputer operating by using the program stored in the main memory is able to update the ISP while continuously operating without being affected, thereby increasing the processing speed of the TV running the ISP.

ISP update, secondary memory

Description

IPS update device and method {Apparatus and method for updating ISP}             

1 is a view showing an ISP update device in a conventional TV

2 is a diagram showing an ISP update apparatus using an auxiliary memory in a TV according to the present invention.

3A and 3B are timing diagrams illustrating an operation of an ISP update apparatus using an auxiliary memory according to the present invention.

<Description of the symbols for the main parts of the drawings>

210: micom 220: main memory

230: auxiliary memory 240: start signal generator

241: reset IC 242: delay IC

243: flip-flop 245: reset unit

250: memory control IC

The present invention relates to an apparatus and method for updating an ISP using an auxiliary memory.

In order to extend the TV function, it is common to embed a microcomputer that can execute an application program in the TV.

In order for the execution application to be used in the TV as described above, not only a microcomputer, but also a program that can be executed in the microcomputer, and a memory for storing data accordingly must be provided.

In general, after the initial production process, certain parts of the program are continuously upgraded to improve the program function according to the use of the program. The program stored in the TV executed by the microcomputer also can be updated by receiving the upgraded contents in real time through the network as the program is provided with an improved function by the upgrade.

1 is a diagram illustrating an apparatus for updating an ISP in a conventional TV.

As shown in FIG. 1, the ISP updating apparatus of a conventional TV includes a microcomputer 110 having an interface unit capable of transmitting and receiving data with an external serial port 160, a program that can be executed by the microcomputer, and a program thereof. And a main memory 120 and an auxiliary memory 130 for storing data associated with the same.

A process of updating a corresponding program by an ISP updating apparatus in a conventional TV having the above configuration will be described.

When the update-related data of the program is transmitted from the external serial port 160 to the TV 150 through the interface unit of the microcomputer 110, the microcomputer 110 receives the update information.

The microcomputer 110 controls the main memory 120 to be in a write and read enable state to update the update-related data to a program stored in the main memory 120. In this case, the auxiliary memory 130 is used for temporarily storing data when necessary in the data processing of the microcomputer 110.

However, in the conventional TV as described above, the ISP update device is a program that is currently running for the update when the update information for the corresponding program is transmitted while the microcomputer 120 is operating by loading the program. There is a difficult problem that must be stopped or abandoned.

The present invention receives an update-related data from the outside even while the microcomputer is operating by loading a program, using the auxiliary memory, and immediately assists when the microcomputer terminates the program or stops the operation. An object of the present invention is to provide an apparatus and method for updating an ISP using an auxiliary memory capable of updating by loading update-related data stored in a memory.

In order to achieve the above object, the ISP updating apparatus using the auxiliary memory according to the present invention is provided with an interface for exchanging data with an external device, and a microcomputer for processing TV application programs, and a program started by the microcomputer. And a main memory for storing related data, an auxiliary memory for storing update-related data from the outside when the microcomputer is executing a program, and a write and read operation of the main memory and the auxiliary memory under the control of the microcomputer. And a start signal generator for outputting a signal for starting the memory control IC according to the control of the microcomputer.

The start signal generator comprises a flip-flop for generating a start signal to the memory control IC under the control of the micom, and a reset unit for receiving the self reset signal of the micom and resetting the micom and the flip-flop. .

The reset unit may include a reset IC for outputting a reset signal and a delay IC for delaying and outputting the reset signal for a predetermined time.

In addition, the ISP update method using the auxiliary memory according to the present invention for achieving the above object, the step of loading the data necessary for the update in the auxiliary memory as the update request signal is input from the external terminal, and the data required for the update When the loading step is completed, the microcomputer is changed to a state under the control of the auxiliary memory program, and the microcomputer is loaded into the auxiliary memory according to the program of the auxiliary memory under the control of the program of the auxiliary memory. And loading the data into the main memory.

Hereinafter, an ISP updating apparatus and method using an auxiliary memory according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram illustrating an apparatus for updating an ISP using an auxiliary memory according to the present invention.

As shown in FIG. 2, the ISP updating apparatus using the auxiliary memory according to the present invention includes a microcomputer 210, a main memory 220, an auxiliary memory 230, a memory control IC 250, and a start signal. It is configured to include a generator 240.

The microcomputer 210 processes the application program started on the TV and controls the function of the TV. In addition, the microcomputer has an interface for exchanging data with an external device, such as receiving data from an external device or outputting data stored in an internal storage means to an external device, if necessary.

The main memory 220 may be mainly composed of a memory device such as a nonvolatile memory having a high data input / output speed, and stores a program and related data started by the microcomputer 210. In addition, programs and related data related to TV add-ons are stored.

The auxiliary memory 230 mainly includes a memory device such as a RAM and the like, and stores the update-related data from the outside when the microcomputer 210 is executing a program. The auxiliary memory 230 temporarily stores data necessary for the execution of the program by the microcomputer 210 or data generated temporarily during the execution of the program.

The start signal generator 240 includes a flip-flop 243 and a reset unit 245, and outputs a signal for starting the memory control IC 250 under the control of the microcomputer 210.

The flip-flop 243 may be configured as a flip-flop, and generates a start signal to the memory control IC 250 under the control of the microcomputer 210.

The reset unit 245 includes a reset IC 241 and a delay IC 242, and resets the microcomputer 210 and the flip-flop 243 by the self reset signal of the microcomputer 210.

The reset IC 241 outputs a reset signal, and the delay IC 242 delays the reset signal for a predetermined time and outputs the reset signal. The delay time is about 150 to 300 Hz.

The memory control IC 250 writes and reads the main memory 220 and the auxiliary memory 230 according to a control signal of the microcomputer 210 and an output signal of the start signal generator 240. To control.

The memory control IC 250 may control signals such as a read signal RDB, a write signal WRB, a data input / output enable PSEN, and the like, a power signal VDD, and the start signal output from the microcomputer 210. The output signal of the generator 240 is input.

The output signal of the memory control IC 250 may include an output enable signal ROM_OE of the main memory 220, a write enable signal ROM_WE of the main memory 220, and an output enable signal of the auxiliary memory 230. (RAM_OE) and the write enable signal RAM_WE of the auxiliary memory 230.

The signal output by the memory control IC 250 to control the main memory 220 and the auxiliary memory 230 according to the output signal S of the start signal generator 240 is shown in the following table. .

S input signal High (H) Low (L) ROM_OE PSEN RDB ROM_WE VDD WRB RAM_OE RDB PSEN RAM_WE WRB VDD

That is, when the start signal generator 240 outputs a low L signal to the S input terminal of the memory control IC 250, the main memory 220 performs normal data communication with the microcomputer 210. (PSEN state), the auxiliary memory 230 is enabled in the read and write mode to load the update data input from the external terminal.

When the start signal generator 240 outputs a high (H) signal and is input to the S input terminal of the memory control IC 250, the auxiliary memory 230 performs normal data communication with the microcomputer 210 (PSEN state). In the main memory 220, read and write modes are enabled, and thus the main memory 220 may load update data stored in the auxiliary memory 230.

The operation of the ISP updating apparatus according to the present invention configured as described above will be described with reference to FIGS. 3A and 3B.

3A and 3B are timing diagrams illustrating an operation of an ISP updater using an auxiliary memory according to the present invention.

3A is a timing diagram illustrating an initial operation state of an ISP update apparatus using an auxiliary memory according to the present invention when a normal operation is performed by an ISP stored in a TV system.

As shown in FIG. 3A, in the state in which the microcomputer 210 operates normally by the ISP stored in the main memory 220 because there is no update request, the power supply VDD remains high (H). The signal output from 241 remains high (H).

The self reset (Self_reset) signal output at the time t0 from the microcomputer 210 is input to the delay IC 242 and becomes a time delay of about 150 to 300 microseconds. ), The ISP update device using the auxiliary memory 230 according to the present invention is placed in an operation standby state.

In this case, the download switch signal Down_SW output from the microcomputer 210 is kept high (H) and is applied to the flip-flop 243 in the start signal generator 240. Accordingly, the output terminal Q of the flip-flop 243 is input to the memory control IC 250 while the output signal in the low L state is maintained as it is.

As the low (L) state is input to the S input terminal of the memory control IC 250, the main memory 220 performs normal data communication with the microcomputer 210 (PSEN state), and the auxiliary memory 230 reads. And the write mode is enabled so that the update data input from the external terminal can be loaded.

While the status of each component constituting the ISP updating apparatus using the auxiliary memory according to the present invention is maintained as described above, when update data is input from an external terminal, the ISP updating apparatus using the auxiliary memory according to the present invention is an ISP. It will execute the action for update.

3B is a timing diagram when an ISP update apparatus using an auxiliary memory according to the present invention performs an operation for updating when update data is input from an external terminal.

First, when the update message is received (t0), the auxiliary memory 230 which maintains a state capable of receiving the update data receives the update data from the external terminal and loads the data necessary for the update (step A).

When it is determined that the loading process of the data necessary for the update is finished and the update can be executed, the microcomputer 210 outputs the download switch signal Down_SW (t2).

In response to the download switch signal Down_SW, the flip-flop 243 of the start signal generator 240 outputs a high H signal so that the high H signal is applied to the input terminal S of the memory control IC 250. To be entered.

At this time, the control signal output from the output terminal of the memory control IC 250, the auxiliary memory 230 is a normal data communication with the microcomputer 210 (PSEN state), the main memory 220 is read and write mode is In the enabled state, the update data stored in the auxiliary memory 230 is changed into a loadable state.

Accordingly, the microcomputer 210 executes the update by the program received and stored in the auxiliary memory 230. Since the main memory 220 has read and write modes enabled, the microcomputer 210 transmits data for update stored in the auxiliary memory 230 to the control signal RDB, of the memory control IC 250. WRB is loaded into the main memory 220 to complete the update (step B).

When the update is completed by the above process, the microcomputer 210 outputs the self reset signal Self_reset signal to the reset unit 245 (t3). The self-reset signal Self_reset signal input to the reset unit 245 is a microcomputer reset for resetting the microcomputer 210 and the flip-flop 243 after a delay of about 150 to 300 s by the delay IC 242. Output the signal Reset_M.

The microcomputer 210 is reset to an initial state according to the output of the microcomputer reset signal Reset_M of the reset unit 245. In addition, the flip-flop 243 outputs a low (L) signal to the memory control IC 250 by the reset signal input to the flip-flop 243 to bring the ISP update apparatus according to the present invention to an initial operation state. Will be maintained.

According to the ISP update apparatus and method according to the present invention, the ISP update is executed by using the auxiliary memory, so that the microcomputer operating by using the program stored in the main memory can be operated continuously without being affected. This can increase the processing speed of the TV running the ISP.

In addition, although the embodiments of the present invention have been described with reference to the accompanying drawings, the present invention is not limited thereto, and changes and modifications are included in the present invention without departing from the spirit of the present invention and will be apparent to those skilled in the art. will be.

Claims (4)

A microcomputer having an interface for exchanging data with an external device and processing an application program of the television; A main memory for storing a program started by the microcomputer and related data; An auxiliary memory for storing update related data from the outside when the microcomputer is executing a program; A memory control IC configured to output write and read operation control signals of the main memory and the auxiliary memory according to the control of the microcomputer; And a start signal generator for outputting a signal for starting the memory control IC according to the control of the microcomputer. The method of claim 1, wherein the start signal generator, A flip-flop for generating a start signal to the memory control IC according to the control of the microcomputer; And a reset unit configured to receive the self reset signal of the micom and reset the micom and the flip-flop. The method of claim 2, wherein the reset unit, A reset IC for outputting a reset signal; And a delay IC configured to delay and output the reset signal for a predetermined time. Loading data necessary for the update into the auxiliary memory as the update request signal is input from an external terminal; When the loading of the data required for the update is completed, changing the state of the microcomputer to a state controlled by a program of the auxiliary memory; And loading the data loaded in the auxiliary memory into the main memory according to the program of the auxiliary memory in the state in which the microcomputer is controlled by the program of the auxiliary memory. .

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