KR20060033983A - Nmosfet of semicondutor device and fabricating method for the same - Google Patents

Nmosfet of semicondutor device and fabricating method for the same Download PDF

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KR20060033983A
KR20060033983A KR1020040083090A KR20040083090A KR20060033983A KR 20060033983 A KR20060033983 A KR 20060033983A KR 1020040083090 A KR1020040083090 A KR 1020040083090A KR 20040083090 A KR20040083090 A KR 20040083090A KR 20060033983 A KR20060033983 A KR 20060033983A
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substrate
forming
gate pattern
semiconductor device
nmos transistor
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Korean (ko)
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이진열
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures

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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract

본 발명은 누설전류(Leakage Current)를 감소시켜 리프레쉬(Refresh)특성을 향상시킬 수 있는 반도체 소자의 NMOS트랜지스터 및 그의 제조 방법에 관한 것으로, 기판의 표면 하부에 문턱전압 조절을 위해 P형 불순물을 이온주입하는 단계; 상기 기판 상에 게이트 패턴의 폭을 정의하는 희생 하드마스크를 형성하는 단계; 전면식각을 실시하여 상기 희생 하드마스크의 형상을 상기 기판에 전사시켜 상기 게이트 패턴 형성영역의 기판에 돌출부를 형성하는 단계; 상기 게이트 패턴의 측면에 얼라인 되도록 상기 기판에 소스/드레인 접합영역을 형성하는 단계를 포함한다.
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an NMOS transistor of a semiconductor device capable of improving the refresh characteristics by reducing leakage current, and a method of manufacturing the same. Injecting; Forming a sacrificial hardmask defining a width of a gate pattern on the substrate; Performing surface etching to transfer the shape of the sacrificial hard mask to the substrate to form protrusions on the substrate of the gate pattern forming region; And forming a source / drain junction region in the substrate to be aligned with the side surface of the gate pattern.

누설전류(Leakage Current), 리프레쉬(Refresh), 돌출부Leakage Current, Refresh, Projection

Description

반도체 소자의 ＮＭＯＳ트랜지스터 및 그의 제조 방법{NMOSFET OF SEMICONDUTOR DEVICE AND FABRICATING METHOD FOR THE SAME} NMOS transistor of semiconductor device and manufacturing method thereof {NMOSFET OF SEMICONDUTOR DEVICE AND FABRICATING METHOD FOR THE SAME}             

도 1은 종래기술에 따라 제조된 반도체 소자의 NMOS트랜지스터 구조를 나타내는 단면도,1 is a cross-sectional view showing an NMOS transistor structure of a semiconductor device manufactured according to the prior art;

도 2는 본 발명의 바람직한 실시예에 따라 제조된 반도체 소자의 NMOS트랜지스터의 구조를 나타내는 단면도,2 is a cross-sectional view showing a structure of an NMOS transistor of a semiconductor device manufactured according to a preferred embodiment of the present invention;

도 3a 내지 도 3d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 NMOS트랜지스터 제조 방법을 도시한 공정단면도.
3A to 3D are cross-sectional views illustrating a method of manufacturing an NMOS transistor in a semiconductor device according to a preferred embodiment of the present invention.

*도면의 주요 부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

30 : 기판 31 : 필드 산화막30 substrate 31 field oxide film

32 : 딥웰 33 : 셀웰32: Deepwell 33: Selwell

34 : 필드스탑영역 35 : P형 불순물영역34: field stop region 35: P-type impurity region

36 : 희생 하드마스크 37 : 돌출부36: sacrificial hard mask 37: protrusion

G : 게이트 패턴 T : 트렌치G: gate pattern T: trench

39 : 소스/드레인 접합영역39: source / drain junction area

본 발명은 반도체 소자의 NMOS트랜지스터 및 그의 제조 방법에 관한 것으로, 특히 누설전류(Leakage Current)를 감소시켜 리프레쉬(Refresh)특성을 향상시킬 수 있는 반도체 소자의 NMOS트랜지스터 및 그의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an NMOS transistor of a semiconductor device and a method of manufacturing the same, and more particularly, to an NMOS transistor of a semiconductor device and a method of manufacturing the same that can improve refresh characteristics by reducing leakage current.

반도체 소자의 직접도가 증가함에 따라 각 패턴들의 크기도 점점작아지는 추세이다. 특히 DRAM과 같은 메모리 소자는 고직접화로 인하여 필요한 문턱전압(Vt)의 확보를 위해 셀 영역에서 채널형성을 위한 불순물의 이온주입양이 증가하게 된다. 이러한 이온주입된 불순물은 소스/드레인 접합영역에 잔존하여 리프레쉬(Refresh)특성에 영향을 미친다.As the directivity of the semiconductor device increases, the size of each pattern also decreases. In particular, in the memory devices such as DRAM, the ion implantation amount of impurities for channel formation is increased in the cell region in order to secure the necessary threshold voltage (Vt). The ion implanted impurities remain in the source / drain junction region to affect the refresh characteristics.

도 1은 종래기술에 따라 제조된 반도체 소자의 NMOS트랜지스터 구조를 나타내는 단면도이다.1 is a cross-sectional view showing an NMOS transistor structure of a semiconductor device manufactured according to the prior art.

도 1을 참조하여 종래기술에 따른 반도체 소자의 트랜지스터 제조 방법을 살펴보면, 기판(10)의 하부에 불순물을 이온주입하여 필드스탑(Field Stop; 11)영역을 형성한다.Referring to FIG. 1, a method of manufacturing a transistor of a semiconductor device according to the related art is described. A field stop region is formed by implanting impurities into a lower portion of a substrate 10.

이어서, 기판(10)의 표면하부에 채널형성을 위한 문턱전압 조절을 위해 P형 불순물을 이온주입하여 P형 불순물영역(12)을 형성한 후, 기판(10) 상에 게이트패턴(13) 및 측벽에 스페이서(13)를 형성한다. 이어서, 게이트패턴(G1)의 측면에 얼라인된 기판(10)하부에 N형의 불순물을 이온주입하여 소스/드레인 접합영역(14)을 형성함으로써, 셀 영역에 NMOS트랜지스터를 완성한다.Subsequently, the P-type impurity region 12 is formed by ion implanting P-type impurities to adjust the threshold voltage for channel formation under the surface of the substrate 10. Then, the gate pattern 13 and the substrate 10 are formed on the substrate 10. The spacer 13 is formed on the side wall. Subsequently, an N-type impurity is implanted under the substrate 10 aligned with the side of the gate pattern G1 to form a source / drain junction region 14, thereby completing an NMOS transistor in the cell region.

상기와 같은 종래기술은 디자인룰이 감소하면서 셀 영역에서 게이트의 채널길이가 줄어들어 디바이스 동작에 필요한 문턱전압(Vt)을 얻기 위해서는 P형 불순물영역(12)에 이온주입되는 불순물의 양을 증가시켜야 한다. In the related art as described above, in order to reduce the channel length of the gate in the cell region while decreasing the design rule, the amount of impurities implanted into the P-type impurity region 12 must be increased in order to obtain the threshold voltage (Vt) required for device operation. .

이온주입된 P형의 불순물은 소스/드레인 접합영역(14)형성 후에도 소스/드레인 접합(14)영역에 잔존하게 된다. 잔존한 P형의 불순물은 접합공핍영역(D)의 전계를 크게하여 누설전류가 증가된다. 즉, 필요한 문턱전압(Vt)을 확보하기 위해 채널영역에 불순물을 증가시킬수록 빠져나가는 누설전류가 비례하여 증가하게 되어 리프레쉬(Refresh)특성이 열화되는 문제점이 있었다.
The ion implanted P-type impurities remain in the source / drain junction 14 region even after the source / drain junction region 14 is formed. Residual P-type impurities increase the electric field of the junction depletion region D to increase the leakage current. That is, as the impurity is increased in the channel region in order to secure the required threshold voltage Vt, the leakage current flowing out increases proportionally, causing a problem in that the refresh characteristic is deteriorated.

본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 소스/드레인 접합영역에서 발생하는 누설전류(Leakage Current)를 감소시켜 리프레쉬(Refresh)특성을 향상시킬수 있는 반도체 소자의 NMOS트랜지스터 및 그의 제조 방법을 제공하는데 그 목적이 있다.
Disclosure of Invention The present invention has been made in view of the above-described problems, and an NMOS transistor of a semiconductor device capable of improving refresh characteristics by reducing leakage current generated in a source / drain junction region, and a method of manufacturing the same. The purpose is to provide.

상기한 목적을 달성하기 위한 본 발명은 돌출부를 갖는 기판; 상기 기판의 돌출부 상에 형성된 게이트 패턴; 및 상기 게이트 패턴의 측면에 얼라인 된 상기 기판에 형성된 소스/드레인 접합영역을 포함하며, 상기 돌출부에 채널이 유기되는 반도체 소자의 NMOS트랜지스터를 제공한다.
The present invention for achieving the above object is a substrate having a projection; A gate pattern formed on the protrusion of the substrate; And a source / drain junction region formed on the substrate aligned with the side of the gate pattern, and provides an NMOS transistor of a semiconductor device in which a channel is organically formed in the protrusion.

또한, 본 발명은 기판의 표면 하부에 문턱전압 조절을 위해 P형 불순물을 이온주입하는 단계; 상기 기판 상에 게이트 패턴의 폭을 정의하는 희생 하드마스크를 형성하는 단계; 전면식각을 실시하여 상기 희생 하드마스크의 형상을 상기 기판에 전사시켜 상기 게이트 패턴 형성영역의 기판에 돌출부를 형성하는 단계; 상기 게이트 패턴의 측면에 얼라인 되도록 상기 기판에 소스/드레인 접합영역을 형성하는 단계를 포함하는 반도체 소자의 NMOS트랜지스터 제조 방법을 제공한다.
In addition, the present invention comprises the steps of ion implantation of the P-type impurities in the lower surface of the substrate to control the threshold voltage; Forming a sacrificial hardmask defining a width of a gate pattern on the substrate; Performing surface etching to transfer the shape of the sacrificial hard mask to the substrate to form protrusions on the substrate of the gate pattern forming region; It provides a method for manufacturing an NMOS transistor of a semiconductor device comprising forming a source / drain junction region on the substrate to be aligned with the side of the gate pattern.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부한 도면을 참조하여 상세히 설명한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

도 2는 본 발명의 바람직한 실시예에 따라 제조된 반도체 소자의 NMOS트랜지스터의 구조를 나타내는 단면도이다.2 is a cross-sectional view illustrating a structure of an NMOS transistor of a semiconductor device manufactured according to a preferred embodiment of the present invention.

도 2를 참조하면, 필드산화막(21) 및 돌출부(27)가 형성된 기판(20)의 하부에 셀 트랜지스터의 동작특성 향상을 위한 딥웰(Deep Well; 22)을 형성되고, 딥웰(Deep Well; 22)의 상부에 셀웰(Cell Well; 23)이 형성된다. 필드산화막(21)이 형성된 기판(20)의 하부에 불순물을 이온주입된 필드스탑영역(Field Stop; 24)을 형성된다.Referring to FIG. 2, a deep well 22 is formed below the substrate 20 on which the field oxide film 21 and the protrusion 27 are formed to improve operating characteristics of the cell transistor, and a deep well 22 Cell Well (23) is formed on the top. A field stop region 24 in which impurities are ion implanted is formed under the substrate 20 on which the field oxide film 21 is formed.

돌출부(27)에는 문턱전압 조절을 위한 P형의 불순물을 이온주입하여 P형 불 순물영역(25)을 형성된다. 돌출부 상에 게이트 패턴(G2)이 형성되고, 게이트 패턴(G2)의 측면에 얼라인된 기판하부에는 소스/드레인 접합영역(29)이 형성된다. 트랜지스터 동작시 돌출부의 P형 불순물 영역(25a)에 채널이 유기된다. P-type impurity regions 25 are formed in the protrusions 27 by implanting P-type impurities for adjusting the threshold voltage. A gate pattern G2 is formed on the protrusion, and a source / drain junction region 29 is formed under the substrate aligned with the side surface of the gate pattern G2. During transistor operation, a channel is induced in the P-type impurity region 25a of the protrusion.

도 3a 내지 도 3d는 본 발명의 바람직한 실시예에 따른 반도체 소자의 NMOS트랜지스터 제조 방법을 도시한 공정단면도이다.3A to 3D are cross-sectional views illustrating a method of manufacturing an NMOS transistor in a semiconductor device according to a preferred embodiment of the present invention.

도 3a를 참조하면, 기판(30) 상에 마스크패턴(도면에 도시되지 않음)형성 및 식각공정을 통하여 기판(30)의 소자분리영역에 트렌치(T)를 형성한다. 바람직한 트렌치(T)의 깊이는 3000∼4000Å이다. 이어서, 소자분리를 위한 HDP 산화물질을 증착한후, 습식식각을 통해 필드산화막(31)을 형성한다. 필드산화막(31)은 트렌치(T)의 깊이보다 낮은 두께로 형성한다.Referring to FIG. 3A, the trench T is formed in the device isolation region of the substrate 30 by forming and etching a mask pattern (not shown) on the substrate 30. Preferred trenches T have a depth of 3000 to 4000 mm. Subsequently, after depositing the HDP oxide material for device isolation, the field oxide layer 31 is formed through wet etching. The field oxide film 31 is formed to a thickness lower than the depth of the trench T.

이어서, 기판(30)의 하부에 셀 트랜지스터의 동작특성 향상을 위하여 N형 불순물을 이온주입한 딥웰(Deep Well; 32)을 형성하고, 딥웰(Deep Well; 32)의 상부에 셀웰(Cell Well; 33)을 형성한다. 셀웰(Cell Well; 33)은 NMOS트랜지스터 형성을 위한 것으로 P형 불순물을 이온주입하여 형성한다.Subsequently, a deep well 32 in which N-type impurities are ion-implanted is formed below the substrate 30 to improve operating characteristics of the cell transistor, and a cell well is formed on the deep well 32. 33). Cell Well 33 is for forming an NMOS transistor and is formed by ion implantation of P-type impurities.

이어서, 필드산화막(31)이 형성된 기판(30)의 하부에 불순물을 이온주입하여 필드스탑영역(Field Stop; 34)을 형성한다.Subsequently, impurities are implanted into the lower portion of the substrate 30 on which the field oxide film 31 is formed to form a field stop region 34.

여기서, 딥웰(Deep Well; 32), 셀웰(Cell Well; 33) 및 필드스탑영역(Field Stop; 34)은 후속공정에서 기판(30)이 식각되는 깊이를 고려하여 충분한 마진을 갖는 깊이에 형성한다.Here, the deep well 32, the cell well 33 and the field stop 34 are formed at a depth having sufficient margin in consideration of the depth at which the substrate 30 is etched in a subsequent process. .

이어서, 기판(30)의 표면 하부에 채널 형성을 위한 문턱전압 조절을 위한 P 형의 불순물을 이온주입하여 P형 불순물영역(35)을 형성한다. Subsequently, a P-type impurity region 35 is formed by ion implanting P-type impurities for controlling the threshold voltage for channel formation under the surface of the substrate 30.

이어서, 도 3b에 도시된 바와 같이, 기판(30) 상에 희생 하드마스크용 폴리실리콘막을 증착하고, 폴리실리콘막 상에 후속공정의 형성되는 게이트 전극 형성을 위한 마스크패턴(도면에 도시되지 않음)을 형성한다. 이어서, 마스크패턴을 식각마스크로 폴리실리콘막을 식각하여 희생 하드마스크(36)을 형성한다.Subsequently, as shown in FIG. 3B, a polysilicon film for a sacrificial hard mask is deposited on the substrate 30, and a mask pattern for forming a gate electrode formed in a subsequent process on the polysilicon film (not shown). To form. Subsequently, the polysilicon layer is etched using the mask pattern as an etch mask to form a sacrificial hard mask 36.

이어서, 도 3c에 도시된 바와 같이, 전면식각을 실시하여 희생 하드마스크(36)의 형상을 기판에 전사기켜 게이트 전극 형성영역에 돌출부(37)를 형성한다. 여기서, 전면식각을 진행하면 돌출부(37) 이외에 형성된 P형 불순물영역은 제거되고, 이후, 트랜지스터 동작시 돌출부의 P형 불순물 영역(35)에 채널이 유기된다. Subsequently, as shown in FIG. 3C, the entire surface is etched to transfer the shape of the sacrificial hard mask 36 to the substrate to form the protrusion 37 in the gate electrode formation region. In this case, when the entire surface is etched, the P-type impurity region formed in addition to the protrusion 37 is removed, and then a channel is induced in the P-type impurity region 35 of the protrusion during transistor operation.

이어서, 돌출부 상에 게이트 산화막(38a), 폴리실리콘막(38b), 금속(또는 금속실리사이드; 38c) 및 하드마스크용 절연막(38d)을 차례로 증착후 이를 선택적으로 식각하여 게이트 패턴(G3)을 형성하고, 게이트 패턴(G3)의 측면에 얼라인 된 기판에 N형의 불순물을 이온주입하여 소스/드레인 접합영역(39)을 형성한다.Subsequently, the gate oxide film 38a, the polysilicon film 38b, the metal (or metal silicide; 38c), and the hard mask insulating film 38d are sequentially deposited on the protrusions, and then selectively etched to form the gate pattern G3. The source / drain junction region 39 is formed by implanting N-type impurities into the substrate aligned on the side surface of the gate pattern G3.

상기와 같은 본 발명은 기판에 돌출부를 형성하여 문턱전압 조절을 위한 P형 불순물 영역과 N형 불순물이 이온주입된 소스/드레인 접합영역을 격리시킴으로써, 필요한 문턱전압(Vt)을 확보하기 위해 채널영역에 불순물을 증가시키더라도 P형 불순물에 의한 누설전류가 발생하지 않아 리프레쉬(refresh)특성이 열화되는 것을 방지할수 있다.
The present invention as described above forms a protrusion on the substrate to isolate the P-type impurity region for the threshold voltage and the source / drain junction region into which the N-type impurity is ion-implanted, thereby securing the required threshold voltage Vt. Even if the impurity is increased, leakage current caused by the P-type impurity does not occur, thereby preventing the refresh characteristic from deteriorating.

상술한 본 발명에 의하면 문턱전압 조절을 위한 P형 불순물 영역과 소스/드레인 접합영역을 격리시켜 소스/드레인 접합영역에 P형 불순물이 잔존하는 것을 방지함으로써, 누설전류(Leakage Current)를 감소시켜 리프레쉬(Refresh)특성을 향상시킬수 있다. According to the present invention described above, the P-type impurity region for controlling the threshold voltage and the source / drain junction region are isolated to prevent the P-type impurity from remaining in the source / drain junction region, thereby reducing leakage current to refresh. (Refresh) can be improved.

Claims (5)

돌출부를 갖는 기판;A substrate having protrusions; 상기 기판의 돌출부 상에 형성된 게이트 패턴; 및A gate pattern formed on the protrusion of the substrate; And 상기 게이트 패턴의 측면에 얼라인 된 상기 기판에 형성된 소스/드레인 접합영역Source / drain junction regions formed in the substrate aligned with the side surfaces of the gate pattern 을 포함하며, Including; 상기 돌출부에 채널이 유기되는 반도체 소자의 NMOS트랜지스터.An NMOS transistor of a semiconductor device in which a channel is organic to the protrusion. 제1항에 있어서,The method of claim 1, 문턱전압 조절을 위해 상기 돌출부에 형성된 P형 불순물 영역을 더 포함하는 반도체 소자의 NMOS트랜지스터.The NMOS transistor of the semiconductor device further comprises a P-type impurity region formed in the protrusion to control the threshold voltage. 기판의 표면 하부에 문턱전압 조절을 위해 P형 불순물을 이온주입하는 단계;Implanting P-type impurities into the lower surface of the substrate to adjust the threshold voltage; 상기 기판 상에 게이트 패턴의 폭을 정의하는 희생 하드마스크를 형성하는 단계; Forming a sacrificial hardmask defining a width of a gate pattern on the substrate; 전면식각을 실시하여 상기 희생 하드마스크의 형상을 상기 기판에 전사시켜 상기 게이트 패턴 형성영역의 기판에 돌출부를 형성하는 단계;Performing surface etching to transfer the shape of the sacrificial hard mask to the substrate to form protrusions on the substrate of the gate pattern forming region; 상기 게이트 패턴의 측면에 얼라인 되도록 상기 기판에 소스/드레인 접합영역을 형성하는 단계Forming a source / drain junction region in the substrate to be aligned with the side surface of the gate pattern; 를 포함하는 반도체 소자의 NMOS트랜지스터 제조 방법.NMOS transistor manufacturing method of a semiconductor device comprising a. 제3항에 있어서,The method of claim 3, 상기 돌출부의 P형 불순물영역에 채널이 유기되는 반도체 소자의 NMOS트랜지스터 제조 방법.A method of manufacturing an NMOS transistor in a semiconductor device in which a channel is induced in a P-type impurity region of the protrusion. 제3항에 있어서,The method of claim 3, 상기 희생 하드마스크를 형성하는 단계는,Forming the sacrificial hard mask, 상기 기판 상에 희생 하드마스크용 폴리실리콘막을 증착하는 단계와, 상기 폴리실리콘막 상에 게이트 패턴 형성을 위한 마스크패턴을 형성하는 단계와, 상기 마스크패턴을 식각마스크로 폴리실리콘막을 식각하여 희생 하드마스크를 형성하는 단계를 더 포함하는 반도체 소자의 NMOS트랜지스터 제조 방법.Depositing a polysilicon film for a sacrificial hard mask on the substrate, forming a mask pattern for forming a gate pattern on the polysilicon film, and etching a polysilicon film using the mask pattern as an etching mask NMOS transistor manufacturing method of a semiconductor device further comprising forming a.
KR1020040083090A 2004-10-18 2004-10-18 Nmosfet of semicondutor device and fabricating method for the same KR20060033983A (en)

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