KR20060029063A - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display for dividing a liquid crystal panel into a plurality of regions and applying a scanning signal to the divided regions, thereby minimizing distortion and delay of the scanning signal to prevent image degradation. A substrate divided into a second region, a plurality of data lines arranged in a longitudinal direction on the substrate, and substantially perpendicular to the data lines to define a plurality of pixels, the pixels of the first region and the second region And a thin film transistor disposed in the pixel, and a gate line structure for applying an external signal through another path.

Liquid Crystal Panel, Division, Gate Line, Distortion, Scanning Signal

Description

Liquid crystal display {LIQUID CRYSTAL DISPLAY DEVICE}

1 is a block diagram schematically showing a general liquid crystal display device.

FIG. 2 shows an equivalent circuit of the liquid crystal panel of FIG.

3 is a view illustrating a change in a scan signal transmitted through a gate line.

4 is a plan view showing a liquid crystal display device according to the present invention;

FIG. 5 is a cross-sectional view of a thin film transistor array substrate in enlarged view of part I-I in FIG.

*** Description of the symbols for the main parts of the drawings ***

210: liquid crystal panel 215: data line

216a: first gate line 216b: second gate line

220: data driver 230: gate driver

P10: pixel T10: switching element

Vg: Scanning signal AREA1: First panel area

AREA2: Second Panel Area

The present invention is directed to a liquid crystal display device which can prevent deterioration in image quality due to signal distortion by dividing a liquid crystal panel into a plurality of regions and applying a scanning signal to each of the divided regions. It is about.

In recent years, with the development of information technology (IT), display devices are becoming more important as a transmission medium of various visual information, and various kinds of display devices have already been developed and used. Among them, the liquid crystal display device is being developed as a main product of the display that can replace the cathode ray tube (CRT) due to the advantages of low power consumption, thinness, light weight and high quality.

Liquid crystal display is a device that displays an image by using optical anisotropy of liquid crystal. In general, the liquid crystal display adjusts the light transmittance of pixels by separately supplying image information to pixels arranged in a matrix form. In this way, the display device can display a desired image. Accordingly, the liquid crystal display includes a liquid crystal panel in which pixels, which are the smallest units for implementing an image, are arranged in an active matrix form, and a driving unit for driving the liquid crystal panel. A backlight unit for supplying light to the liquid crystal panel is provided.

The liquid crystal display as described above will be described with reference to the accompanying drawings.

1 is a block diagram schematically illustrating a general liquid crystal display device.

Referring to FIG. 1, a liquid crystal display includes a liquid crystal panel 10 in which a plurality of pixels P are arranged in a matrix, and a gate for applying a scan signal to the pixels P of the liquid crystal panel 10. The driver 30, the data driver 20 to apply an image information to the pixel P to which the scan signal is applied by the gate driver 30, to display an image, and various control signals by receiving external data. The timing controller 40 forms a driving voltage and supplies the driving voltage to the data driver 20 and the gate driver 30.

The liquid crystal panel 10 is manufactured by bonding a thin film transistor array substrate and a color filter substrate to a predetermined cell gap, and forming a liquid crystal layer in a space between the cell gaps. do.

A plurality of gate lines 16 are arranged in the transverse direction and a plurality of data lines 15 are arranged in the longitudinal direction on the thin film transistor array substrate. The gate line 16 and the data line 15 cross each other to define a plurality of regions, and define the region as the pixel P. FIG.

One side of the pixel P is provided with a switching element such as a thin film transistor and electrically connected to the data line 15 and the gate line 16.

The timing controller 40 receives image-related information from an external system such as a graphic card, converts the generated signal into a control signal and a driving voltage suitable for driving the liquid crystal display, and generates the gate driver 30 and The data driver 20 is applied.

The gate driver 30 receives a control signal and a driving voltage from the timing controller 40 and sequentially applies a scan signal to the gate line 16. When a scan signal is applied to the gate line 16, the plurality of switching elements connected to the gate line 16 are conducted by the scan signal. In this case, the data driver 20 outputs image information through the data line 15, and the image information applied to the pixel P through the switching element is transferred to the pixel electrode provided in the pixel P. Is approved. Therefore, an electric field is formed by the voltage difference between the common electrode and the pixel electrode provided in the color filter substrate to change the arrangement of the liquid crystal so that an image is displayed on the pixel.

FIG. 2 is a diagram illustrating an equivalent circuit of the liquid crystal panel of FIG. 1.

Referring to FIG. 2, a plurality of gate lines GL1 to GLn are arranged at regular intervals in a horizontal direction on the substrate, and a plurality of data lines DL1 to DLm are arranged at regular intervals in a vertical direction so that the gate lines GL1 are arranged. A plurality of pixels P are defined in the region where the -GLn and the data lines DL1 -DLm intersect. In addition, a switching element T is disposed in an area where the gate lines GL1 to GLn and the data lines DL1 to DLm cross each other to be electrically connected to the data lines DL1 to DLm and the gate lines GL1 to GLn. Is connected.

The pixel P is provided with a pixel electrode to apply a voltage of image information, and the color filter substrate is provided with a common electrode to apply a common voltage. An electric field is formed between the pixel electrode and the common electrode due to the voltage difference between the voltage of the image information and the common voltage. Since a constant gap exists between the pixel electrode and the common electrode, the capacitor serves as a capacitor to maintain an electric field for one frame. The capacitor between the pixel electrode and the common electrode is defined as a liquid crystal capacitor Cl.

In addition, since the space between the pixel electrodes overlapped at regular intervals and the gate lines GL1 to GLn serves as a storage capacitor Cs, the voltage of the image information applied through the pixel P11 is stored for one frame. Will be maintained.

As illustrated, the gate driver 130 is provided at one side of the liquid crystal display to sequentially supply scan signals Vg1 to Vgn to one side of each gate line GL1 to GLn. As such, the scan signals Vg1 to Vgn applied to one side of the gate lines GL1 to GLn are transmitted to the other side of the gate lines GL1 to GLn.

However, inherent resistance and capacitance components exist in all electrical devices that supply and process electrical signals, and similarly, resistance exists in electrical wirings that transmit electrical signals. Accordingly, as described above, the scan signals Vg1 to Vgn are supplied to one end of each gate line GL1 to GLn and transferred to the other side, and thus the resistance of the gate lines GL1 to GLn and the gate lines GL1 to GLn are increased. The scan signals Vg1 to Vgn are delayed and distorted due to the intrinsic resistance of various electrical elements electrically connected to GLn.

3 is a view illustrating a change in a scan signal transmitted through a gate line.

Referring to FIG. 3, the resistance component and the capacitance component present in the gate line are constituted by an equivalent circuit. In the equivalent circuit, the resistor component is connected to the resistor R, the capacitance component is connected to the capacitor C, and the resistor R and the capacitor C are connected in parallel with each other.

The gate line has inherent resistance depending on the fabrication material, which delays signal transmission and distorts the signal. In addition, since the pixel connected to the gate line acts as a capacitor, a resistance-capacitance delay (RC Delay) is generated by a combination of a resistance component and a capacitance component even when a scan signal Vg11 having a normal pulse shape is applied. The shape of the scan signal Vg11 is distorted, and a time delay is generated. This phenomenon is more prominent in the large-screen liquid crystal display devices, which are widely used in recent years. In order to realize an image on the large screen, the gate line must be lengthened to correspond to the screen length, so that the distance that the scan signal Vg11 moves is increased. As a result, distortion and delay of the scan signal Vg11 become more severe.

As described above, as the gate line lengthens due to the delay and distortion of the scan signal due to the resistance and capacitance components of the gate line, horizontal crosstalk in which the luminance of the displayed image in the left and right regions of the liquid crystal panel is different is different. ) May cause deterioration of image quality.

Accordingly, the present invention was devised to solve the conventional problems, and an object of the present invention is to divide a liquid crystal panel into a plurality of areas and apply scanning signals to the divided areas, thereby maximizing delay and distortion of the scanning signal. The present invention provides a liquid crystal display that can be suppressed to prevent deterioration of image quality.

As described above, a liquid crystal display device for achieving the object of the present invention includes a substrate divided into a first region and a second region, a plurality of data lines arranged in a longitudinal direction on the substrate, and substantially perpendicular to the data lines. And a gate line structure for applying an external signal to the pixels of the first region and the second region through different paths, and a thin film transistor disposed on the pixels.

4 is a plan view showing a liquid crystal display device according to the present invention.

Referring to FIG. 4, a liquid crystal display includes a liquid crystal panel 210 in which a first and second substrates facing each other are bonded to each other, and is divided into a plurality of regions, and a plurality of data lines arranged in a vertical direction at regular intervals. 215 and the first gate line 216a and the second gate line 216b that are spaced at regular intervals and are arranged in the horizontal direction and apply the scan signal Vg100 to the divided regions of the liquid crystal panel 210, respectively. It is configured to include.

The liquid crystal panel 210 is divided into a first panel area AREA1 and a second panel area AREA2. The first panel area AREA1 and the second panel area AREA2 divide the liquid crystal panel 210 in order to separately apply the scan signal Vg.

The data line 215 and the first and second gate lines 216a and 216b which are arranged in the vertical and horizontal directions on the liquid crystal panel 210 intersect each other and divide a plurality of regions, and the regions are divided into pixels P10. It is defined as The pixel P10 includes a switching element T10, a liquid crystal capacitor Cl, and a storage capacitor Cs.

A thin film transistor is usually applied to the switching element T10 and is electrically connected to the data line 215 and the first and second gate lines 216a and 216b.

A plurality of first gate lines 216a and a plurality of second gate lines 216b are connected to the gate driver 230. The first gate line 216a is electrically connected to the pixel P10 formed in the first panel area AREA1, and the second gate line 216b is connected to the pixel formed in the second panel area AREA2. It is electrically connected with P10). That is, the scan signal Vg output from the gate driver 230 is supplied to different panel regions through the first gate line 216a and the second gate line 216b.

A plurality of data lines 215 are connected to the data driver 220, and the plurality of data lines 215 are connected to the pixel P10 to apply image information to the pixel P10.

Conventionally, in the liquid crystal panel 210 having the pixels P10 arranged in a matrix form, one gate line corresponds to the pixel P10 in a row unit, and the scan signal Vg is applied to all the pixels P10. However, in the present invention, the scan signal Vg is applied to all the pixels P10 by matching two gate lines to the pixels P10 in a row unit. In other words, the pixel P10 in a row unit is shared by half so that each gate line applies the scan signal Vg. Therefore, the gate line applying the scan signal Vg to the pixel P10 in the row unit should receive the scan signal Vg output at the same timing from the gate driver 230.

Referring to the drawings, the first gate line 216a and the second gate line 216b are formed to correspond to each pixel P10 in a row unit, and the first gate line 216a is formed in the first panel area AREA1. Is connected only to the pixel P10 of the second gate line 216b, and only to the pixel P10 of the second panel area AREA2. In addition, the scan signal Vg output from the gate driver 230 is supplied to the first gate line 216a and the second gate line 216b corresponding to the pixels P10 in the same row, respectively, so that the first panel region is provided. Pixels P10 of 216a and pixels P10 of the second panel region 216b. In more detail, the first gate line 216a and the second gate line 216b are separately formed on the liquid crystal panel 210, but the first gate line 216a and the second gate corresponding to the same row. Since the line 216b is electrically connected through the contact hole, the first gate line 216a and the second gate line 216b corresponding to the same row simultaneously apply the scan signal output from the gate driver 230. Will receive.

The first gate line 216a needs to apply the scan signal Vg only to the first panel area AREA1 in which the liquid crystal panel 210 is divided, so that the scan signal Vg having less delay or distortion than the conventional gate line 216a is applied. It is possible to supply to the pixel P10 of the first panel area AREA1, and the second gate line 216b is not electrically connected to the pixel P10 of the first panel area 216a. Since only the second panel region 216b is electrically connected to the second panel region 216b, a scan signal is applied to the pixel P10 of the second panel region AREA2 without signal delay or distortion caused by the capacitance of the pixel P10 of the first panel region AREA1. (Vg) can be applied.

The scan signals Vg respectively applied to the first panel area AREA1 and the second panel area AREA2 are substantially applied to the switching element T10 provided in each pixel P10. The switching element T10 is turned on by the scan signal Vg, and receives the image information output from the data driver 220 and applies it to the pixel P10. In this case, the image information applied to the pixel P10 is applied to the pixel electrode (not shown) to apply an electric field to the liquid crystal layer together with the common electrode (not shown).

On the other hand, since the voltage of the image information is stored in the storage accumulator Cl provided in the pixel P10 while the scan signal Vg is applied, the scan signal Vg is next to the first and second gate lines 216a and 216b. ), The voltage of the image information is continuously applied to the pixel P10 to maintain the driving of the liquid crystal.

In FIG. 4, the first gate line 216a and the second gate line 216b are electrically connected to the gate driver 230 and respectively connected to the first panel area AREA1 and the second panel area AREA2. The first gate line 216a and the second gate line 216b are shown separately on the drawings in order to easily explain that they are electrically connected. However, in practice, the first gate line 216a and the second gate line 216b are formed to overlap on the substrate, as shown in FIG.

FIG. 5 is a cross-sectional view of a thin film transistor array substrate in enlarged view of portion I-I of FIG. 4.

In FIG. 5, only a thin film transistor array substrate on which a first gate line and a second gate line are formed is shown.

As shown in FIG. 4, the thin film transistor array substrate 201 is divided into a first panel area AREA1 and a second panel area AREA2, as shown in FIG. 4, and the first panel area AREA1 and the second panel area. The thin film transistor and the data line 215 are formed in AREA2, respectively. The first and second gate lines 216a and 216b have different structures in the first panel area AREA1 and the second panel area AREA2, respectively.

First, the thin film transistor includes a gate electrode 222 formed on the thin film transistor array substrate 201, a second insulating layer 232 formed on the gate electrode 222, and a second insulating layer 232. A semiconductor layer 224 formed on the semiconductor layer, an ohmic contact layer 226 formed on the semiconductor layer 224, and a source-drain electrode 228 formed on the ohmic contact layer 226. It is composed.

The second insulating layer 232 is formed on the entirety of the thin film transistor array substrate 201 and insulates the gate electrode 222 from the outside. The source-drain electrode 228 together with the gate electrode 222 constitutes three terminals of the thin film transistor.

Meanwhile, data lines 215 are formed on the second insulating layer 232 at regular intervals. After the data line 215 and the source-drain electrode 228 are formed, a passivation layer 234 is formed on the entirety of the thin film transistor array substrate 201, and corresponds to the drain electrode of the passivation layer 234. A contact hole is formed in the region to electrically connect the pixel electrode 230 and the drain electrode. The pixel electrode 230 forms an electric field with a common electrode provided on a color filter substrate (not shown) facing the thin film transistor array substrate 201 to control light transmittance of the liquid crystal layer.

As described above, the thin film transistor and the data line 215 are identically formed in the first and second panel regions AREA1 and AREA2, but the first gate line 216a and the second gate line 216b are different from each other. You have a structure.

In the case of the first panel area AREA1, the first gate line 216a is formed on the thin film transistor array substrate 201. The first gate line 216a is formed together in the same process as the gate electrode 222. A first insulating layer 221 is formed on the first gate line 216a. The first insulating layer 221 may be formed only on the first gate line 216a. The gate line 216a may be formed to surround the gate line 216a. The second gate line 216b is formed on the first insulating layer 221. That is, in the first panel area AREA1, the first gate line 216a and the second gate line 216b are formed together, and between the first gate line 216a and the second gate line 216b. The first insulating layer 221 is insulated from each other.

On the other hand, the second gate line 216b may be formed to deviate from the first gate line 216a, but in order to maximize the aperture ratio of the pixel as much as possible, the second gate line 216b may be replaced by the first gate line 216a. It would be desirable to form so as to overlap on).

Only the second gate line 216b is formed in the second panel area AREA2. The second gate line 216b is formed on the thin film transistor array substrate 201. Since the first gate line 216a is formed only in the first panel area AREA1, a short circuit between the first gate line 216a and the second gate line 216b is prevented in the second panel area AREA2. The first insulating layer 221 is also unnecessary. The second gate line 216b of the first panel area AREA1 and the second gate line 216b of the second panel area AREA2 are integrally formed. That is, after the first gate line 216a and the first insulating layer 221 are sequentially stacked in the first panel area AREA1, the second gate line 216b is disposed on the first insulating layer 221. While forming a single line to the second panel area AREA2.

The first gate line 216a and the second gate line 216b formed in the first panel area AREA1 must be electrically connected to each other to receive the same scan signal from the gate driver. As described above, the first gate line 216a and the second gate line 216b corresponding to the same pixel row are electrically connected and simultaneously receive a scan signal output from the gate driver to receive the first panel area AREA1. ) And a scan signal are applied to the second panel area AREA2, respectively.                     

In order to connect the first gate line 216a and the second gate line 216b, a contact hole is provided in the first insulating layer 221 provided between the first gate line 216a and the second gate line 216b. Is formed to electrically connect the first gate line 216a and the second gate line 216b through the contact hole. However, when the contact hole is formed in the pixel, the aperture ratio of the pixel may be lowered, so that the first gate line 216a and the second are formed by forming the contact hole outside the image display unit displaying the image by arranging the pixels. It may be desirable to connect the gate line 216b.

As described above, since the first gate line applies the scan signal only to the first panel region, the scan signal can be applied to the pixels of the first panel region without signal distortion and delay. In addition, since the second gate line is not electrically connected to the first panel region and is formed separately from the first gate line by an insulating layer, the second gate line is scanned in the pixel of the second panel region by minimizing signal distortion or delay. Signal can be applied. Accordingly, by applying the scanning signal to the liquid crystal panel by the first gate line and the second gate line, it is possible to prevent the degradation of the image quality of the image as much as possible.

As described above, the liquid crystal display according to the present invention divides the liquid crystal panel into a plurality of regions and applies scanning signals to the pixels of the divided regions through different gate lines, thereby minimizing signal distortion and delay. Can be supplied to the pixels of each divided area, so that the image quality of the image displayed on the liquid crystal panel can be improved.

Claims (11)

A substrate divided into a first region and a second region; A plurality of data lines arranged longitudinally on the substrate; A gate line structure arranged substantially perpendicular to the data line to define a plurality of pixels, and applying an external signal to the pixels of the first region and the second region through different paths; And And a thin film transistor arranged on the pixel. The thin film transistor of claim 1, wherein the thin film transistor A gate electrode formed on the substrate; A second insulating layer formed on the gate electrode; A semiconductor layer formed on the second insulating layer; An ohmic contact layer formed on the semiconductor layer; And And a source-drain electrode formed on the ohmic contact layer. 2. The gate line structure of claim 1, wherein the gate line structure of the first region A first gate line formed on the substrate; A first insulating layer formed on the first gate line; And And a second gate line formed on the first insulating layer. 4. The liquid crystal display device according to claim 3, wherein the first insulating layer is formed only on the first gate line. The liquid crystal display of claim 3, wherein the first insulating layer is formed to surround the first gate line. The gate line structure of claim 1, wherein the gate line structure of the second region And a third gate line formed on the substrate. The gate line structure of claim 1, wherein the gate line structure of the first region includes a first gate line formed on the substrate, a first insulating layer formed on the first gate line, and a second gate line formed on the first insulating layer. And the gate line structure of the second region comprises a third gate line formed on the substrate. 8. The liquid crystal display device according to claim 7, wherein the second gate line and the third gate line are integrally formed. 8. The liquid crystal display of claim 7, wherein the first gate line and the second gate line are electrically connected through a contact hole. The liquid crystal display of claim 9, wherein the contact hole is formed outside the pixel. The liquid crystal display of claim 1, further comprising a gate driver configured to apply the same scan signal to the pixels of the first region and the pixels of the second region through different paths of the gate line structure. .

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