CN113885260B

CN113885260B - Display panel

Info

Publication number: CN113885260B
Application number: CN202111163366.7A
Authority: CN
Inventors: 严允晟; 刘菁; 曲凯莉; 张琪; 梁楚尉
Original assignee: TCL Huaxing Photoelectric Technology Co Ltd
Current assignee: TCL Huaxing Photoelectric Technology Co Ltd
Priority date: 2021-09-30
Filing date: 2021-09-30
Publication date: 2023-02-07
Anticipated expiration: 2041-09-30
Also published as: JP2023546630A; KR102640064B1; US20240029681A1; WO2023050540A1; JP7464625B2; CN113885260A; KR20230047945A

Abstract

A display panel comprises a plurality of data lines, a plurality of scanning lines, a plurality of sharing line groups and a plurality of pixel units. Each of the sharing line groups comprises a first sharing line and a second sharing line. Each pixel unit comprises a first thin film transistor, a second thin film transistor and a shared thin film transistor. The first thin film transistor and the second thin film transistor are electrically connected with the same data line. The first thin film transistor, the second thin film transistor and the shared thin film transistor are electrically connected with the same scanning line. The shared thin film transistor is electrically connected with the second thin film transistor and the shared line set.

Description

Display panel

Technical Field

The invention relates to the technical field of display, in particular to a display panel.

Background

A Liquid Crystal Display (LCD) has the features of low power consumption, light weight, low driving voltage, and the like, and is one of the most widely used displays at present. The display region of the liquid crystal display generally includes a plurality of pixel regions. Each of the pixel regions is provided with a thin-film transistor (TFT) and a pixel electrode. The thin film transistor is used as a switching element and can drive the pixel electrode to control the electric field of each pixel area, thereby achieving the liquid crystal deflection control of the liquid crystal display. The liquid crystal display with the thin film transistor forms an active matrix liquid crystal display, and is suitable for the display requirements of large pictures, high resolution and multi-gray scale.

At present, the liquid crystal display is developed towards high contrast, no gray scale inversion, high brightness, high saturation, fast response, and wide viewing angle. Common wide-view techniques include: twisted Nematic (TN) liquid crystal plus wide-angle film, in-plane switching (IPS) liquid crystal display, fringe Field Switching (FFS) liquid crystal display, and multi-domain vertical alignment (MVA) liquid crystal display. In the multi-domain vertical alignment type lcd, the liquid crystal molecules in each pixel region can be aligned in multiple directions by an alignment pattern (alignment pattern), such as alignment protrusions (alignment protrusions) or slits (slits). The multi-domain vertical alignment liquid crystal display has a plurality of alignment domains (domains) in different directions, so that the display requirement of wide viewing angle can be achieved.

However, when a viewer views the same image as the multi-domain vertical alignment liquid crystal display at different viewing angles, the saturation of the image seen by the viewer may be different, so-called color shift (colorshift).

In order to improve the color shift problem, a display panel design is proposed in which the pixel unit of each pixel region has two different voltage regions. The design is mainly to arrange two pixel electrodes in the pixel unit, and enable the two pixel electrodes to have different voltages through different driving configurations.

Please refer to fig. 1, which is a graph of voltage ratios of two pixel electrodes of the pixel unit of the display panel at different gray levels according to the prior art. In order to meet the requirement of gamma (gamma) curve, the voltage ratio must show an upward trend in the curve a of different gray scale values, however, as can be seen from fig. 1, the voltage ratio shows a downward trend in the curve a of different gray scale values. Therefore, the design can reduce the light transmittance of the multi-domain vertical alignment liquid crystal display in high gray scale display.

Disclosure of Invention

The invention provides a display panel of a display, which can avoid the problem of color cast of the display. Furthermore, the display panel of the invention can increase the viewing angle of the display during low gray scale display and increase the light penetration rate of the display during high gray scale display.

The display panel of the invention comprises a plurality of data lines, a plurality of scanning lines, a plurality of sharing line groups and a plurality of pixel units. Each of the sharing line groups comprises a first sharing line and a second sharing line. Each pixel unit comprises a first thin film transistor, a second thin film transistor and a shared thin film transistor. The first thin film transistor and the second thin film transistor are electrically connected with the same data line. The first thin film transistor, the second thin film transistor and the shared thin film transistor are electrically connected with the same scanning line. The shared thin film transistor is electrically connected with the second thin film transistor and the shared line set.

In an embodiment, the first sharing lines of the sharing line groups are electrically connected, and the second sharing lines of the sharing line groups are electrically connected.

In an embodiment, the source of the first thin film transistor and the source of the second thin film transistor are electrically connected to the same data line, the gate of the first thin film transistor, the gate of the second thin film transistor and the gate of the shared thin film transistor are electrically connected to the same scan line, the source of the shared thin film transistor is electrically connected to the drain of the second thin film transistor, and the drain of the shared thin film transistor is electrically connected to one of the first shared line and the second shared line of the shared line group.

In one embodiment, in a row of the pixel units, the common thin film transistor of each of the pixel units is electrically connected to the same common line group.

In one embodiment, in a row of the pixel units, one of the common tfts of two adjacent pixel units is electrically connected to the first common line of the same common line group, and the other of the common tfts of two adjacent pixel units is electrically connected to the second common line of the same common line group.

In one embodiment, in a row of the pixel units, one of the common tfts of two adjacent pixel units is electrically connected to the first common line of one of the common line groups, and the other of the common tfts of the two adjacent pixel units is electrically connected to the second common line of the other of the common line groups.

In one embodiment, in a row of the pixel units, the common thin film transistor of each of the pixel units is electrically connected to the first common line of each of the common line groups; or in a row of the pixel units, the sharing thin film transistor of each pixel unit is electrically connected with the second sharing line of each sharing line group.

In an embodiment, each of the pixel units further includes a first pixel electrode and a second pixel electrode. The first pixel electrode is electrically connected with the first thin film transistor, and the second pixel electrode is electrically connected with the second thin film transistor.

In one embodiment, in a column of the pixel units, the first common line and the second common line of one of the common line groups are insulated and disposed in a middle area of the first pixel electrodes and the second pixel electrodes of the pixel units.

In an embodiment, in a row of the pixel units, the first common line and the second common line of one of the common line groups are disposed in a side region of the first pixel electrodes and the second pixel electrodes of the pixel units in an insulated manner.

The display panel of the invention avoids the color cast problem of the display by configuring the shared thin film transistor of each pixel unit and the first shared line and the second shared line of each shared line group, increases the visual angle of the display during low gray scale display, and increases the light penetration rate of the display during high gray scale display. Further, the display panel can also be applied to the display in the dot inversion mode and the display in the row inversion mode. In the display with frequent signal exchange, the display panel can reduce the effect of coupling capacitance generated by each sharing line group and the pixel unit, thereby achieving the target display effect, such as low color cast, wide viewing angle in the low gray scale display and high light penetration rate in the high gray scale display.

Drawings

Fig. 1 is a graph of voltage ratios of two pixel electrodes of each pixel unit of a display panel of the prior art at different gray levels.

Fig. 2 is a partial circuit diagram of a display panel according to the present invention.

Fig. 3 is a partial circuit diagram of a plurality of sharing line groups and a plurality of pixel units of the display panel according to the present invention.

Fig. 4 is another partial circuit diagram of the plurality of sharing line groups and the plurality of pixel units of the display panel according to the present invention.

Fig. 5 is a schematic partial structure diagram of the display panel according to the present invention.

Fig. 6 is another partial structural schematic diagram of the display panel according to the present invention.

Fig. 7 is a graph of ratios of voltages of the second pixel electrode and the first pixel electrode of each pixel unit of the display panel at different gray scale values.

FIG. 8 is a graph showing the variation of the voltages of the first common line and the second common line of each of the common line groups of the display panel according to the display frame number.

FIG. 9 is another variation of the voltages of the first common line and the second common line of each of the common line groups of the display panel according to the present invention with respect to the number of frames.

Detailed Description

In order to make the aforementioned and other objects, features and advantages of the present invention comprehensible, preferred embodiments accompanied with figures are described in detail below.

The invention provides a display panel of a display. Please refer to fig. 2, which is a partial circuit diagram of the display panel. The present invention takes the partial circuit diagram shown in fig. 2 as an example to illustrate the relative relationship of the elements in the display panel.

As shown in fig. 2, the display panel includes a plurality of data lines 100 (only one data line 100 is shown in the partial circuit diagram of fig. 2), a plurality of scan lines 200, and a plurality of pixel units 400. Each of the pixel units 400 of the display panel includes a first thin film transistor 410 and a second thin film transistor 420. In each pixel unit 400, the first thin film transistor 410 and the second thin film transistor 420 are electrically connected to the same data line 100, and the first thin film transistor 410 and the second thin film transistor 420 are electrically connected to the same scan line 200. The first thin film transistor 410 is further electrically connected to the first liquid crystal capacitor Clc1 and the first storage capacitor Cst1. The second thin film transistor 420 is further electrically connected to the second liquid crystal capacitor Clc2 and the first storage capacitor Cst2. The first liquid crystal capacitor Clc1 and the second liquid crystal capacitor Clc2 are electrically connected to a common electrode Ccom of the color film substrate. The first storage capacitor Cst1 and the second storage capacitor Cst2 are electrically connected to the common electrode Acom of the array substrate.

In order to achieve multi-domain display, each pixel unit 400 further includes a common thin film transistor 430. As shown in fig. 2, in each pixel unit 400, the common thin film transistor 430 is electrically connected to the second thin film transistor 420, and the first thin film transistor 410, the second thin film transistor 420 and the common thin film transistor 430 are electrically connected to the same scan line 200. When the display panel is in operation, the shared thin film transistor 430 can draw a portion of the voltage of the second thin film transistor 420, so that the first thin film transistor 410 and the second thin film transistor 420 of each pixel unit 400 can generate two different voltage regions. The two different voltage regions can drive the liquid crystal on each pixel unit 400 to perform multi-domain display, thereby increasing the viewing angle of the display during displaying.

However, in the conventional multi-domain display, a cross talk (crosstalk) phenomenon is easily generated in two different voltage regions generated in one pixel unit by sharing the thin film transistor, thereby affecting a display effect. Therefore, as shown in fig. 2, in the present invention, the display panel further includes a plurality of sharing line groups 300 (only one sharing line group 300 is shown in the local circuit diagram of fig. 2), and one sharing line group 300 is electrically connected to the sharing tft 430. By setting the plurality of shared line groups 300, the partial voltage of the second thin film transistor 420 is led out independently of the color film substrate common electrode Ccom and the array substrate common electrode Acom, and the display panel avoids a crosstalk phenomenon that may occur in the first thin film transistor 410 and the second thin film transistor 420.

Further, as shown in fig. 2, each of the set of sharing lines 300 includes a first sharing line 310 and a second sharing line 320. The source of the first thin film transistor 410 and the source of the second thin film transistor 420 are electrically connected to the same data line 100. The gate of the first thin film transistor 410, the gate of the second thin film transistor 420, and the gate of the shared thin film transistor 430 are electrically connected to the same scan line 200. The source of the shared thin film transistor 430 is electrically connected to the drain of the second thin film transistor 420. The drain of the common tft 430 is electrically connected to one of the first common line 310 and the second common line 320 of one of the common line groups 300.

When the display uses the dot inversion mode or the row inversion mode, two adjacent pixel units 400 have different polarities. If the two common tfts 430 in the two adjacent pixel units 400 with different polarities are electrically connected to the same common line of the common line set 300, a coupling capacitance effect will be generated, which may cause abnormal display of the display. Moreover, in the display device adopting the dot inversion mode or the row inversion mode, signals of the same common line electrically connected to the two common tfts 430 in the two adjacent pixel units 400 with different polarities are frequently exchanged, and a display delay of the display device is easily caused.

Therefore, the display panel of the present invention electrically connects the two adjacent pixel units 400 with different polarities to the first sharing line 310 and the second sharing line 320 of each sharing line group 300, respectively, so as to avoid the display abnormality and the display delay problem.

Please refer to fig. 3 and 4, which are two partial circuit diagrams of the plurality of shared line groups 300 and the plurality of pixel units 400 of the display panel according to the present invention. The present invention takes 4 × 4 pixel cells 400 and four shared line groups 300 shown in fig. 3 and 4 as examples, and describes the relative relationship between the pixel cells 400 and the shared line groups 300 in the display panel.

As shown in fig. 3 and 4, the first common lines 310 of the plurality of common line groups 300 are electrically connected, and the second common lines 320 of the plurality of common line groups 300 are electrically connected. In a row of the pixel units 400, the common thin film transistor 430 of each pixel unit 400 is electrically connected to the same common line group 300. In order to avoid the problems of abnormal display and display delay, in one row of the pixel units 400, one of the common tfts 430 of two adjacent pixel units 400 is electrically connected to the first common line 310 of the same common line group 300, and the other of the common tfts 430 of two adjacent pixel units 400 is electrically connected to the second common line 320 of the same common line group 300.

In one embodiment, one of the partial circuit diagrams of FIG. 3 is the display in the dot inversion mode. The first row of the pixel units 400 from the left is sequentially four pixel units 400 with positive polarity, negative polarity, positive polarity, and negative polarity from top to bottom. The pixel units 400 in the second row from the left are four pixel units 400 with negative polarity, positive polarity, negative polarity, and positive polarity in sequence from top to bottom. The third row from the left of the pixel units 400 is sequentially four pixel units 400 with positive polarity, negative polarity, positive polarity and negative polarity from top to bottom. The pixel units 400 in the fourth row from the left are four pixel units 400 with negative polarity, positive polarity, negative polarity, and positive polarity in sequence from top to bottom.

As shown in fig. 3, in a row of the pixel units 400, one of the tfts 430 of two adjacent pixel units 400 is electrically connected to the first common line 310 of one of the two sets of pixel units 300, and the other one of the tfts 430 of two adjacent pixel units 400 is electrically connected to the second common line 320 of the other set of pixel units 300.

In the present embodiment, in each row of the pixel units 400 or each column of the pixel units 400, one of the two adjacent pixel units 400 has a positive polarity, and the other of the two adjacent pixel units 400 has a negative polarity, thereby forming the dot inversion mode of the display. Moreover, the pixel units 400 with positive polarity are electrically connected through the first common lines 310 of the common line groups 300, and the pixel units 400 with negative polarity are electrically connected through the second common lines 320 of the common line groups 300. In this way, the pixel units 400 with the same polarity can be electrically connected to share the discharge voltage, thereby avoiding the display abnormality and the display delay.

In one embodiment, one of the partial circuit diagrams of FIG. 4 is the display in the row inversion mode. Each row of the pixel units 400 is sequentially four pixel units 400 with positive polarity, negative polarity, positive polarity and negative polarity from top to bottom.

As shown in fig. 4, in a row of the pixel units 400, the common thin film transistor 430 of each pixel unit 400 is electrically connected to the first common line 310 of each common line group 300; alternatively, in a row of the pixel units 400, the common thin film transistor 430 of each pixel unit 400 is electrically connected to the second common line 320 of each common line group 300.

In this embodiment, in each column of the pixel units 400, one of the two adjacent pixel units 400 has a positive polarity, the other of the two adjacent pixel units 400 has a negative polarity, and in the same row of the pixel units 400, each of the pixel units 400 has the same polarity. Thus constituting the display in the dot inversion mode. Moreover, the pixel units 400 with positive polarity are electrically connected through the first common lines 310 of the common line groups 300, and the pixel units 400 with negative polarity are electrically connected through the second common lines 320 of the common line groups 300. In this way, the pixel units 400 with the same polarity can be electrically connected to share the discharge voltage, thereby avoiding the display abnormality and the display delay.

Please refer to fig. 5 and 6, which are two partial structural diagrams of the display panel according to the present invention. The present invention takes one data line 100, one scan line 200, one wire-sharing group 300, and one pixel unit 400 shown in fig. 5 and 6 as examples to illustrate the structural relationship of the elements in the display panel.

As shown in fig. 5 and 6, each of the pixel units 400 further includes a first pixel electrode 440 and a second pixel electrode 450. The first pixel electrode 440 is electrically connected to the first thin film transistor 410, and the second pixel electrode 450 is electrically connected to the second thin film transistor 420.

It should be noted that fig. 5 and 6 only show one pixel unit 400 with positive polarity, i.e., the first common line 310 of one common line group 300 is electrically connected to one pixel unit 400. The structure of one of the pixel cells 400 of negative polarity may be analogized from the description below with respect to fig. 5 and 6.

In one embodiment, in a column of the pixel units 400, the first common lines 310 and the second common lines 320 of one of the common line groups 300 are insulated and disposed in the middle regions of the first pixel electrodes 440 and the second pixel electrodes 450 of the pixel units 400.

As shown in fig. 5, one data line 100 is disposed at one side of one pixel unit 400, and one scan line 200 is disposed between the first pixel electrode 440 and the second pixel electrode 450. The first sharing line 310 and the second sharing line 320 of one sharing line group 300 are arranged side by side in an insulated manner in the middle area of the first pixel electrode 440 and the second pixel electrode 450 of one pixel unit 400.

In the positive polarity pixel unit 400 of the present embodiment, the source of the first thin film transistor 410 and the source of the second thin film transistor 420 are electrically connected to one data line 100. The gate of the first thin film transistor 410, the gate of the second thin film transistor 420 and the gate of the shared thin film transistor 430 are electrically connected to one scan line 200. The source of the shared thin film transistor 430 is electrically connected to the drain of the second thin film transistor 420. The drain of the common tft 430 is electrically connected to the first common line 310 of one of the common line groups 300.

In one embodiment, in a row of the pixel units 400, the first common line 310 and the second common line 320 of one of the common line groups 300 are disposed at side regions of the first pixel electrodes 440 and the second pixel electrodes 450 of the pixel units 400 in an insulated manner.

As shown in fig. 6, one data line 100 is disposed in the middle region of one pixel unit 400, and one scan line 200 is disposed between the first pixel electrode 440 and the second pixel electrode 450. The first and

second sharing lines

310 and 320 of one sharing line group 300 are disposed on left and right sides of the first and

second pixel electrodes

440 and 450 of one pixel unit 400, respectively.

In the positive polarity pixel unit 400 of the present embodiment, the source of the first thin film transistor 410 and the source of the second thin film transistor 420 are electrically connected to one data line 100. The gate of the first thin film transistor 410, the gate of the second thin film transistor 420 and the gate of the shared thin film transistor 430 are electrically connected to one scan line 200. The source of the shared thin film transistor 430 is electrically connected to the drain of the second thin film transistor 420. The drain of the common thin film transistor 430 is electrically connected to the first common line 310 of one of the common line groups 300.

The embodiment shown in fig. 5 arranges the first shared line 310 and the second shared line 320 of one shared line group 300 side by side. The embodiment shown in fig. 6 separates the first shared line 310 and the second shared line 320 of one shared line group 300. Compared to the embodiment shown in fig. 5, since the embodiment shown in fig. 6 increases the distance between the first common line 310 electrically connected to the plurality of pixel units 400 with positive polarity and the second common line 320 electrically connected to the plurality of pixel units 400 with negative polarity, the first common line 310 and the second common line 320 are not easy to generate the effect of coupling capacitance, thereby achieving the target display effect.

Fig. 7 is a graph showing the ratio of the voltage of the second pixel electrode 450 to the voltage of the first pixel electrode 440 of each pixel unit 400 of the display panel of the invention at different gray levels. The display panel provided by the invention can be applied to the display adopting the dot inversion mode and the display adopting the line inversion mode. The graph shown in fig. 7 can be formed under cooperation of the plurality of pixel cells 400 having the positive polarity and the plurality of pixel cells 400 having the negative polarity.

As shown in fig. 7, the voltage ratios of the pixel units 400 with positive polarity show a rising trend in a curve b + of different gray-scale values, and the voltage ratios of the pixel units 400 with negative polarity also show a rising trend in a curve b-of different gray-scale values. Therefore, the ratio of the integrated voltages of the positive pixel units 400 and the negative pixel units 400 is in a rising trend in the curve b with different gray levels, which meets the requirement of a gamma (gamma) curve.

Therefore, the present invention increases the viewing angle of the display in low gray scale display and also increases the light transmittance of the display in high gray scale display by the plurality of first sharing lines 310 and the plurality of second sharing lines 320 of the plurality of sharing line groups 300.

Referring to fig. 8, a variation of the voltages of the first common line 310 and the second common line 320 of each of the common line groups 300 of the display panel according to the present invention corresponding to the number of display frames is shown.

In one embodiment, as shown in fig. 8, the common discharge voltage of the plurality of first common lines 310 corresponds to a variation line of the number of display frames as s1, and the common discharge voltage of the plurality of second common lines 320 corresponds to a variation line of the number of display frames as s2. In the variation line s1, the first common lines 310 have two common discharge potentials, i.e., 6V and 4V. In the variation line s2, the second common lines 320 have two common discharge potentials, i.e., 3V and 1V.

In the embodiment, due to the technical effects of the first common lines 310 and the second common lines 320 of the common line groups 300, the common discharge voltages generated by the first common lines 310 and the second common lines 320 can cancel each other out in each display frame, so that the display panel is not easy to generate the effect of coupling capacitance, thereby achieving the target display effect.

Please refer to fig. 9, which is another variation diagram of the display frame number corresponding to the voltages of the first common line 310 and the second common line 320 of each of the common line groups 300 of the display panel according to the invention.

In an embodiment, as shown in fig. 9, the common discharge voltage of the first common lines 310 corresponds to a change line of the display frame number is s1', and the common discharge voltage of the second common lines 320 corresponds to a change line of the display frame number is s2'. In the variation line s1, the first common lines 310 have common discharge potentials of 14V, 10V, 6V, and 4V. In the variation line s2, the plurality of second common lines 320 have a plurality of common discharge potentials, i.e., 14V, 10V, 6V, and 4V.

In the embodiment, due to the technical effects of the first common lines 310 and the second common lines 320 of the common line groups 300, the common discharge voltages generated by the first common lines 310 and the second common lines 320 can cancel each other out in each display frame, so that the display panel is not easy to generate the effect of coupling capacitance, thereby achieving the target display effect. In addition, compared to the embodiment shown in fig. 8, in the embodiment, the variation of the shared discharge voltage generated by the first common lines 310 and the second common lines 320 is smaller between each display frame, so that the ratio of the voltage of the second pixel electrode 450 to the voltage of the first pixel electrode 440 of each pixel unit 400 can be adjusted more greatly. By further adjusting the ratio, the display panel is less likely to generate the effect of coupling capacitance, thereby achieving the target display effect.

The display panel of the present invention avoids the color shift problem of the display, increases the viewing angle of the display in low gray scale display, and increases the light transmittance of the display in high gray scale display by configuring the common thin film transistor 430 of each pixel unit 400 and the first common line 310 and the second common line 320 of each common line group 300. Further, the display panel can also be applied to the display in the dot inversion mode and the display in the row inversion mode. In the display with frequent signal exchange, the display panel can reduce the effect of the coupling capacitance generated by each of the sharing line groups 300 and the pixel units 400, thereby achieving the target display effect, such as low color shift, wide viewing angle in the low gray scale display, and high light transmittance in the high gray scale display.

Claims

1. A display panel, comprising:

a plurality of data lines;

a plurality of scan lines;

a plurality of sharing line groups, each sharing line group comprising a first sharing line and a second sharing line; a plurality of first sharing lines of the plurality of sharing line groups are electrically connected, and a plurality of second sharing lines of the plurality of sharing line groups are electrically connected; and

a plurality of pixel units, each of the pixel units including a first thin film transistor, a second thin film transistor and a shared thin film transistor, the first thin film transistor and the second thin film transistor being electrically connected to the same data line, the first thin film transistor, the second thin film transistor and the shared thin film transistor being electrically connected to the same scan line, and the shared thin film transistor being electrically connected to the second thin film transistor and a shared line set;

the display panel is provided with a display frame number which is N, wherein N is greater than or equal to 4;

the first sharing lines are provided with a plurality of first sharing discharge potentials which are gradually reduced from a 1 st frame to a 4 th frame; the second sharing lines have a plurality of second sharing discharge potentials, and the second sharing discharge potentials are gradually increased from the 1 st frame to the 4 th frame.

2. The display panel according to claim 1, wherein the source of the first thin film transistor and the source of the second thin film transistor are electrically connected to the same data line, the gate of the first thin film transistor, the gate of the second thin film transistor and the gate of the shared thin film transistor are electrically connected to the same scan line, the source of the shared thin film transistor is electrically connected to the drain of the second thin film transistor, and the drain of the shared thin film transistor is electrically connected to one of the first shared line and the second shared line of one of the shared line groups.

3. The display panel according to claim 1, wherein in a row of the pixel units, the common thin film transistors of each of the pixel units are electrically connected to the same common line group.

4. The display panel according to claim 3, wherein in a row of the pixel units, one of the TFTs of two adjacent pixel units is electrically connected to the first common line of the same common line group, and the other of the TFTs of two adjacent pixel units is electrically connected to the second common line of the same common line group.

5. The display panel according to claim 3, wherein in a row of the pixel units, one of the TFTs of two adjacent pixel units is electrically connected to the first common line of one of the common line groups, and the other of the TFTs of two adjacent pixel units is electrically connected to the second common line of the other of the common line groups.

6. The display panel according to claim 3, wherein in a row of the pixel units, the common TFT of each of the pixel units is electrically connected to the first common line of each of the common line groups; or is

In a row of the pixel units, the common thin film transistor of each pixel unit is electrically connected to the second common line of each common line group.

7. The display panel of claim 1, wherein each pixel unit further comprises a first pixel electrode and a second pixel electrode, the first pixel electrode is electrically connected to the first thin film transistor, and the second pixel electrode is electrically connected to the second thin film transistor.

8. The display panel according to claim 7, wherein in a column of the pixel units, the first common line and the second common line of one of the common line groups are disposed in an insulating manner in a middle region of the first pixel electrodes and the second pixel electrodes of the pixel units.

9. The display panel according to claim 7, wherein in a column of the pixel units, the first common line and the second common line of one of the common line groups are disposed in a side region of the first pixel electrodes and the second pixel electrodes of the pixel units in an insulated manner.