KR20060028049A - Display device and method of driving thereof - Google Patents

Abstract

 Disclosed are a display device and a driving method thereof for improving visibility. The data processor converts the first image data input from the outside into second image data. The control unit controls the data processing unit to convert the first image data into the second image data having the first data format when the image mode selection signal is the general image mode, and the first image when the image mode selection signal is the high quality image mode. The data processor is controlled to convert the image data into second image data having a second data format. The display unit displays the second image data. Accordingly, the visibility problem caused by the asymmetric data format can be solved.

Visibility, asymmetrical data format, symmetrical data format

Description

Display device and driving method thereof {DISPLAY DEVICE AND METHOD OF DRIVING THEREOF}

1 is a schematic block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

FIG. 2 is a detailed block diagram of the data processor of FIG. 1.

3 is a flowchart for explaining an operation of the data processor.

4A and 4B are conceptual views illustrating a process of processing the first image data into second image data in the normal mode.

5A and 5B are conceptual views illustrating an example for describing a process of processing the first image data into second image data in the high quality mode.

6A and 6B are conceptual views illustrating another example for explaining a process of processing the first image data into second image data in the high quality mode.

7 is a schematic block diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

FIG. 8 is a detailed block diagram of the data driver shown in FIG. 7.

FIG. 9 is a conceptual view illustrating an effect of improving visibility by an S-shaped gamma curve applied to the gray voltage generator of FIG. 8.

<Description of Symbols for Main Parts of Drawings>

110: control unit 120: data processing unit                 

130: data driver 140: scan driver

150: driving voltage generation unit 160: display unit

The present invention relates to a display device, and more particularly, to a display device for improving visibility and a driving method thereof.

Recently, the liquid crystal display device has emerged as a next-generation display device due to its light weight, small size, high resolution, and low power, and full-colorization, compared to a CRT display device. It is widely used in small and medium devices such as portable terminals by using the advantages of the liquid crystal display.

The small- and medium-sized liquid crystal display device has fewer gradation levels than full-size liquid crystal display devices depending on the characteristics of the device such as light weight and small size. In general, the image data of a liquid crystal display device used in a portable terminal has 64 gradations and has a 16-bit interface.

As shown in Table 1 below, R (RED) and B (BLUE) data have 32 (5bit) gradation that increases by two levels, and G (GREEN) data has 64 (6bit) gradation that increases by one step. .                         

As described above, in the upper grayscales (0 to 31), the G data is 1 bit larger in the even grayscale, and in the lower grayscales (32 to 63), the G data is smaller by 1 bit. Therefore, in the upper gradation, R, G, and B data are combined with each other in even gradations, and gray colors are represented. In the remaining odd gradations, colors close to green are represented. On the other hand, in the lower grayscale, R, G, and B data are combined with each other in odd gray to represent gray color, and in the even grayscale, the color closer to magenta is represented as 1 bit more of the R and B data.

Therefore, the LCD having the asymmetric data format is not a problem when displaying a simple image. However, when displaying a high quality image such as a photograph, there is a problem that visibility is not good because there is a lot of image data of the same gradation level. In particular, it is even more so when the data of the dark series (BLACK) or the data of the light series (WHITE).

Accordingly, the technical problem of the present invention is to solve such a conventional problem, and an object of the present invention is to provide a display device for improving visibility.

Another object of the present invention is to provide a method of driving the display device.

A display device according to an embodiment for realizing the above object of the present invention includes a data processing unit, a control unit and a display unit. The data processor converts first image data input from the outside into second image data. The controller controls the data processor to convert the first image data into second image data having a first data format when the image mode selection signal is a general image mode, and wherein the image mode selection signal is a high quality image mode. In this case, the data processor is controlled to convert the first image data into second image data having a second data format. The display unit displays the second image data.

According to another aspect of the present invention, there is provided a method of driving a display device, the method including: receiving an image mode selection signal from an external device; Converting the first image data into second image data having a first data format when the image mode selection signal is a general image mode; and converting the second image data to a second image data having a first data format; Converting to second image data having a data format; And displaying the second image data. The first data format is characterized in that the most significant bit and the least significant bit of the second video data are the same as the most significant bit of the first video data, and the second data format is the least significant bit of the second video data. And the least significant bit of the first image data.

According to such a display device and a driving method thereof, visibility problems caused in an asymmetrical image data structure can be improved.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention.

1 is a schematic block diagram of a liquid crystal display according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the LCD includes a controller 110, a data processor 120, a data driver 130, a scan driver 140, a driving voltage generator 150, and a display 160.

The controller 110 controls the overall operation of the liquid crystal display, and generates a second control signal, a third control signal, and a fourth control signal based on a first control signal input from an external device (not shown). do. Specifically, the first control signal includes a main clock signal MCLK, a horizontal synchronization signal HSYNC, and a vertical synchronization signal VSYNC. The image data input from the external device may include a high quality mode (or a camera mode) in which high quality image data is input, and a mode selection signal for a normal mode in which high quality image data is input. The second control signal includes a horizontal start signal STH, an inversion signal RVS, a load signal TP, and the like that control the data driver 140. The third control signal includes a scan start signal STV, a clock signal CK, an output enable signal OE, etc. for controlling the scan driver 150, and the fourth control signal includes a driving voltage generator. The signal for controlling 160 includes a main clock signal MCLK, an inverted signal RVS, and the like.

The data processor 120 converts the first image data R, G, and B input from the external device into second image data R ', G', and B 'having a symmetrical data format.

For example, when the 18-bit first video data is input, the 18-bit first video data is converted into 15-bit second video data. That is, 6-bit first red, green, and blue data R, G, and B are converted into 5-bit second red, green, and blue data, R ', G', and B ', respectively. In the method of converting the 6-bit data into 5-bit data, the 6-bit data is converted into 5-bit data by setting the least significant bit LSB of the 6-bit data to the most significant bit MSB.

In addition, when 24 bit first video data is input, it converts to 18 bit second video data. That is, 8-bit first red, green, and blue data (R, G, B) is converted into 6-bit second red, green, and blue data (R ', G', B '). In this case, the 6-bit data is composed of the upper 5 bits and the least significant bit (LSB) of the 8-bit data. That is, the second red, green, and blue data R ', G', and B 'may be converted into mutually symmetric data formats to prevent unwanted colors from being displayed by the existing asymmetric data format.

The data driver 130 may receive a second control signal CONTL, a data signal DATA, and a reference gray voltage VREF, and may perform digital image data based on the signals CONTL, DATA, and VREF. The signal is converted into an analog image signal and output to the display unit 160. The data driver 130 may include a gray voltage generator that generates a gray voltage based on the reference gray voltage, and a digital-to-analog converter that converts digital image data into an analog image signal based on the gray voltage. Include. The gray voltage generator includes a distribution resistor to which a gamma curve is applied, and generates a gray voltage by distributing a reference gray voltage by the distribution resistor. The gray voltage generator may be embedded in the digital-analog converter.

The scan driver 140 generates a scan signal based on the third control signal and outputs the scan signal to the display unit 160.

The driving voltage generator 150 may adjust the scan voltages VON and VOFF 152, the common voltages VCOM and VST 154, the reference gray voltage VREF 156, and the like based on the fourth control signal. Occurs. The scan voltages VON and VOFF 152 are provided to the scan driver 150, and the common voltages VCOM and VST are provided to the liquid crystal capacitor CLC and the storage capacitor CST of the display unit 160. The reference gray voltage VREF is provided to the gray voltage generator of the data driver 130.

The display unit 160 has an array substrate, an upper substrate, and a liquid crystal layer interposed between the substrates. The array substrate has a plurality of data lines DL and a plurality of scan lines SL interconnected with the data lines DL and includes a plurality of unit pixels 161 defined by the data lines and the scan lines. Have The unit pixel 161 has sub pixels 161a, 161b, and 161c corresponding to the R, G, and B color pixels. The sub-pixel includes a switching element TFT, a liquid crystal capacitor CLC, and a storage capacitor CST, and a gate electrode of the switching element TFT is connected to a scan line, and a source electrode is connected to the data line. The drain electrode is connected to the pixel electrode which is the first electrode of the liquid crystal capacitor CLC. The storage capacitor CST is defined by the gate electrode and the sub pixel electrode. The upper substrate has R, G and B color filters for expressing color at a position corresponding to the pixel, and has a common electrode which is a second electrode of the liquid crystal capacitor CLC. The common voltages VCOM and VST are applied to the common electrodes of the liquid crystal capacitor CLC and the storage capacitor CST.

2 is a detailed block diagram of the data processor of FIG. 1, and FIG. 3 is a flowchart for describing an operation of the data processor.

1 to 3, the data processor 120 may input the first image data R, G, and B to have second image data R ', G', and B 'having a symmetrical data format. R, G, and B data processing units 121, 122, and 123 are converted into.

The R, G, and B data processing units 121, 122, and 123 use the first image data (R, G, B) is converted into the second image data R ', G', and B '.

Specifically, the controller 110 determines the image mode of the first image data input based on the image mode selection signal by the user's operation, and provides the control signal MODE_CONTL corresponding thereto to the data processor 120. do.

When the first image data is the general image data of 18 bits (step S211), the controller 110 provides the data processor 120 with a high signal, which is a control signal MODE_CONTR. Accordingly, the data processor 120 converts the 18-bit first image data R, G, and B into 15-bit second image data R ', G', and B '(step S213).

Therefore, 6-bit R, G, B, and data are converted into 5-bit R ', G', and B 'data. The R, G, and B data processing units 121, 122, and 123 convert the most significant bit MSB of the first image data R, G, and B to the least significant bit LSB of the second image data R ', B', and G '. Set 5) to generate 5bit data.

On the other hand, when the first image data (R, G, B) is 24-bit high-definition image data (step S221), the control unit 110 is a low signal that is a control signal MODE_CONTR to the data processing unit 120 To provide. Accordingly, the data processor 120 converts the first 24-bit first image data R, G, and B into 18-bit second image data R ', G', and B '(step S223).

Therefore, the 8-bit first red, green and blue data is converted into 6-bit second red, green and blue data. The R, G, and B data processing units 121, 122, and 123 use the upper 5 bits and the least significant bits LSB of the first image data R, G, and B to generate second image data R ', G', and B '. Create

4A and 4B are conceptual views illustrating a process of processing the first image data into second image data in the normal mode.

Referring to FIG. 4A, 6-bit first red, green, and blue data (R, G, B), that is, first image data (Normal data: R, G, B) of a normal mode are stored in the data processor 120. Is entered. Correspondingly, the data processor 120 determines that the data of the upper 5 bits of the first image data, “b (5), b (4), b (3), b (2), b (1)”, is as it is. Generates the upper 5 bits of the image data R ', G', and B '. Meanwhile, the most significant bit MSB: b (5) of the first image data R, G, and B is generated as the least significant bit LSB of the second image data R ', G'.B'.

As shown in FIG. 4B, 18-bit first image data R, G, and B are converted into 15-bit second image data R ', G', and B 'having a symmetrical data format. The second image data R ', G', and B 'may have a symmetrical data format to prevent unwanted color from being displayed due to the asymmetrical data format.

5A and 5B are conceptual views illustrating an example for describing a process of processing the first image data into second image data in the high quality mode.

Referring to FIG. 5A, 24 bits of R, G, B data, that is, first image data (Camera data: R, G, B) of a high quality mode are input to the data processor 120. Correspondingly, the data processor 120 determines that the data of the upper 5 bits of the first image data, “b (7), b (6), b (5), b (4), b (3)”, is as it is. The upper 5 bits of the image data R ', G', and B 'are output. The least significant bit LSB (b (0)) of the first image data R, G, and B is output as the least significant bit LSB of the second image data R ', G'.B'. .

As shown in FIG. 5B, the 24-bit first image data R, G, and B are converted into 18-bit second image data R ', G', and B 'having a symmetrical data format. The second image data R ', G', and B 'may have a symmetrical data format to prevent unwanted color from being displayed due to the asymmetrical data format.

6A and 6B are conceptual views illustrating another example for explaining a process of processing the first image data into second image data in the high quality mode.                     

Referring to FIG. 6A, 24-bit R, G, and B data and first image data (Camera data: R, G, and B) are input to the data processor 120. In response, the data processor 120 selects the upper 6 bit data "b (7), b (6), b (5), b (4), b (3), b (2)" of the first image data. 6 bit data of the second image data R ', G', and B 'are output. That is, the lower 2 bit data, b (1), and b (0) of the 8 bit first red, green, and blue data are cut out to generate 6 bit second red, green, and blue data.

As shown in FIG. 6B, first 24-bit first image data R, G, and B are converted into 18-bit second image data R ', G', and B 'having a symmetrical data format. The second image data R ', G', and B 'may have a symmetrical data format to prevent unwanted color from being displayed due to the asymmetrical data format.

In the above description, the data format conversion based on the image mode selection signal by the user's operation has been described as an example, but a person skilled in the art can determine the image mode based on the first image data input. That is, the controller regards the high quality image mode when the total number of bits of the first image data exceeds the threshold, and the normal image mode when the total number of bits of the first image data exceeds the threshold. Accordingly, the data processor is controlled to convert the first image data into second image data having a data format corresponding to the image mode.

7 is a schematic block diagram of a liquid crystal display according to another exemplary embodiment of the present invention.

Referring to FIG. 7, the liquid crystal display includes a controller 310, a data processor 320, a data driver 330, a scan driver 340, a driving voltage generator 350, and a display 360. The control unit 310 controls the overall operation of the liquid crystal display, and based on a first control signal input from an external device (not shown), a second control signal, a third control signal, and a third control signal. 4 Generate each control signal.

Specifically, the first control signal includes a main clock signal MCLK, a horizontal synchronization signal HSYNC, and a vertical synchronization signal VSYNC. The second control signal includes a horizontal start signal STH, an inversion signal RVS, a load signal TP, and the like that control the data driver 140. The third control signal includes a scan start signal STV, a clock signal CK, and an output enable signal OE for controlling the scan driver 350, and the fourth control signal includes a driving voltage generator ( The signal for controlling 360 includes a main clock signal MCLK, an inverted signal RVS, and the like.

The data processor 320 converts the first image data R, G, and B input from the external device into second image data R ', G', and B 'corresponding to a 16-bit data format.

Specifically, 6 bit first red and blue data R and B are converted into 5 bit second red and blue data R 'and B', respectively, and 6 bit first green data G is 6 bit still. The second green data G 'is output. In the method of converting the 6-bit data into 5-bit data, the 6-bit data is converted into 5-bit data by setting the least significant bit LSB of the 6-bit data to the most significant bit MSB.

The data driver 330 receives a second control signal CONTL, a data signal DATA, and a reference gray voltage VREF, and is based on the signals CONTL, DATA, and VREF. Is converted into an analog image signal and output to the display unit 360. The data driver 330 includes a divider resistor to which an S-shaped gamma curve is applied, and converts the second image data in digital form into an analog form based on the gray voltage generated by the divider resistor. Output as a video signal.

The scan driver 340 generates a scan signal based on the third control signal and outputs the scan signal to the display unit 360.

The driving voltage generator 350 may scan the scan voltages VON and VOFF 352, the common voltages VCOM and VST 354, the reference gray voltage VREF 356, and the like based on the fourth control signal. Occurs. The scan voltages VON and VOFF 352 are provided to the scan driver 340, and the common voltages VCOM and VST are provided to the liquid crystal capacitor CLC and the storage capacitor CST of the display unit 360. The reference gray voltage VREF is provided to the gray voltage generator of the data driver 330.

The display unit 360 has an array substrate, an upper substrate, and a liquid crystal layer interposed between the substrates. The array substrate has a plurality of data lines DL and a plurality of scan lines SL interconnected with the data lines DL, and includes a plurality of unit pixels 361 defined by the data lines and the scan lines. Have The unit pixel 361 has sub pixels 361a, 361b, and 361c corresponding to the R, G, and B color pixels. The sub pixel includes a switching element TFT, a liquid crystal capacitor CLC, and a storage capacitor CST.

FIG. 8 is a detailed block diagram of the data driver shown in FIG. 7.

Referring to FIG. 8, the data driver 330 includes a shift register 331, a data register 332, a line latch 333, a gray voltage generator 334, and a digital-to-analog converter 335. And an output buffer 336.

The shift register 331 outputs a latch pulse to the line latch 333 based on the second control signal provided from the controller 310.

The data register 332 line latches second image data, that is, second red, green, and blue data R ′, G ′, and B ′ sequentially input from the controller 310 based on the second control signal. When the latch pulse is input from the shift register 331, the second red, green, and blue data R ′, G ′, and B ′ are output to the line latch 333.

The line latch 333 latches the second red, green, and blue data R ', G', and B 'in line units. When the load signal TP which is the second control signal is input, the latched line data is output.

The gray voltage generator 334 has a distribution resistor to which an S-shaped gamma curve is applied. The reference gradation voltage VREF input by the distribution resistor is divided by the gradation voltage corresponding to the gradation level (for example, 64 gradations) and output.

The digital-analog converter 335 converts the digital image data output from the line latch 333 into an analog image signal based on the gray voltage and outputs the analog image signal. In addition, the polarity of the data signal is inverted based on the inversion signal REV.

The output buffer 336 amplifies an image signal converted into an analog form and outputs the amplified image signal to the display unit 360.

FIG. 9 is a conceptual view illustrating an effect of improving visibility by an S-shaped gamma curve applied to the gray voltage generator of FIG. 8.

Referring to Fig. 9, when the S-shaped gamma curve γs is applied, the interval Ld of the gradation level on the white side is narrow. On the other hand, the general gamma curve γ has a relatively wide interval Ld 'of the gradation level on the white side. By applying the S-shaped gamma curve γs, the difference in the gradation level on the white side that is most prominent is reduced to alleviate the change in color displayed on the white side.

Referring to Table 2, the magenta color appears as the second red and blue data R 'and B' are 1 bit larger than the second green data G 'toward the white side. Therefore, the magenta color is alleviated by reducing the gradation voltage difference corresponding to the gradation level on the white side. By using the S-shaped gamma curve as described above, the visibility problem occurring in the white side according to the asymmetric data format can be solved.

As described above, according to the present invention, the visibility problem caused by the asymmetrical data format can be solved by processing the image data into the symmetrical data format.

In addition, by processing the image data having an asymmetric data format by applying an S-shaped gamma curve, it is possible to solve the visibility problem on the white side caused by the asymmetric data format.

Although described above with reference to the embodiments, those skilled in the art can be variously modified and converted within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand.

Claims (14)

A data processor converting first image data input from the outside into second image data; When the image mode selection signal is a normal image mode, the data processor controls the data processing unit to convert the first image data into second image data having a first data format, and when the image mode selection signal is a high quality image mode, A controller configured to control the data processor to convert first image data into second image data having a second data format; And And a display unit for displaying the second image data. The display apparatus of claim 1, wherein the image mode selection signal is selected by a user's operation. The display apparatus of claim 1, wherein the image mode selection signal is selected based on the first image data. The method of claim 1, wherein when the first image data is a general image mode having 6 bits of R, G, and B data, And the data processor converts the 6-bit R, G, and B data into 5-bit R, G, and B data. The display device according to claim 4, wherein the data processor generates the 5-bit data in which the most significant bit is the same as the most significant bit of the 6 bit data and the least significant bit is the same as the most significant bit of the 6 bit data. . The method of claim 1, wherein when the first image data is a high quality image mode having R, G, and B data of 8 bits or more, And the data processor converts the R, G, B data of 8 bits or more into 6, R, G, B data. The display apparatus of claim 6, wherein the data processor generates the 6-bit data having the least significant bit equal to the least significant bit of the 8-bit or more data. The display device of claim 1, further comprising: a gray voltage generator which generates a reference gray voltage as a gray voltage corresponding to the gray level by applying an S-shaped gamma curve; And And a digital-to-analog converter for converting the second image data into an analog image signal based on the gray voltage and outputting the analog image signal to the display unit. The display apparatus of claim 8, wherein the data processor converts the first image data into the second image data having 5-bit R and B data and 6-bit G data. (a) inputting an image mode selection signal from the outside; (b) converting the first video data into second video data having a first data format when the video mode selection signal is a general video mode; and when the video mode selection signal is a high quality video mode, the second video data. Converting to second image data having a second data format; And and (c) displaying the second image data. The method of claim 10, wherein when the first image data is a general image mode having 6 bits of R, G, and B data, step (b) includes: And converting the 6-bit R, G, B data into 5-bit R, G, B data. 12. The method of claim 11, wherein the 5-bit data having the most significant bit and the least significant bit equal to the most significant bit of the 6 bit data is generated. The method of claim 10, wherein when the first image data is a high quality image mode having R, G, and B data of 8 bits or more, the step (b) includes: And converting the 8 or more bits of R, G, and B data into 6 bits of R, G, and B data. The method of claim 13, wherein the 6-bit data having the least significant bit equal to the least significant bit of the 8-bit or more data is generated.

Images