KR20060024805A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

A method for fabricating a semiconductor device comprising a step for forming a second conductivity type drift region having a low concentration region at least on one side in the channel length direction of the gate electrode by implanting impurity ions into a semiconductor substrate from four different directions at a specified injection angle, and a step for forming a second conductivity type high concentration region surrounded by a drift region except the low concentration region. According to the method, a semiconductor device having a drift region capable of fining can be fabricated without increasing the number of fabrication steps.

Description

Semiconductor device and manufacturing method therefor {SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a semiconductor device and a method of manufacturing the same. More specifically, the present invention relates to a high breakdown voltage semiconductor device which can be used, for example, as a power supply IC and a manufacturing method thereof.

Among semiconductor devices, typical high breakdown voltage semiconductor devices are used for power supply ICs, display device drivers, and the like. A schematic sectional view (conventional example 1) of a high breakdown voltage semiconductor device is shown in FIG. FIG. 3 shows the gate electrode 3, the first conductive drift region 6 having a second conductivity type and a low concentration, including just below the end thereof, and the first drift region 6, which is isolated from the gate electrode 3. Is a semiconductor device having a second conductivity type enclosed by a) and a high concentration source region 4 and drain region 5. Here, reference numeral 1 denotes a first conductive semiconductor substrate, reference numeral 2 denotes a gate insulating film, reference numeral 6A denotes a first drift region end, reference numeral 6B denotes a boundary between the drain region and the first drift region, and reference numeral 8 denotes an element. The isolation region, reference numeral 14 is an interlayer insulating film, reference numeral 15 is a drain electrode, reference numeral 16 is a source electrode, and reference numeral 17 is a first drift region length. The principle of high breakdown voltage in this conventional example 1 is demonstrated below.

In the prior art example 1, when a high voltage is applied to the drain region 5, a voltage drop is generated in the drift region 6 by depletion of the first drift region 6, so that the first voltage under the gate electrode 3 is reduced. By reducing the electric field at 6 A of one drift region end, high breakdown voltage is aimed at. That is, the density of the first drift region 6 is lowered to improve the breakdown voltage at the first drift region end 6A and to promote the voltage drop in the first drift region 6.

In addition, by overlapping the gate electrode 3 with the first drift region 6 just below the end, depletion is further promoted in the overlapping region due to the potential difference with the gate electrode 3, resulting in the drift region end 6A. Higher breakdown voltage is also achieved by further relieving the electric field.

As an improved type of the conventional example 1, a schematic sectional view of the semiconductor device of the conventional example 2 is shown in FIG.4 (d). This is the first electrode drift region 6 of the second conductivity type and low concentration that overlaps the gate electrode 3, including just below the end thereof, and the first drift region 6, which is isolated from the gate electrode 3. A semiconductor having a second drift region 7 adjacent to and a second conductivity type, high concentration source region 4 and drain region 5 isolated from the gate electrode 3 and surrounded by the second drift region 7. Device. The principle of high breakdown voltage in this conventional example 2 is demonstrated below.

In the conventional example 1 of FIG. 3, in order to improve the breakdown voltage at the first drift region end 6A, the concentration of the first drift region 6 is lowered to promote the voltage drop in the first drift region 6. Needs to be. On the other hand, in the boundary portion 6B of the drain region and the first drift region, since the voltage drop occurs due to the depletion of the first drift region 6, the electric field strength of the boundary portion 6B becomes high and the breakdown voltage decreases. Cause.

Therefore, in the conventional example 2, the 2nd drift region 7 is formed so that the drain region 5 may be enclosed as shown in FIG.4 (d), and the density | concentration of the 2nd drift region 7, By making it higher than the 1st drift region 6, the electric field of the boundary part 7B of a drain region and a 2nd drift region is alleviated, and the high breakdown voltage of the whole transistor is realized. In the figure, reference numeral 7A denotes a boundary between the first drift region and the second drift region.

Japanese Patent Application Laid-Open No. 61-180483 corresponds to this conventional example 2.

However, the high pressure-resistant technique has the problem of causing an increase in the process and limiting the miniaturization.

That is, in order to manufacture two drift regions having different concentrations as in the conventional example 2, as shown in FIGS. 4A and 4B, the drift region formation is separately performed using the photosensitive resist mask 10. It is necessary to perform impurity implantation (11, 12). This leads to an increase in the process.

In addition, when the second drift region is formed, the transistor characteristics may become unstable because the length of the first drift region 17 is changed by the alignment error with the already introduced first drift region. In order to suppress this, it is necessary to increase the design value to the first drift region length 17 to about five times the alignment error (when the alignment error in the manufacturing process is 0.2 µm, about 1 µm of the total drift length). As a result, there was a limit to micronization.

In the formation of the gate electrode, the overlapping width of the gate electrode and the drift region should be about twice the alignment error so that the gate electrode and the drift region are not separated by the alignment error of the gate electrode and the first drift region 6. There was a need. In the drawing, reference numeral 13 denotes impurity implantation for forming the source region and the drain region.

<Start of invention>

In view of the above-described problems, the inventor of the present invention has found a semiconductor device having a drift region which can be manufactured without increasing the number of steps, and which can be miniaturized, and a method of manufacturing the same.

Thus, according to the present invention, a sidewall spacer and a gate electrode are formed of a first conductive semiconductor substrate having an element isolation region, a gate electrode formed on the semiconductor substrate via a gate insulating film, and an insulating film arbitrarily formed on sidewalls of the gate electrode. A second conductivity type drift region having a low concentration region formed in a semiconductor substrate on at least one side of an end in the channel longitudinal direction of the second conductivity type high concentration region surrounded by a drift region except the low concentration region, and an interlayer formed on the entire surface of the semiconductor substrate An insulating film, a contact hole formed in a predetermined position, and a metal wiring;

There is provided a semiconductor device in which a drift region of the second conductivity type having a low concentration region is a region formed by ion implantation of impurities which have a predetermined implantation angle from four different directions.

Further, according to the present invention, a step of forming a gate electrode via a gate insulating film on a first conductive semiconductor substrate in which an element isolation region is formed, and optionally forming sidewall spacers made of an insulating film on sidewalls of the gate electrode The second conductivity type drift region having a low concentration region is provided on the semiconductor substrate on at least one side of the end portion of the channel electrode in the channel length direction by implantation of impurities which have a predetermined implantation angle from the four different directions. Forming a resist pattern, forming a high conductivity region of a second conductivity type surrounded by a drift region other than the low concentration region through the resist pattern, removing the resist pattern, and removing the interlayer insulating film on the entire surface of the semiconductor substrate. Forming a contact hole, forming a contact hole at a predetermined position, and There is provided a method of manufacturing a semiconductor device including a step of forming.

Further, according to the present invention, a step of forming a gate electrode via a gate insulating film on a first conductive semiconductor substrate in which an element isolation region is formed, and optionally forming sidewall spacers made of an insulating film on sidewalls of the gate electrode A process of etching a semiconductor substrate using a sidewall spacer as a mask and forming a groove in the process, the gate electrode and, if formed, a gate by ion implantation of impurities having a predetermined implantation angle from four different directions. Forming a second conductivity type drift region having a low concentration region in at least one side of the end of the electrode in the channel length direction; forming a resist pattern, and enclosing the drift region excluding the low concentration region through the resist pattern; This is the process of forming a high concentration region of the second conductivity type, and the resist A method of manufacturing a semiconductor device is provided, which includes removing a semiconductor pattern, forming an interlayer insulating film on the entire surface of the semiconductor substrate, and forming a contact hole at a predetermined location and forming a metal wiring.

1 (a) to 1 (c) are schematic cross sectional views showing a semiconductor device of First Embodiment during a manufacturing step;

2 (a) to 2 (c) are schematic cross sectional views showing the semiconductor device of Example 3 during a manufacturing step;

3 is a schematic cross-sectional view of a semiconductor device of Conventional Example 1. FIG.

4A to 4D are schematic cross-sectional views showing steps for manufacturing the semiconductor device of Conventional Example 2;

<Best mode for carrying out the invention>

In the present invention, in the impurity introduction step for forming the drift region after forming the gate electrode, impurity implantation for forming the drift region, which is usually performed at an incident angle of 0 ° with the wafer surface, is inclined (for example, 30 °). By changing the direction of introduction during the implantation, (1) impurity introduction is limited in the region immediately below the end of the gate electrode by the shadow of the gate electrode, so that the copper region becomes low, (2 ) And a drift region overlapping immediately below the end of the gate electrode formed by the impregnation of impurities immediately below the end of the gate electrode due to the oblique incidence.

Thereby, the process for forming the 1st drift region of the prior art example 2 becomes unnecessary. In addition, since the overlap width and the low concentration region length of the gate electrode and the drift region are determined by the incidence angle of impurity implantation and the thickness of the gate electrode, these values are stable, so that the semiconductor device can be miniaturized. Specifically, it can be made about 10 to 40% finer compared with the semiconductor device of the prior art example 2 of FIG.

Further, by selectively forming sidewall spacers made of insulating films on the sidewalls of the gate electrodes, the depth penetrating immediately below the ends of the gate electrodes due to the oblique incidence in the subsequent impurity introduction step for forming the drift region can be limited. Therefore, the overlap width of the gate electrode and the drift region can be reduced, and the semiconductor device can be made smaller.

In addition, by making the surface of the semiconductor substrate of the drift region into a groove shape with respect to the semiconductor surface immediately below the gate electrode, the sidewall portion of the groove adjacent immediately below the end of the gate electrode is the lowest, and then the drift region is removed from a portion of the groove bottom portion. You can do it at a low concentration. Therefore, the effective low concentration region length can be extended, and it is possible to achieve higher withstand voltage of the semiconductor device. Specifically, the pressure resistance can be 1.1 to 1.3 times higher than that of the semiconductor device of FIG. 1C.

In addition, when the voltage applied to the source region is low, the source region side can omit the drift region and form a high concentration source region adjacent immediately below the gate electrode, whereby miniaturization can be achieved.

The semiconductor substrate which can be used for this invention is not specifically limited, Well-known board | substrates, such as a silicon substrate and a silicon germanium substrate, can be used.

An element isolation region is formed in the semiconductor substrate. The element isolation region may be either a LOCOS isolation region or a trench isolation region.

The gate electrode is formed through a gate insulating film at a predetermined position on the semiconductor substrate in the region partitioned by the element isolation region. As a gate insulating film, a silicon oxide film, a silicon nitride film, a laminated body of these films, etc. are mentioned. Examples of the gate electrode include a metal film such as Al and Cu, a polysilicon film, a silicide film of silicon and a high melting point metal (for example, titanium and tungsten), a laminate of a polysilicon film and a silicide film (poly Side film). The gate insulating film can be formed by, for example, selecting a thermal oxidation method, a sputtering method or the like according to a material, and the gate electrode can be formed by selecting a CVD method, a vapor deposition method or the like according to a material, for example.

A sidewall spacer made of an insulating film (for example, silicon oxide film or silicon nitride film) may be formed on the sidewall of the gate electrode. The sidewall spacer can be formed by selecting a CVD method, a sputtering method, etc. according to a material.

In the case where the gate electrode and the gate electrode are formed, the grooves may be formed by dry or wet etching the semiconductor substrate using the sidewall spacer as a mask. The depth of the groove can be, for example, 0.1 to 0.5 mu m. The shape of the groove is not particularly limited, and examples thereof include a shape in which the wall surface of the groove is vertical, a shape in which the bottom of the groove is narrower than the upper surface, and a shape in which the bottom of the groove is wider than the upper surface.

The semiconductor substrate has a second conductivity type drift region having a low concentration region at the end of the channel electrode in the channel length direction by implanting impurities at a predetermined implantation angle from four different directions. It is formed in the drain region formation side of the. Although the injection angle changes with the characteristic of a desired semiconductor device, it can carry out by 30 degrees or more, for example, and can select it in the range of 30 degrees-70 degrees more specifically.

Here, the four different directions may have any relationship with each other as long as the drift region can be formed. In particular, the four directions are preferably directions in which one direction is parallel to the channel width direction, and the other three directions are directions having incidence angles of 90 °, 180 ° and 270 ° with respect to the one direction.

Further, a high concentration drain region of the second conductivity type is formed through the resist pattern and surrounded by the drift region except for the low concentration region. The source region may also be formed in the drift region. The source region may be formed alone so as to overlap the lower portion of the sidewall of the gate electrode.

In addition, an interlayer insulating film is provided on the entire surface of the semiconductor substrate, and contact holes and metal wirings are provided at predetermined locations. It does not specifically limit as an interlayer insulation film, Any well-known film, such as a silicon oxide film and an SOG film formed by a well-known method, can be used. In addition, the predetermined location where a contact hole is formed is mentioned above a source region, a drain region, a gate electrode. Examples of the metal wirings include Al films and Cu films.

EXAMPLE

EMBODIMENT OF THE INVENTION Hereinafter, the Example which concerns on the semiconductor device of this invention and its manufacturing method is demonstrated, showing a specific numerical value.

Example 1

FIG. 1C is a schematic cross-sectional view of the semiconductor device of Example 1. FIG.

The semiconductor substrate 1 of the first conductor type is, for example, P-type, and has a boron concentration of approximately 1 × 10 ¹⁵ / cm 3. An element isolation region 8 having a thickness of about 400 nm is provided on this substrate. For example, a gate insulating film 2 having a thickness of 40 nm and a gate electrode 3 made of a polyside having a thickness of 200 nm are formed, for example. The channel length of this gate electrode 3 is about 1 micrometer, and the sidewall spacer 23 which consists of an insulating film is selectively formed in the sidewall of a gate electrode, and the film thickness of a bottom part is 100 nm, for example.

In addition, a drift region 21 including just under the end of the gate electrode 3 and overlapping by about 0.1 μm by self matching is formed. The low concentration region length 22 of this drift region is about 0.2 micrometer, a density is 0.9x10 <^17> / cm <3>, and a junction depth is about 0.4 micrometer. In addition, the concentration of the drift region itself is 1.2 x 10 ¹⁷ / cm 3, and the junction depth is about 0.5 μm.

The distance between the gate electrode 3 and the drain region 5 is 1 탆.

The manufacturing method of the semiconductor device of FIG. 1 (c) is demonstrated with schematic sectional drawing which shows the manufacturing process of the semiconductor device of FIG. 1 (a)-(c).

1 (a), an element isolation region 8 is selectively formed on the semiconductor substrate 1, a gate insulating film 2 is formed next, and a gate electrode 3 is formed.

Optionally, sidewall spacers 23 made of an insulating film are formed on the sidewalls of the gate electrodes 3. The film thickness of the bottom part of the sidewall spacer 23 is adjusted by the overlap width of the gate electrode and the drift region 21 formed later.

On the surface of such a semiconductor substrate, for example, phosphorus is divided into four directions with an energy of about 180 keV and an injection angle of 45 °, and ion implantation is implanted at an implantation amount of about 7 × 10 ¹² / cm 2, and an impurity implantation for forming a drift region is performed. Is done. In Embodiment 1, of the four directions, two directions are parallel to the channel width direction and have directions different from each other by 180 °, and the other two directions are parallel to the channel length direction and have directions different from each other by 180 °. In addition, the adjustment of the overlapping width of the drift region 21 can select timely in an injection angle within the range of 30-70 degrees. At this time, the energy, the injection amount, and the injection angle determine the subsequent low concentration region length 22 and are adjusted according to the desired internal pressure.

At this time, according to FIG. 1A, the region adjacent to the gate electrode 3 is formed by the impurity gradient implantation 18 for forming the drift region and the impurity gradient implantation 19 for forming the drift region in the opposite direction. In the shadow of the gate electrode 20 is generated, the amount of impurities introduced into the region is limited.

In the case of this embodiment, since the same amount of impurities are introduced in four directions, the amount of impurities introduced into the region adjacent to the gate electrode 3 becomes the shadow 20 of the gate electrode only in one direction, and therefore the amount of impurities in this portion. Is about 3/4 of the total injection amount, and the width of the drift region is formed about 200 nm from the end of the gate electrode 3.

Thereafter, in FIG. 1B, annealing is performed at 800 ° C. for about 10 minutes in an N ₂ atmosphere to activate the drift region.

Next, by the photosensitive resist mask 10, for example, arsenic is impurity implanted 13 for drain / source region formation selectively at an implantation amount of 3 × 10 ¹⁵ / cm 2 at an energy of 40 keV.

Next, in FIG. 1C, an interlayer insulating film 14 is formed, for example, 900 nm, and a contact hole is drilled to form an electrode.

Thereafter, a high breakdown voltage transistor can be produced by a known method.

Example 2

This second embodiment is the same as the first embodiment except that the sidewall spacers are not formed. Since no spacer is formed, a finer semiconductor device can be obtained.

Example 3

FIG. 2C is a schematic cross-sectional view of the semiconductor device of Example 3. FIG.

The first conductor-type semiconductor substrate 1 is, for example, P-type, and has a boron concentration of approximately 1 × 10 ¹⁵ / cm 3. An element isolation region 8 having a thickness of about 400 nm is formed on the substrate, and then a gate insulating film 2 having a thickness of 40 nm, for example, and a gate electrode 3 made of a polyside having a thickness of 200 nm, for example, Formed. The channel length of the gate electrode 3 is about 1 mu m, and sidewall spacers 23 made of an insulating film are selectively formed on the sidewalls of the gate electrode, and the film thickness of the bottom portion is, for example, 100 nm.

In addition, a drift region 21 overlapping by about 0.1 mu m is formed by self matching, including just below the end of the gate electrode 3. This drift region 21 is formed in the side wall part and bottom part of the groove | channel with a depth of 0.2 micrometer. The low-concentration area length 22 of this drift region is about 0.6 micrometers in the side wall part and a part of bottom part, the density is 0.3x10 ¹⁷ / cm <3> in a side wall part, the junction depth is about 0.2 micrometer, and 0.9 in a bottom part. × 10 ¹⁷ / cm 3, and the bonding depth is about 0.4 μm. In addition, the concentration of the drift region itself is 1.2 x 10 ¹⁷ / cm 3, and the junction depth is about 0.5 μm.

The manufacturing method of the semiconductor device of FIG. 2 (c) is demonstrated by schematic sectional drawing which shows the manufacturing process of the semiconductor device of FIG. 2 (a)-(c).

2A, an element isolation region is selectively formed on the first conductivity type semiconductor substrate 1, a gate insulating film 2 is formed next, and a gate electrode 3 is formed. .

Optionally, sidewall spacers 23 made of an insulating film are formed on the sidewall of the gate electrode. The film thickness of the spacer is adjusted in accordance with the overlap width of the gate electrode and the drift region 21 formed later. After the sidewall spacer is formed, a region of the semiconductor substrate surface to be formed later with a drift region is processed into a groove shape having a depth of 0.2 µm, for example.

On the surface of such a semiconductor substrate, for example, phosphorus is divided into four directions with an energy of about 180 keV and an injection angle of 45 °, and ion implantation is implanted at an implantation amount of about 7 × 10 ¹² / cm 2, and an impurity implantation for forming a drift region is performed. Is done. In Embodiment 1, of the four directions, two directions are parallel to the channel width direction and have directions different from each other by 180 °, and the other two directions are parallel to the channel length direction and have directions different from each other by 180 °. At this time, the energy, the injection amount, and the angle of incidence determine the subsequent low concentration region length 22 and are adjusted according to the desired internal pressure.

At this time, according to FIG. 2A, the region adjacent to the gate electrode 3 is formed by the impurity gradient implantation 18 for forming the drift region and the impurity gradient implantation 19 for forming the drift region in the opposite direction. In the shadow of the gate electrode 20 is generated, the amount of impurities introduced into the region is limited.

In this embodiment, since the same amount of impurity is introduced in four directions, the impurity introduced into the sidewall region of the groove adjacent to the gate is 1/4 of the total injection amount because only one direction is ion implanted. Since the amount of impurity introduced into the low concentration region of the bottom part is shadowed in only one direction, 3/4 of the total amount of ion implanted is ion implanted.

In the case of 45 ° inclined implantation, the shadow 20 of the gate electrode is 400 nm which is the sum of the depths of the gate electrode and the silicon-etched groove, and the length of the drift layer is about 600 nm. In addition, the adjustment of the width | variety of the drift area | region 21 can select timely in an injection angle within 30-70 degrees.

Thereafter, in FIG. 2B, annealing is performed at 800 ° C. for about 10 minutes in an N ₂ atmosphere to activate the drift region.

Next, by the photosensitive resist mask 10, for example, arsenic is impurity implanted 13 for drain / source region formation selectively at an implantation amount of 3 × 10 ¹⁵ / cm 2 at an energy of 40 keV.

Next, in Fig. 2C, an interlayer insulating film 14 is formed, for example, 900 nm, a contact hole is formed, and an electrode is formed to form a high breakdown voltage transistor.

Example 4

Although all of the first to third embodiments described above are semiconductor devices having a structure capable of applying a high voltage to the source region, when the voltage to be applied to the source region is low, the drift region is omitted on the source region side. However, adjacent to just below it, a high concentration source region 4 can be formed.

According to the semiconductor device of the present invention, a process for forming the first drift region is unnecessary, and the overlapping and low concentration region length of the gate electrode and the drift region is determined by the incident angle of impurity implantation and the thickness of the gate electrode, The characteristic is stable, and further miniaturization can be achieved.

Claims (10)

A sidewall spacer comprising a first conductive semiconductor substrate having an element isolation region, a gate electrode formed on the semiconductor substrate via a gate insulating film, an insulating film arbitrarily formed on the sidewall of the gate electrode, and an end portion in the channel length direction of the gate electrode. A second conductivity type drift region having a low concentration region formed on at least one side of the semiconductor substrate, a high concentration region of the second conductivity type surrounded by a drift region other than the low concentration region, an interlayer insulating film formed on the entire surface of the semiconductor substrate, and formed at a predetermined location With contact holes and metal wiring, A semiconductor device in which the drift region of the second conductivity type having a low concentration region is a region formed by ion implantation of impurities which have a predetermined implantation angle from four different directions. The method of claim 1, The semiconductor device has a groove | channel formed by being etched using the gate electrode and the sidewall spacer as a mask, and the drift region and the high concentration region are formed in the groove when the semiconductor substrate is formed. The method of claim 1, A second conductivity type drift region having a low concentration region is formed on both sides of the channel length direction of the gate electrode, and a high concentration region of the second conductivity type is formed as a source region and a drain region in the drift region except the low concentration region. Semiconductor device. The method of claim 1, A semiconductor device having an injection angle of 30 to 70 degrees. The method of claim 1, The four different directions are semiconductor devices in which one direction is a direction parallel to the channel width direction and the other three directions are directions having incidence angles of 90 °, 180 ° and 270 ° with respect to the one direction. Forming a gate electrode via a gate insulating film on a first conductive semiconductor substrate in which an element isolation region is formed, and optionally forming a sidewall spacer made of an insulating film on the sidewall of the gate electrode; Forming a second conductivity type drift region having a low concentration region in at least one side of the semiconductor substrate at an end of the gate electrode in the channel length direction by ion implantation of impurities having a predetermined implantation angle from the direction; Forming a pattern, forming a second conductive high concentration region surrounded by a drift region other than the low concentration region through a resist pattern, removing a resist pattern, and forming an interlayer insulating film on the entire surface of the semiconductor substrate; Forming a contact hole at a predetermined location and forming a metal wiring; A method of manufacturing a semiconductor device. Forming a gate electrode via a gate insulating film on a first conductive semiconductor substrate having an element isolation region, optionally forming sidewall spacers made of an insulating film on sidewalls of the gate electrode, a gate electrode, and If formed, the semiconductor substrate is etched using the sidewall spacers as a mask to form the grooves, and the ion lengths of the impurity in which the impurity has a predetermined implantation angle from four different directions are used in the channel length direction of the gate electrode. Forming a second conductivity type drift region having a low concentration region in at least one side of the semiconductor substrate; forming a resist pattern; and enclosing the second conductivity type in a drift region other than the low concentration region through the resist pattern. Forming a high concentration region, removing a resist pattern, and A step of forming an interlayer insulating film over the entire surface of the substrate body, a method of manufacturing a semiconductor device including a step of forming a contact hole at a predetermined position, and forming a metal wiring. The method according to claim 6 or 7, The manufacturing method of the semiconductor device whose injection angle is 30-70 degrees. The method according to claim 6 or 7, A second conductivity type drift region having a low concentration region is formed in the semiconductor substrate on both sides of the end portion in the channel longitudinal direction of the gate electrode, and the second conductivity type high concentration region is formed in the drift region except for the low concentration region. The manufacturing method of a semiconductor device formed as a drain region. The method according to claim 6 or 7, One of four different directions is a direction parallel to the channel width direction, and the other three directions are directions having angles of incidence of 90 °, 180 ° and 270 ° with respect to the one direction. .

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