KR20060021063A - Wafer for performing electric die sorting test effectvely - Google Patents

Abstract

A wafer is provided that can effectively perform electrical property testing. Wafers capable of effectively conducting electrical property tests serve as a reference for semiconductor device dies on which semiconductor devices are formed and for electric die sorting (EDS) tests, and are a reference die that can be visually distinguished from semiconductor device dies by color differences. consist of.

Electrical Characteristic Testing, Reference Dies, Wafers

Description

Wafer for performing electric die sorting test effectvely

1 is a plan view schematically illustrating a wafer capable of effectively performing an electrical characteristic test according to an embodiment of the present invention.

2 is a cross-sectional view illustrating a semiconductor device die of a wafer capable of effectively performing an electrical characteristic test according to an embodiment of the present invention.

3 is a cross-sectional view illustrating a reference die of a wafer capable of effectively performing an electrical characteristic test according to an embodiment of the present invention.

<Description of symbols on the main parts of the drawings>

100: wafer 110: reference die

120: semiconductor element die 130: starting die

210, 310: silicon oxide film 220, 320: polyimide film

230: metal film

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer capable of effectively conducting electrical property tests. In particular, the present invention effectively conducts an electrical die sorting (EDS) in which a reference die is formed to visually distinguish the semiconductor device die from color differences. It is about the wafer which can be done.

In general, a semiconductor device performs an fabrication process of repeatedly forming a pattern set on a wafer to form a die having an integrated circuit, and then performs an electrical characteristics (EDS) test that measures electrical characteristics of the die formed on the wafer. Find the bad die through Then, an inking process of checking the defective die with ink is performed to display the die determined as the defective die in the electrical property test. After the inking process is completed, the wafer is manufactured by performing a back lap process, which is a process for thinning the thickness of the wafer, and then performing an assembly process of cutting and packaging each die.

In this electrical property test, electrical property tests are performed from the starting die on the wafer. Here, the starting die is input to the electrical property test apparatus and detects the position of the starting die to perform the electrical property test.

However, as the manufacturing technology of semiconductor devices advances, dies on a wafer become smaller and smaller, and as the number of dies formed on a wafer increases, an error occurs in finding a starting die that first starts a test in an electrical property test. As a result, electrical property tests may be performed at locations other than the designated starting die. This error can lead to mismatches between the positions of the normal and bad die resulting from the electrical property test and the actual and bad die on the wafer. In addition, the wafer that performs the back lap process after the inking process that displays the defect may have a thin wafer, and may cause cracks or cracks due to ink.

Accordingly, an aspect of the present invention is to provide a wafer capable of effectively conducting an electrical property test by accurately finding a starting die for performing the electrical property test.

Another object of the present invention is to provide a wafer capable of performing an assembly process with the result data of the electrical property test without performing the inking process, which is a process after the electrical property test.

Technical problem of the present invention is not limited to the above-mentioned technical problems, another technical problem that is not mentioned will be clearly understood by those skilled in the art from the following description.

The wafer capable of effectively performing the electrical property test according to an embodiment of the present invention for achieving the above technical problem, the semiconductor device die on which the semiconductor device is formed and the basis of the electrical die (Electric Die Sorting (EDS) test) And a reference die which can be visually distinguished from the semiconductor device die by color differences.

Specific details of other embodiments are included in the detailed description and the drawings.                     

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various forms. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view illustrating a wafer capable of effectively performing an electrical characteristic test according to an embodiment of the present invention.

As shown in FIG. 1, a wafer 100 capable of effectively performing electrical property tests includes a semiconductor device die 120 and a reference die 110.

The semiconductor device die 120 is a die on which a semiconductor device is formed on the wafer 100. The semiconductor device die 120 will be described with reference to FIG. 2. 2 is a cross-sectional view illustrating a semiconductor device die of a wafer 100 capable of effectively performing electrical property tests according to an embodiment of the present invention. The semiconductor device die 120 may be formed by repeatedly performing an oxidation process, a photo process, a chemical vapor deposition process, a sputtering process, an etching process, and the like, and an oxide film 210, a metal film 220, and a polyimide film 230. It includes.

The reference die 110 serves as a reference for the electric die sorting (EDS) test and may be visually distinguished from the semiconductor device die 120 by color differences. The reference die 110 is formed at the edge of the wafer 100. Reference die 110 is described in detail with reference to FIG. 3. 3 is a cross-sectional view illustrating a reference die of the wafer 100 capable of effectively performing electrical property tests in accordance with one embodiment of the present invention. This reference die 110 comprises a transparent film. The transparent film may be a silicon oxide film 310 or a polyimide film 320.

The wafer 100 capable of effectively performing the electrical property test according to an embodiment of the present invention is manufactured and used in the following manner.

The wafer 100 capable of effectively performing the electrical property test forms the silicon oxide film 210 of the semiconductor device die 120 and the silicon oxide film 310 of the reference die 110 on the wafer 100 through an oxidation process. do. A photoresist film is formed by coating a photoresist liquid on the wafer 100 on which the silicon oxide film 210 of the semiconductor device die 120 and the silicon oxide film 310 of the reference die 110 are formed. The integrated circuit pattern formed on the reticle is patterned through the light emitted through the reticle using a reticle having an integrated circuit pattern formed on the oxide film 230 of the semiconductor device die 120 of the wafer 100 on which the photoresist film is formed. However, the silicon oxide film 310 is formed at the position where the reference die 110 is to be formed, and the integrated circuit pattern is not patterned. Since the oxide film 310 of the reference die 110 may be formed together when the oxide film 210 of the semiconductor device die 120 is formed, a separate reticle is formed to form the silicon oxide film 310 of the reference die 110. There is no need to make it.                     

After the exposure process is completed, a development process of removing a portion where light is transferred onto the wafer 100 is performed. In the developing process, the photoresist film of the portion where the light is selectively transferred is removed by the integrated circuit pattern formed on the reticle, and the photoresist film formed on the reference die 110 is transferred to the entire photoresist film. All removed.

After the developing process, the above-described processes are repeatedly performed to manufacture a wafer 100 capable of effectively performing an electrical property test. In order to protect the semiconductor device die 120 and the reference die 110, the polyimide films 230 and 320 may be disposed on the metal film 220 of the semiconductor device die 120 and the silicon oxide film 310 of the reference die 110. ).

As shown in FIGS. 2 and 3, the semiconductor device die 120 and the reference die 110 of the wafer 100 manufactured as described above are stacked with a metal layer 230 such as aluminum on the reference die 110. Therefore, color difference occurs and it becomes visible with the naked eye. Since the silicon oxide film 210 and the polyimide film 220 according to an embodiment of the present invention are transparent materials, the color of the wafer 100 may be the color of the reference die 110.

The wafer 100 thus manufactured is loaded into the electrical property test apparatus for the electrical property test. To perform the electrical property test, the electrical property test apparatus finds a starting die 130, which is one of the semiconductor device dies 120 on the wafer 100. Although the position of the starting die 130 is input to the electrical property test apparatus, as the semiconductor device fabrication technology is developed, the size of the die on the wafer 100 may become smaller and smaller, thereby causing an error in finding the starting die 130.                     

However, when the reference die 110 is formed and the semiconductor die formed next to the reference die 110 is selected as the starting die 130, the starting die 130 may be easily found by the reference die 110. In addition, in the case of monitoring the electrical characteristics, the error check such as starting the electrical characteristics test in the starting die 130 may be performed due to the reference die 110 that may be visually distinguished from the semiconductor device die 120.

In addition, the resultant data from the electrical characteristics test can be input to the assembly process device so that the normal die and the bad die can be separated and packaged, thereby eliminating the inking process of marking the defective die. In addition, the reference die 110 during the assembly process can easily find the start die 130 of the electrical characteristic test, it is possible to easily distinguish between the normal die and the bad die to reduce the packaging time of the normal die.

As mentioned above, although the present invention has been described with reference to preferred embodiments, the present invention is not limited to the above embodiments, and various modifications may be made by those skilled in the art within the scope of the technical idea of the present invention.

As described above, according to the present invention, the wafer capable of effectively performing the electrical property test includes a reference die which can be visually distinguished from the semiconductor device die by color difference, thereby starting the electrical property test by the reference die in the electrical property test for the first time. The process of accurately finding the starting die and proceeding the process eliminates the problem of performing the electrical characteristic test off the starting die input to the electrical characteristic test device, and saves the time to find the starting die, thereby reducing the electrical characteristic test execution time. .

In addition, since the assembly process can be performed as a result of the electrical property test, there is no need for the inking process, thereby saving the time required for fixing the inking. As a result of the electrical property test, the reference die makes it easy to find the starting die and effectively package the normal die during the assembly process, which increases productivity and saves time.

Claims (4)

A semiconductor element die in which a semiconductor element is formed; An electric die sorting (EDS) test standard, and a wafer capable of effectively performing an electrical property test including a reference die which can be visually distinguished from the semiconductor device die by color difference. The method of claim 1, Wherein the reference die is capable of effectively performing electrical property tests formed at the edge of the wafer. The method of claim 1, The reference die is a wafer capable of effectively performing an electrical property test comprising a transparent film. The method of claim 3, wherein The transparent film is a silicon oxide film or a polyimide (Polyimide) wafer that can effectively perform the electrical characteristics test.

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