KR20060019858A - Plasma display device and driving method of plasma display panel - Google Patents

Abstract

In the driving method of the plasma display panel according to the present invention, a sustain discharge pulse in which only the scan electrodes alternately have a positive voltage and a negative voltage in the sustain period is applied. When the negative voltage is applied to the scan electrode, the voltage of the sustain electrode is biased to the positive voltage. This reduces the circuit cost of the plasma display device because a power recovery circuit for recovering and reusing reactive power in addition to the power for applying the sustain discharge pulse is required only in the scan electrode driver for applying the drive voltage to the scan electrodes in the sustain period. . In the sustain period, when positive voltage is applied to the scan electrode, the anion formed on the sustain electrode moves only to the scan electrode, and thus discharge occurs well. However, when a negative voltage is applied to the scan electrode, the negative electrode was formed on the scan electrode. Since negative ions are dispersed and moved between the sustain electrode and the address electrode, low discharge may occur. However, when a negative voltage is applied to the scan electrode in the sustain period as in the present invention, when the voltage of the sustain electrode is biased to a positive voltage, low discharge is prevented by increasing the voltage difference between the scan electrode and the sustain electrode.

PDP, integrated board, impedance, electrode, negative ion, sustain discharge pulse, sustain period

Description

Plasma display device and plasma display panel driving method {PLASMA DISPLAY DEVICE AND DRIVING METHOD OF PLASMA DISPLAY PANEL}

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

2 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention.

3 is a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention.

The present invention relates to a method of driving a plasma display panel and a plasma display device.

A plasma display panel is a display panel that displays characters or images by using plasma generated by gas discharge, and tens to millions or more pixels (discharge cells) are arranged in a matrix form according to their size. The plasma display panel is classified into a direct current type and an alternating current type according to a shape of a driving voltage waveform applied and a structure of a discharge cell.                         

In the DC plasma display panel, since the electrode is exposed to the discharge space as it is, the current flows in the discharge space while the voltage is applied, and for this purpose, a resistance for limiting the current must be made. On the other hand, in the AC plasma display panel, since the electrode covers the dielectric layer, the current is limited by the formation of a natural capacitance component, and the life is longer than that of the DC type since the electrode is protected from the impact of ions during discharge.

In general, an AC plasma display panel is driven by dividing one frame into a plurality of subfields, and each subfield includes a reset period, an address period, and a sustain period.

The reset period is a period of initializing the state of each cell in order to perform an addressing operation smoothly on the cell, and the address period selects a wall charge on a cell (addressed cell) that is turned on by selecting a cell that is turned on and a cell that is not turned on. This is the period during which the stacking operation is performed. The sustain period is a period in which a discharge for actually displaying an image on a cell to be turned on is performed.

To perform this operation, sustain discharge pulses are applied to the scan electrodes and sustain electrodes alternately in the sustain period, and the reset waveform and the scan waveform are applied to the scan electrodes in the reset period and the address period. Therefore, the scan driving board for driving the scan electrode and the sustain driving board for driving the sustain electrode are separately present.

Since the discharge space between the scan electrode and the sustain electrode, the surface where the address electrode is formed, and the surface where the scan and sustain electrode are formed acts as a capacitive load (hereinafter referred to as a panel capacitor), capacitance exists in the panel. Therefore, in order to apply sustain discharge pulses alternately to the scan electrodes and sustain electrodes, reactive power is required in addition to the power for sustain discharge. The sustain discharge driving circuit of the plasma display panel generally includes a power recovery circuit for recovering and reusing reactive power. The power recovery circuit is a method of recovering and reusing reactive power by using a resonance of a capacitive load and an inductor, and there are circuits proposed by L.F.Weber (US Pat. Nos. 4,866,349 and 5,081,400) as such power recovery circuits.

 Therefore, in order to apply the sustain discharge pulse to the scan electrodes and the sustain electrodes alternately, a power recovery circuit is required for each of the scan drive board and the sustain drive board, which increases the overall circuit price and increases the unit price of the plasma display device. .

In order to solve this problem, Korean Laid-Open Patent Publication No. 2003-90370 applies a sustain discharge pulse alternately having a Vs voltage and a -Vs voltage only in the scan electrode driver. In the sustain period, when the Vs voltage is applied to the Y electrode, since the Y electrode actually acts as an anode, negative ions formed on the X electrode move only to the Y electrode, so that sufficient negative ions are supplied to the Y electrode to discharge the charge. It happens well. However, when the -Vs voltage is applied to the Y electrode, since the X electrode and the A electrode actually act as an anode, negative ions formed in the Y electrode are dispersed and moved between the X electrode and the A electrode. If the negative ions are not supplied sufficiently, the discharge may not occur well or the discharge may occur weakly, resulting in low discharge.

 An object of the present invention is to provide a plasma display device capable of preventing low discharge in a sustain period.

In addition, the present invention provides a plasma display device having an integrated board which can reduce the unit cost of the plasma display device and drive the scan electrode and the sustain electrode. Another object of the present invention is to provide a driving waveform suitable for an integrated board.

According to an aspect of the present invention, a frame is formed in a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode. A method of driving by dividing into a plurality of subfields is provided. The driving method includes alternately applying a positive first voltage and a negative second voltage to the first electrode in the sustain period, and applying the second voltage to the first electrode. Biasing the voltage of with a positive voltage.

In this case, in the address period, the method may include applying a scan pulse to the first electrode to be selected while biasing the plurality of first electrodes with a third voltage, wherein the bias voltage of the second electrode is It may be the same voltage as the third voltage.

The method may include applying a third voltage and a fourth voltage to the selected first electrode and the third electrode, respectively, in the address period, wherein the bias voltage of the second electrode is the same as that of the fourth voltage. Can be.                     

In this driving method, the second electrode may be biased to the fifth voltage in the reset period and the address period, and the fifth voltage may be the ground voltage.

According to another feature of the present invention, a plasma display panel includes a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode. A plasma display device includes a driving circuit configured to apply a driving voltage for displaying an image to the first to third electrodes by the plasma display panel. At this time, the driving circuit alternately applies a positive first voltage and a negative second voltage to the first electrode in the sustain period, and the first when the first voltage is applied to the first electrode. The voltage difference between the first electrode and the second electrode when the second voltage is applied to the first electrode is set larger than the voltage difference between the first electrode and the second electrode.

The driving circuit applies a ground voltage to the second electrode when the first voltage is applied to the first electrode, and applies the ground voltage to the second electrode when the second voltage is applied to the first electrode. A positive voltage lower than 1 voltage can be applied.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention. Like parts are designated by like reference numerals throughout the specification.

In addition, the wall charge referred to in the present invention refers to a charge formed close to each electrode on the wall of the cell (eg, the dielectric layer). And the wall charge is not actually in contact with the electrode itself, but is described here as "formed", "accumulated" or "stacked" on the electrode. In addition, the wall voltage refers to the potential difference formed in the wall of the cell by the wall charge.

A method of driving a plasma display panel and a plasma display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

A method of driving a plasma display panel and a plasma display device according to an exemplary embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

First, a schematic structure of a plasma display device according to an exemplary embodiment of the present invention will be described in detail with reference to FIG. 2.

1 is a diagram illustrating a plasma display device according to an exemplary embodiment of the present invention.

As shown in FIG. 1, a plasma display device according to an exemplary embodiment of the present invention includes a plasma display panel 100, a controller 200, an address electrode driver 300, a sustain electrode driver 400, and a scan electrode driver 500. It includes.

The plasma display panel 100 includes a plurality of address electrodes A1 to Am extending in the column direction, and a plurality of sustain electrodes X1 to Xn and scan electrodes Y1 to Yn extending in pairs in the row direction. Include. The X electrodes X1 to Xn are formed corresponding to the respective Y electrodes Y1 to Yn, and generally have one end connected in common to each other. The plasma display panel 100 includes a substrate (not shown) on which the sustain and scan electrodes X1 to Xn and Y1 to Yn are arranged, and a substrate (not shown) on which the address electrodes A1 to Am are arranged. The two substrates are disposed to face each other with the discharge space therebetween so that the scan electrodes Y1 to Yn and the address electrodes A1 to Am and the sustain electrodes X1 to Xn and the address electrodes A1 to Am are orthogonal to each other. At this time, the discharge space at the intersection of the address electrodes A1 to Am and the sustain and scan electrodes X1 to Xn and Y1 to Yn forms a discharge cell.

The controller 200 receives an image signal from the outside and outputs an address driving control signal, a sustain electrode X driving control signal, and a scan electrode Y driving control signal. The controller 200 divides and drives one frame into a plurality of subfields, and each subfield is composed of a reset period, an address period, and a sustain period.

The address electrode driver 300 receives an address driving control signal from the controller 200 and applies a display data signal for selecting a discharge cell to be displayed to each address electrode.

The sustain electrode driver 400 receives the sustain electrode X driving control signal from the controller 200 and applies a driving voltage to the sustain electrode X.

The scan electrode driver 500 receives the scan electrode Y driving control signal from the controller 200 and applies a driving voltage to the scan electrode Y.

Hereinafter, a driving waveform applied to the address electrodes A1 to Am, the sustain electrodes X1 to Xn, and the scan electrodes Y1 to Yn in each subfield will be described with reference to FIG. 2. And a discharge cell formed by one address electrode (hereinafter referred to as "A electrode"), a sustain electrode (hereinafter referred to as "X electrode"), and a scan electrode (hereinafter referred to as "Y electrode") below. The explanation is based on the following. In addition, the wall charges mentioned below refer to charges that are formed on the walls of the discharge cells (eg, dielectric layers) close to each electrode and accumulate in the electrodes. This wall charge is not actually in contact with the electrode itself, but here the wall charge is described as "formed", "accumulated" or "stacked" on the electrode. In addition, a wall voltage refers to the potential difference formed in the wall of a discharge cell by wall charge.

2 is a driving waveform diagram of a plasma display panel according to a first exemplary embodiment of the present invention.

As shown in Fig. 2, in the rising period of the reset period, the Y electrode is increased from the Vs voltage to the Vset voltage while the X electrode is kept at 0V. In FIG. 2, the voltage of the Y electrode is shown to increase in the form of a lamp. As the voltage of the Y electrode increases, a weak discharge (hereinafter referred to as "weak discharge") occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode, and a negative wall charge is formed on the Y electrode. Positive wall charges are formed on the X and A electrodes. When the voltage of the electrode gradually changes as shown in FIG. 2, a weak discharge occurs in the cell, and the wall charge is formed so that the sum of the voltage applied from the outside and the wall voltage of the cell maintains the discharge start voltage state. This principle is disclosed in US Pat. No. 5,745,086 to Weber. In the reset period, since the state of all cells must be initialized, the voltage Vset is high enough to cause a discharge in the cells of all conditions. In addition, the Vs voltage is generally a voltage and a high voltage applied to the Y electrode in the sustain period, and a voltage lower than the discharge start voltage between the Y electrode and the X electrode.

In the falling period of the reset period, the X electrode is reduced from the Vs voltage to the Vnf voltage while the X electrode is maintained at the Ve voltage. While the voltage of the Y electrode decreases, a weak discharge occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode, so that the negative wall charges formed on the Y electrode and the positive wall charges formed on the X electrode and the A electrode Erased. In general, the magnitude of the Vnf voltage is set near the discharge start voltage between the Y electrode and the X electrode. As a result, the wall voltage between the Y electrode and the X electrode becomes almost 0 V, whereby a cell that does not have an address discharge in the address period can be prevented from being erroneously discharged in the sustain period. Since the A electrode is maintained at the reference voltage, the wall voltage between the Y electrode and the A electrode is determined by the level of the Vnf voltage.

In the address period, in order to select a cell to be turned on, a scan pulse having a VscL voltage and an address pulse having a Va voltage are applied to the Y and A electrodes while maintaining the voltage of the X electrode at a Ve voltage. The non-selected Y electrode biases the VscH voltage higher than the VscL voltage, and applies a reference voltage to the A electrode of the cell that is not turned on. At this time, the VscL voltage is called a scan voltage, and the VscH voltage is also called a non-scan voltage. In order to perform such an operation, the scan electrode driver 500 selects the Y electrode to which the scan pulse of VscL is to be applied among the Y electrodes Y1 to Yn, and for example, the Y electrodes in the order arranged in the vertical direction in a single drive. Can be selected. In addition, when one Y electrode is selected, the address electrode driver 300 selects a cell to which an address pulse of Va voltage is applied among the A electrodes A1 to Am passing through the cell formed by the corresponding Y electrode.                     

Specifically, first, a scan pulse of VscL voltage is applied to the Y electrode of the first row, and an address pulse of Va voltage is applied to the A electrode located in the cell to be turned on in the first row. Then, a discharge occurs between the Y electrode of the first row and the A electrode to which the Va voltage is applied, thereby forming a positive wall charge on the Y electrode and a negative wall charge on the A and X electrodes, respectively. As a result, the wall voltage Vwxy is formed between the Y electrode and the X electrode so that the potential of the Y electrode is high with respect to the potential of the X electrode. Subsequently, while applying the scan pulse of the VscL voltage to the Y electrode of the second row, an address pulse of Va voltage is applied to the A electrode located in the cell to be displayed in the second row. Then, as described above, an address discharge occurs in the cell formed by the A electrode to which the Va voltage is applied and the Y electrode of the second row, thereby forming wall charge as described above. Similarly, wall pulses are formed by applying an address pulse of Va voltage to the A electrode positioned in the cell to be turned on while sequentially applying the scan pulse of the VscL voltage to the Y electrodes of the remaining rows.

Subsequently, in the sustain period, pulses having a voltage of Vs and a voltage of -Vs are alternately applied to the Y electrode. When the -Vs voltage is applied to the Y electrode in the sustain period, the voltage of the X electrode is biased with a positive voltage (Va voltage in FIG. 2). Then, if a wall voltage is formed between the Y electrode and the X electrode by the address discharge in the address period, the discharge is caused at the Y electrode and the X electrode by the wall voltage and the Vs voltage, the wall voltage and the -Vs voltage, and the Vs1 voltage. Happens. The process of alternately applying the Vs voltage and the -Vs voltage to the Y electrode is repeated the number of times corresponding to the weight indicated by the corresponding subfield.

At this time, the bias voltage of the X electrode may be a voltage of about 1/4 to 3/4 of the Vs voltage, and to select a cell to be turned on in the VscH voltage or the address period applied to the Y electrode which is not selected in the address period. Va voltage applied to the A electrode may be used. In this case, when the VscH voltage or the Vs voltage is used as the bias voltage of the X electrode, an additional power source may not be used. In this case, when the -Vs voltage is applied to the Y electrode, the voltage difference (| -Vs-Va |) between the Y electrode and the X electrode becomes large so that negative ions move to the X electrode side, thereby preventing low discharge.

In addition, since the Vs voltage and the -Vs voltage are applied only to the Y electrode during the sustain period, the power recovery circuit is needed only on the scan driving board, thereby reducing the circuit cost.

In FIG. 2, the Ve voltage is applied to the X electrode in the falling period and the address period of the reset period. However, the reference voltage (0 V in FIG. 3) is applied to the X electrode, and the voltage difference between the X electrode and the Y electrode is shown in FIG. 2. In order to maintain the same, the voltage level applied to the Y electrode can be reduced as a whole by the voltage applied to the X electrode in the falling period and the address period of the reset period in the driving waveform of FIG. 2. This eliminates the power supply for the Ve voltage, resulting in lower circuit costs. Hereinafter, such an embodiment will be described in detail with reference to FIG. 3.

3 is a driving waveform diagram of a plasma display panel according to a second exemplary embodiment of the present invention.

As shown in FIG. 3, the driving waveform according to the second embodiment of the present invention applies a reference voltage (0 V in FIG. 3) to the X electrode in the falling period and the address period of the reset period as described above. It is the same as the driving waveform of the first embodiment of the present invention except that the voltage level is reduced by the Ve voltage level.

That is, in the falling period of the reset period, the Y electrode is reduced from the Vs voltage to the Vnf1 voltage while the X electrode is kept at 0V. Then, a weak discharge occurs between the Y electrode and the X electrode and between the Y electrode and the A electrode while the voltage of the Y electrode decreases, and the negative wall charge formed on the Y electrode and the positive wall formed on the X electrode and the A electrode. The charge is erased. As described above, the Vnf1 voltage is a voltage obtained by lowering the Vnf voltage of FIG. 2 by the Ve voltage.

In the address period, a scan pulse having a VscL1 voltage and an address pulse having a Va voltage are applied to the Y electrode and the A electrode, respectively, to select a cell to be turned on while the X electrode is held at 0V. The unselected Y electrode biases the VscH1 voltage higher than the VscL1 voltage, and applies a reference voltage to the A electrode of the cell that is not turned on. Then, discharge occurs between the Y electrode to which the VscL1 voltage is applied and the A electrode to which the Va voltage is applied, thereby forming positive wall charges on the Y electrode and negative wall charges on the A and X electrodes, respectively. Similarly, the VscL1 voltage is the same voltage as lowering the VscL voltage of FIG. 2 by the Ve voltage, and the VscH1 voltage is the same voltage as lowering the VscH voltage of FIG. 2 by the Ve voltage. In this case, the driving waveform of the second embodiment of the present invention can reduce the number of power supplies for supplying the voltage applied to the X electrode, thereby making the circuit configuration simpler and lowering the circuit price.

The maintenance period is the same as described above. At this time, if only the reference voltage is applied to the X electrode in the reset and address periods, and the voltage (Va in FIG. 3) applied to the X electrode in the sustain period is supplied from the address electrode driver 300, the Y electrode is actually The reset operation, the address operation, and the sustain discharge operation are performed only by the driving waveform applied to the integrated board, which can be driven by only one board.

In addition, according to the first and second embodiments of the present invention, since the pulse for sustain discharge is supplied only from the scan electrode driver 500, the impedance in the path to which the sustain discharge pulse is applied may be constant.

Although the preferred embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements of those skilled in the art using the basic concepts of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

When the sustain discharge pulse is alternately applied to the scan electrode and the sustain electrode in the sustain period, a power recovery circuit for applying the sustain discharge pulse is required in the scan electrode driver and the sustain electrode driver, respectively. However, according to the present invention, since the sustain discharge pulse having a high voltage and a low voltage is alternately applied only to the scan electrodes in the sustain period, a power recovery circuit is required only in the scan electrode driver. Therefore, the circuit price is reduced, and the unit cost of the plasma display device is reduced.

When a low voltage is applied to the scan electrode in the sustain period, negative ions are dispersed and moved between the sustain electrode and the address electrode, thereby causing low discharge. According to the present invention, however, low discharge is prevented by increasing the voltage difference between the scan electrode and the sustain electrode by biasing the voltage of the sustain electrode to a positive voltage when applying the sustain discharge pulse in the sustain period. In addition, since the sustain discharge pulse is supplied only from the scan electrode driver, the impedance may always be constant.

In addition, a driving waveform is applied only to the scan electrode while the sustain electrode is biased to a constant voltage, and in the sustain period, an integrated board for driving with only one board can be realized by supplying the bias voltage of the sustain electrode from the address electrode driver. As a result, the unit cost of the plasma display device can be further reduced.

Claims (8)

In a plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, a frame is driven by dividing a frame into a plurality of subfields. In the method, In the retention period, Alternately applying a positive first voltage and a negative second voltage to the first electrode, and Biasing the voltage of the second electrode to a positive voltage while applying the second voltage to the first electrode Method of driving a plasma display panel comprising a. The method of claim 1, In the address period, applying a scan pulse to the first electrode to be selected while biasing the plurality of first electrodes to a third voltage; Including; And a bias voltage of the second electrode is the same voltage as the third voltage. The method of claim 1, In the address period, applying a third voltage and a fourth voltage to the selected first and third electrodes, respectively Including; And a bias voltage of the second electrode is the same voltage as the fourth voltage. The method of claim 3, wherein And the second electrode is biased at a fifth voltage in a reset period and an address period. The method of claim 4, wherein And the fifth voltage is a ground voltage. A plasma display panel including a plurality of first electrodes, a plurality of second electrodes, and a plurality of third electrodes formed in a direction crossing the first electrode and the second electrode, and A driving circuit which applies a driving voltage to the plasma display panel to display an image on the first to third electrodes Including; The drive circuit, In the sustain period, a positive first voltage and a negative second voltage are alternately applied to the first electrode, The first electrode and the second electrode when the second voltage is applied to the first electrode than the voltage difference between the first electrode and the second electrode when the first voltage is applied to the first electrode Plasma display device for setting a larger voltage difference. The method of claim 6, The drive circuit, When the first voltage is applied to the first electrode, a ground voltage is applied to the second electrode, and when the second voltage is applied to the first electrode, the second electrode is positively lower than the first voltage. A plasma display device for applying a voltage. The method according to claim 6 or 7, And the second electrode is biased to the ground voltage in the reset period and the address period.

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