KR20060009418A - Method of manufacturing semiconductor device - Google Patents

Abstract

The present invention discloses a method of manufacturing a semiconductor device capable of preventing generation of stringer foreign matter in a via region when forming a metal-insulator-metal (MIM) capacitor. According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: sequentially forming a lower metal film, a dielectric film, and an upper metal film on an interlayer insulating film over a semiconductor substrate having a capacitor formation region and a via region; Etching the upper metal layer to form an upper electrode; Etching the dielectric layer; The method of manufacturing a semiconductor device comprising forming a MIM capacitor in the capacitor formation region by etching the lower metal layer to form a lower electrode, wherein the etching of the upper metal layer, the dielectric layer, and the lower metal layer comprises a via region. Proceeding to the state covered by the photosensitive film is characterized in that to prevent the generation of the stringer in the via region.

Description

Method of manufacturing semiconductor device

1A and 1B are views for explaining a conventional MIM process.

2 is a view for explaining a method of manufacturing a semiconductor device according to the present invention.

Explanation of symbols on the main parts of the drawings

1: semiconductor substrate 2: interlayer insulating film

3: via hole 4: tungsten film

5: lower metal film 5a: lower electrode

6: dielectric film 7: upper metal film

7a: upper electrode 8,9: photoresist pattern

10: MIM Capacitor 12: Stringer

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device capable of preventing generation of stringer foreign material in the lower metal film during a metal-insulator-metal (MIM) process. will be.

As is well known, capacitors in memory devices have been formed with a structure of poly-insulator-poly (PIP) of poly-insulating film-poly. However, as a recent memory device requires high performance, the PIP structure has been replaced by structures such as poly-insulator-metal (PIM), metal-insulator-poly (MIP), and metal-insulator-metal (MIM).

Among them, the MIM structure has low series resistance, which can realize a high Q (Quality Factor) capacitor. In particular, it has low thermal budget, low Vcc, and small parasitic (Parastic Resistance & Capacitance). It is widely used as a structure.

In forming a capacitor having a MIM structure (hereinafter, referred to as a MIM capacitor), the following process is conventionally performed.

1A and 1B are diagrams for explaining a conventional MIM process.

Referring to FIG. 1A, an interlayer insulating film 2 is formed on a semiconductor substrate 1 having a capacitor formation region and a via region. Then, after depositing the plug tungsten film 4 on the interlayer insulating film 2, the surface is planarized through a chemical mechanical polishing (CMP) process.

Next, the lower metal film 5, the dielectric film 6, and the upper metal film 7 are sequentially deposited on the interlayer insulating film 2 including the tungsten film 4. Then, after the photoresist film is applied on the upper metal film 7, the photoresist film is exposed and developed to form a first photoresist film pattern 8 covering the capacitor formation region.

Referring to FIG. 1B, the upper metal layer 7 is etched using the first photoresist layer pattern as an etch barrier to form the upper electrode 7a, and subsequently the dielectric layer 6 is etched. Then, in a state where the first photoresist pattern is removed, a second photoresist pattern (not shown) for forming a lower electrode is formed on the substrate resultant again, and then a lower metal layer ( 5) is etched to form the lower electrode 5a in the capacitor formation region, thereby forming the MIM capacitor 10 including the lower electrode 5a of the metal material, the dielectric film 6, and the upper electrode 7a of the metal material. .

However, according to the conventional MIM process as described above, there is no big problem in the capacitor formation region, but a stringer, in which the upper and lower metal layers and the dielectric layer are not completely etched and partially remains in the via region, is generated. In addition, such a stringer may fall in the form of particles, causing short between metal wirings, resulting in a decrease in yield.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor device capable of preventing generation of stringer foreign substances in the via region during the MIM process.

In order to achieve the above object, the present invention comprises the steps of sequentially forming a lower metal film, a dielectric film and an upper metal film on the interlayer insulating film on the semiconductor substrate having a capacitor formation region and a via region; Etching the upper metal layer to form an upper electrode; Etching the dielectric layer; The method of manufacturing a semiconductor device comprising forming a MIM capacitor in the capacitor formation region by etching the lower metal layer to form a lower electrode, wherein the etching of the upper metal layer, the dielectric layer, and the lower metal layer comprises a via region. A method of manufacturing a semiconductor device is provided so as to prevent the occurrence of a stringer in the via region by covering the photosensitive film.

(Example)

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the technical principle of the present invention, in the present invention, in the MIM process, the upper metal film, the dielectric film and the lower metal film is etched in a state in which the via region is covered after depositing the lower metal film dielectric film and the upper metal film Do it.

In this case, the lower metal film, the dielectric film, and the upper metal film remain in the via region. Accordingly, occurrence of stringer foreign matter in the via region and short circuit between metal wires caused by the falling off of the stringer foreign material can be prevented. do.

In detail, FIGS. 2A and 2B are diagrams for describing a method of manufacturing a semiconductor device according to the present invention. 1A and 1B are denoted by the same reference numerals.

Referring to FIG. 2A, an interlayer insulating film 2 is formed on a semiconductor substrate 1 having a capacitor formation region and a via region. Then, after depositing the plug tungsten film 4 on the interlayer insulating film 2, the surface is planarized through a chemical mechanical polishing (CMP) process. At this time, the tungsten film 4 in the via region is formed only on the surface of the via hole 3.

Next, the lower metal film 5, the dielectric film 6, and the upper metal film 7 are sequentially deposited on the interlayer insulating film 2 including the tungsten film 4. Then, after the photoresist film is applied on the upper metal film 7, it is exposed and developed to form a first photoresist pattern 9 covering the capacitor formation region. In this case, unlike the conventional method, the first photoresist layer pattern 9 is formed to cover the region where the capacitor is to be formed, as well as to cover the via region. This will be described later to prevent the generation of stringer foreign substances in the via region during the subsequent etching of the upper and lower metal layers and the dielectric layer.

Referring to FIG. 2B, the upper metal layer 7 is etched using the first photoresist pattern as an etch barrier, thereby forming the upper electrode 7a. Subsequently, the dielectric film 6 is etched using the first photoresist pattern. In this case, as described above, since the via region is covered by the first photoresist layer pattern 9, the upper metal layer 7 and the dielectric layer (in the via region during the etching of the upper metal layer 7 and the dielectric layer 6). 6) No etching is done.

Subsequently, in a state where the first photoresist pattern is removed, the photoresist is again applied on the substrate resultant, then exposed and developed to form a second photoresist pattern (not shown). In this case, the second photoresist pattern may also be formed to cover the via region. Subsequently, the lower metal layer 5 is etched using the second photoresist layer pattern to form a lower electrode 5a, whereby the lower electrode 5a, the dielectric layer 6, and the metal are formed in the capacitor formation region. A MIM capacitor 10 made of a material upper electrode 7a is formed.

Here, in the etching of the lower metal film, the etching in the via area is not performed in connection with the fact that the via area is covered by the second photoresist film pattern. Thus, the occurrence of the stringer foreign material is also prevented.

As a result, since the present invention performs etching of the upper and lower metal films and the dielectric film while covering the via region with the photoresist film, it is possible to prevent the occurrence of stringer foreign matter in the via region, and thus, the metal by the stringer foreign material falling off. No electrical short occurs between the wirings.

As described above, the present invention can prevent the occurrence of stringers in the via region, as well as the electrical short between the metal wires due to the stringers, by performing the etching process while covering the via region with the photosensitive film in the MIM process. It can also be prevented.

Therefore, the present invention can improve device reliability and manufacturing yield as well as reliability of the process itself.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

Claims (1)

Sequentially forming a lower metal film, a dielectric film, and an upper metal film on an interlayer insulating film over the semiconductor substrate having a capacitor formation region and a via region; Etching the upper metal layer to form an upper electrode; Etching the dielectric layer; The method of manufacturing a semiconductor device comprising forming a MIM capacitor in the capacitor formation region by etching the lower metal layer to form a lower electrode. And etching the upper metal film, the dielectric film, and the lower metal film to cover the via area with a photoresist to prevent generation of stringers in the via area.

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