KR20060008204A - Laminated ceramic capacitor - Google Patents

Abstract

The present invention relates to a multilayer ceramic capacitor suitable for being used for decoupling of high frequency circuits by minimizing parasitic inductance while increasing the size or the number of processes, wherein the multilayer ceramic capacitor is formed by stacking a plurality of ceramic sheets. Ceramic blocks; A plurality of external electrodes formed on outer surfaces of the ceramic block facing each other and set to + or − terminals, respectively; At least one first and second internal electrodes vertically adjacent to the inside of the ceramic block and flowing current in different directions; And a plurality of lead patterns formed integrally with the first inner electrode and connected to an outer electrode set as a + or − terminal.

Multilayer ceramic capacitor, parasitic inductance, electrode pattern, ceramic sheet, drawing pattern,

Description

Laminated Ceramic Capacitor

1 is a perspective view illustrating an external shape of a general multilayer ceramic capacitor.

2 is an exploded perspective view showing the internal electrode structure of a conventional multilayer ceramic capacitor.

3 is an exploded perspective view showing the internal electrode structure of another conventional multilayer ceramic capacitor.

4 is an internal electrode structure diagram showing a first embodiment of a multilayer ceramic capacitor according to the present invention.

5 is an internal electrode structure diagram showing a second embodiment of the multilayer ceramic capacitor according to the present invention.

6 is an internal electrode structure diagram showing a third embodiment of the multilayer ceramic capacitor according to the present invention.

7 is an internal electrode structure diagram showing a fourth embodiment of the multilayer ceramic capacitor according to the present invention.

8 is an internal electrode structure diagram showing a fifth embodiment of the multilayer ceramic capacitor according to the present invention.

9 is an internal electrode structure diagram showing a sixth embodiment of the multilayer ceramic capacitor according to the present invention.

10A to 10E are views showing the arrangement of external electrodes in the multilayer ceramic capacitor according to the first embodiment of the present invention.

11A to 11G show the external electrode arrangement in the multilayer ceramic capacitor according to the second embodiment of the present invention.

12A to 12E are views showing the arrangement of external electrodes in the multilayer ceramic capacitor according to the fifth embodiment of the present invention.

13 (a) to 13 (e) show the external electrode arrangement in the multilayer ceramic capacitor according to the sixth embodiment of the present invention.

Explanation of symbols on the main parts of the drawings

41, 51, 61, 71, 81, 91: first electrode

42, 52, 62, 72, 82, 92: second electrode

411,421: first conductive pattern

412,422: Second conductive pattern

413,414,423,424: withdrawal pattern

The present invention relates to a multilayer ceramic capacitor, and more particularly, to a multilayer ceramic capacitor suitable for use in decoupling in a high frequency circuit by minimizing the occurrence of parasitic inductance.

A capacitor is a device that can store electricity. Basically, two electrodes are opposed to each other, and electricity is accumulated on each electrode when a voltage is applied. When a DC voltage is applied, a capacitor is stored in the capacitor during electricity storage. Current flows, but no current flows in the stored state. When an AC voltage is applied, the polarity of the electrodes alternates, so that the AC current continues to flow. This capacitor is represented by the accumulator capacity F.

These capacitors are made of aluminum according to the type of insulator positioned between the electrodes, aluminum electrolytic capacitors having a thin oxide film between the aluminum electrodes, and tantalum capacitors, which are electrolytic capacitors using tantalum as electrode material, between the electrodes. Ceramic capacitor using high dielectric constant such as barium titanate (Tiitamu-Barium), laminated ceramic capacitor using high dielectric constant ceramic in multilayer structure as dielectric provided between electrodes, polystyrene film as dielectric between electrodes It is divided into several types such as film capacitors.

Among the above, the multilayer ceramic capacitor is applied in many electronic circuits as long as it has excellent temperature characteristics and frequency characteristics, and has a merit that it can be miniaturized.

1 is a perspective view illustrating an appearance of a multilayer ceramic capacitor. The multilayer ceramic capacitor 10 includes a ceramic block 11 having a +/− electrode pattern formed therein and a plurality of ceramic sheets stacked thereon, and the ceramic block 11. It is formed on the side of the () and consists of external electrodes (12, 13) connected to the internal + /-electrode pattern, respectively.

The multilayer ceramic capacitor 10 includes a conductive pattern for performing two electrode functions of a capacitor between a plurality of ceramic sheets. The conductive pattern may be basically formed of two electrode patterns having a rectangular shape arranged to be parallel to each other at a predetermined interval, but the shape and arrangement of the pattern are variously modified to improve the characteristics of the capacitor.

FIG. 2 is an exploded perspective view illustrating an internal electrode structure applied to a conventional multilayer ceramic capacitor, in which rectangular internal electrode patterns 21 and 22 are stacked in a vertical direction, in which the odd-numbered internal electrode patterns 21 are formed. The lead portions 21a and 22a connected to the terminal electrodes 12 and 13 formed outside the ceramic block 11 so that voltages having different polarities are applied to the inner electrode patterns 22 arranged evenly with each other. To form.

In the multilayer ceramic capacitor configured as described above, voltages having different polarities are applied between upper and lower adjacent inner electrode patterns 21 and 22, and electric charges are accumulated between the inner electrode patterns 21 and 22 having different polarities. This structure increases the area of the electrode patterns facing each other, thereby making it possible to realize a high capacity capacitor. In addition, since the + and − electrodes are alternately arranged, the magnetic flux generated by the high frequency current flowing in the electrode patterns 21 and 22 opposite to each other cancel each other, thereby reducing the parasitic inductance ESL. have.

The above parasitic inductance in the capacitor element is an unnecessary component that lowers the characteristics of the capacitor, and increases in proportion to the current path flowing through the electrode pattern, and the directions of the currents flowing through the electrode patterns 21 and 22 facing each other coincide with each other. If it is increased further.

In order to reduce such parasitic inductance, in the multilayer ceramic capacitor, as shown in FIG. 2, by changing the current directions between the internal electrode patterns 21 and 22 facing each other, the magnetic fluxes generated by the respective currents cancel each other, thereby causing parasitic inductance. Reduce the parasitic inductance or reduce the current path.

3 illustrates an internal electrode structure of another conventional multilayer ceramic capacitor, and in addition to the structure shown in FIGS. 1 and 2, the internal electrode patterns 21 and 22 alternately stacked up and down adjacent to each other. Each of the second lead portions 21b and 22b formed to face each other is further provided, and the current direction flowing on the internal electrode patterns 21 and 22 is more accurately induced, and thus parasitic than in the structure of FIG. 2. It has the effect of further reducing inductance.

However, even if it is configured as described above, the generated parasitic inductance cannot be completely eliminated, and the decoupling capacitor applied to the high frequency circuit is greatly affected by such a small amount of parasitic inductance, thereby further reducing the parasitic inductance. Is required.

In addition to the above, the laminated electronic component of Japanese Patent Laid-Open No. 2002-151349 forms an internal electrode formed on an inner majority plane of a ceramic block with two F-shaped electrode patterns, and two F-shaped electrodes formed on the same plane. The parasitic inductance caused by the high frequency current is reduced by arranging the currents to flow in opposite directions in the pattern. And forming at least one pair of flow path portions formed by sandwiching the notches and allowing current to flow in opposite directions to each other, thereby reducing parasitic inductance caused by high frequency current by causing current flow in two flow path portions in one internal electrode to be reversed to each other. Let's do it.

In the case of the two methods, the parasitic inductance could be reduced more than the stacked devices of FIGS. 2 and 3, but the level required by the decoupling capacitor of the high frequency circuit could not be satisfied. In the case of the high frequency circuit, the decoupling capacitor Since parasitic inductance has a large effect on circuit performance, there is a need for further improvement of parasitic inductance.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the above-mentioned conventional problems, and an object thereof is to provide a multilayer ceramic capacitor suitable for use for decoupling of high frequency circuits by minimizing parasitic inductance at high capacity without increasing size or number of processes. will be.

As a constituent means for achieving the above object of the present invention, a multilayer ceramic capacitor according to the present invention, a ceramic block formed by stacking a plurality of ceramic sheets; A plurality of external electrodes formed on outer surfaces of the ceramic block facing each other and set to + or − terminals, respectively; At least one first and second internal electrodes vertically adjacent to the inside of the ceramic block and flowing current in different directions; And a plurality of lead patterns formed integrally with each of the first inner electrodes and connected to an outer electrode set as a + or − terminal.

In addition, in the multilayer ceramic capacitor according to the present invention, the upper and lower adjacent first and second internal electrodes may be connected to external electrodes set to different polarities through respective drawing patterns.

In the multilayer ceramic capacitor according to the present invention, the first internal electrode and the second internal electrode may flow in opposite directions to each other or in a mutually orthogonal direction.

In the multilayer ceramic capacitor according to the present invention having the above characteristics, the first and second internal electrodes are each formed in parallel on the same plane, and have a pair having a U-shape by forming a slot having a predetermined length at the side of the square pattern. It may be made of a conductive pattern.

In addition, in the multilayer ceramic capacitor according to the present invention, the first inner electrode is formed of a rectangular conductive pattern and two slots formed in a center direction at two opposite edges of the conductive pattern, respectively, and the second The inner electrode includes a rectangular conductive pattern and two slots each formed in a center direction at two opposite edges of the conductive pattern so as to be perpendicular to the slot of the first inner electrode.

In still another aspect, in the multilayer ceramic capacitor according to the present invention, the first internal electrode is formed to penetrate a rectangular conductive pattern and two opposite corners on the conductive pattern, thereby dividing the conductive pattern into two parts. The second internal electrode is formed of a rectangular conductive pattern and two slots facing each other at the two opposite edges of the conductive pattern, respectively, and having two slots orthogonal to the slots of the first internal electrode. It is done.

In still another aspect, in the multilayer ceramic capacitor according to the present invention, the first internal electrode may be formed of a rectangular conductive pattern, and the second internal electrode may be formed of two rectangular conductive patterns and two mutually opposite surfaces on the conductive pattern. It is formed to penetrate the corner may be made of a slot for dividing the conductive pattern into two.

In addition, in the multilayer ceramic capacitor according to the present invention, wherein the first and second internal electrodes are formed of a pair of U-shaped conductive patterns, the pair of conductive patterns have slot positions facing the same direction or opposite to each other. It can be formed to.

In addition, in the multilayer ceramic capacitor according to the present invention, wherein the first and second internal electrodes are formed of a pair of U-shaped conductive patterns, the pair of conductive patterns flow in opposite directions in adjacent regions and are parallel to each other in the same direction. When the arrangement is connected to the external electrodes of different polarities, when the pair of conductive patterns are arranged in opposite directions, the pair of conductive patterns are connected to the external electrodes of the same polarity.

Hereinafter, the structure and operation of the multilayer ceramic capacitor according to the present invention will be described with reference to the accompanying drawings.

The multilayer ceramic capacitor according to the present invention is a ceramic block 11 having a rectangular parallelepiped shape having four side surfaces and an upper and lower side positioned on the upper and lower sides of the ceramic block 11, similar to the general multilayer ceramic capacitor shown in FIG. 1. It is formed on the side and consists of a plurality of external electrodes (12, 13) set to the terminal of the + or-polarity.

FIG. 1 illustrates an eight-terminal type having eight external electrodes 12 and 13 in total, four on two opposite sides of the ceramic block 11, but the number of the external electrodes 12 and 13 is shown in FIG. May be further increased according to needs and demands. For example, two external electrodes may be further provided, one on each of the two other sides besides the two sides on which the eight external electrodes 12 and 13 are formed, so that the external terminal may be realized in a 10-terminal form. Two external electrodes may be further formed on two other sides besides two sides on which the electrodes 12 and 13 are formed, and thus may be implemented in a 12-terminal shape. In this manner, when the number of external electrodes is further increased, the current path is shortened to reduce the parasitic inductance.

In addition, the external electrodes 12 and 13 formed on the ceramic block 11 are alternately arranged with + and − polarities so as to have different polarities.

In addition, in the multilayer ceramic capacitor of the present invention, the first and second internal electrodes having different polarities are repeatedly stacked up and down inside the ceramic block 11, as in the related art, and perform a predetermined capacity accumulation function. .

The multilayer ceramic capacitor of the present invention has a shape of first and second internal electrodes alternately stacked inside the ceramic block 11 such that current paths from the first and second internal electrodes adjacent to each other flow in different directions. By changing, it is characteristic to aim at reduction of parasitic inductance.

4 to 9 illustrate various embodiments of the first and second internal electrodes of the multilayer ceramic capacitor according to the present invention.

First, FIG. 4 shows an internal electrode structure according to the first embodiment of the multilayer ceramic capacitor according to the present invention. Referring to this, the multilayer ceramic capacitor of the present invention is vertically adjacent to the inside of the ceramic block 11. The first and second internal electrodes 41 and 42 and the first and second internal electrodes 41 and 42 which are arranged and applied with different polarities (+ or −), respectively, to the external electrodes 12 and 13. The lead patterns 413, 414, 423, 424 are connected to each other. The first and second internal electrodes 41 and 42 are vertically adjacent to each other, and voltages having different polarities are applied to cancel magnetic fluxes generated by respective high frequency currents.

In addition, the first and second internal electrodes 41 and 42 may be disposed in parallel with each other on a predetermined plane inside the ceramic block 11 and have a slot in the same direction to form a pair of first and second C-shaped shapes. Conductive patterns 411/412, 421/422, wherein the plurality of lead patterns 413, 414, 423, 424 are integrally formed on the first and second conductive patterns 411/412, 421/422 and the ends of the conductive patterns 411/412, 421/422 Is connected to the external electrodes (12, 13).

In this case, the pair of first conductive patterns 411 and 421 and the second conductive patterns 412 and 422 are applied with external electrodes having different polarities, and thus, the pair of first conductive patterns 411 and 421 and the second conductive patterns are respectively applied. Currents in opposite directions flow between adjacent regions of the 412 and 422 so that magnetic fluxes generated between the first conductive patterns 411 and 421 and the second conductive patterns 412 and 422 located on the same plane cancel each other out.

For example, the first conductive pattern 411 of the first inner electrode 41 is connected to the + external electrode 12 through the extraction pattern 413, and the second conductive pattern 412 is the extraction pattern 414. Is connected to the external electrode 13 through, and in the second internal electrode 42, the first conductive pattern 421 is connected to the external electrode 13 through the extraction pattern 423, and the second The conductive pattern 422 is connected to the + external electrode 12 through the lead pattern 424.

In the multilayer ceramic capacitor of the present invention described above, currents in opposite directions flow between adjacent first and second internal electrodes 41 and 42 located on different planes in the ceramic block 11, and are simultaneously located on the same plane. A pair of conductive patterns 411, 412, 421, 422 allow currents in opposite directions to flow, and in addition, the conductive patterns 411, 412, 421, 422 each have a portion of the pattern divided through slots. By configuring current to flow in different directions even between adjacent current paths in the pattern, the magnetic fluxes generated by the current flowing in the capacitor cancel each other, thereby minimizing parasitic inductance.

In general, in two adjacent current paths, when the current paths are parallel and opposite in current direction, the directions of magnetic fluxes generated by respective currents are reversed, and the magnetic fluxes cancel each other, and parasitic inductances proportional to the magnetic flux. It is also reduced. Accordingly, in the case of the internal electrode structure improved by the present invention shown in FIG. 4, the first and second internal electrodes 41 and 42 are reversed in the current direction of the first and second internal electrodes 41 and 42 positioned up and down. Also in 42), by dividing the pattern and forming slots, the current path is further subdivided, and further, by reversing the current direction between adjacent current paths, more parasitic inductance can be reduced as compared with the conventional method.

In the above structure, the lead patterns 413, 414, 423, 424, which connect the first and second conductive patterns 411, 412, 421, 422 to the +/- external electrodes 12, 13, have their lengths as short as possible to shorten the current path. . The current flows while voltage is applied to the extraction patterns 413, 414, 423, 424, and parasitic inductance may also occur due to the current flowing in the extraction patterns 413, 414, 423, 424. Therefore, as the current path is shortened as described above, the amount of parasitic inductance generated by the drawing patterns 413, 414, 423 and 424 can be made smaller.

In the first embodiment, the arrangement of the pair of U-shaped conductive patterns for implementing the first and second internal electrodes can be changed.

5 is an internal electrode structure diagram showing a second embodiment of the present invention in which the arrangement of a pair of conductive patterns is changed. First and second internal electrodes 51 and 52 to which voltages of different polarities are applied adjacent to each other up and down are shown in FIG. And extraction patterns 513, 514, 523, and 524 that connect the first and second internal electrodes 51 and 52 to the external electrodes 12 and 13, respectively, and the first and second internal electrodes 51. As in the first embodiment, reference numeral 52 denotes a U-shaped first conductive pattern 511 and 521 and a second conductive pattern 512 and 522 arranged in parallel on the same plane.

Unlike the first embodiment shown in FIG. 4, the first conductive patterns 511 and 521 and the second conductive patterns 512 and 522 are arranged such that slots implementing the U shape are located in opposite directions, respectively. Voltages of the same polarity are applied to the first conductive patterns 511 and 521 and the second conductive patterns 512 and 522. For example, voltages of + polarity are applied to the first and second conductive patterns 511 and 512 of the first internal electrode 41, and the first and second conductive patterns 521 and 52 of the second internal electrode 42 are applied. -A polarity voltage is applied.

In this case, the first conductive patterns 511 and 521 and the second conductive patterns 512 and 522 have slots formed in opposite directions, respectively, so that reverse currents flow in the adjacent regions as in the first embodiment. The magnetic flux generated by is canceled out. In addition, the vertically symmetrical current paths flowing between the first and second internal electrodes 41 and 42 are reversed, respectively, to cancel the magnetic flux generated by the high frequency current.

6 shows an internal electrode structure of a multilayer ceramic capacitor according to a third embodiment of the present invention. Referring to FIG. 6, the multilayer ceramic capacitor is basically stacked up and down inside the ceramic block 11. A plurality of lead patterns 614 and 624 connecting the first and second internal electrodes 61 and 62 and the first and second internal electrodes 61 and 62 to the external electrodes 12 and 13 having different polarities, respectively. The first and second internal electrodes 61 and 62 may each have a rectangular conductive pattern 611 and 621, and two conductive edges 611 and 621, respectively, formed in an inner center direction at opposite edges of the conductive pattern 611 and 621. 611, 621 is composed of two slots (612, 613, 621, 623) to cut a part.

The pair of slots 612, 613, 621, 623 described above are formed in parallel to each other to divide the conductive patterns 611, 621 into two large areas.

In this case, the slots 612 and 613 formed in the first internal electrode 61 and the slots 621 and 623 formed in the second internal electrode 62 are formed in directions perpendicular to each other. That is, when + voltage is applied to the conductive pattern 611 of the first internal electrode 61 and − voltage is applied to the conductive pattern 612 of the second internal electrode 62, the first internal electrode ( The slots 612 and 613 of the 61 are formed in the center direction from the upper and lower edges so as to be parallel to the current direction, and the slots 622 and 623 of the second internal electrode 62 are the left and right edges to be parallel to the current direction of the conductive pattern 621. Is formed in the center direction.

As a result, the slots 612 and 613 of the first inner electrode 61 induce a current in the conductive pattern 611 to flow in the vertical direction, and the slots 621 and 623 of the second inner electrode 62 are the conductive pattern 621. Induces the current flowing in the flow in the left and right directions. In addition, the current direction is reversed between adjacent regions of the conductive patterns 611 and 621 based on the slots 612 and 613 and 621 and 623.

Accordingly, in the multilayer ceramic capacitor according to the third embodiment, current flows in a direction orthogonal to each other between the first internal electrode 61 and the second internal electrode 62 vertically adjacent to the inside of the ceramic block 11, thereby providing parasitic inductance. In addition, the parasitic inductance can be further reduced by reducing the amount of magnetic flux in each of the first and second internal electrodes 61 and 62.

As a modification of the above structure, Figs. 7 and 8 show the internal electrode structures according to the fourth and fifth embodiments of the multilayer ceramic capacitor according to the present invention.

The multilayer ceramic capacitor shown in FIGS. 7 and 8 is formed by cutting two conductive patterns by connecting two slots on the first inner electrode or the second inner electrode side in the structure shown in FIG. 6.

More specifically, the multilayer ceramic capacitor according to the fourth embodiment shown in FIG. 7 includes the first internal electrodes 71 and 72 adjacent to each other and the first and second internal electrodes 71 and 72 adjacent to each other. A plurality of lead patterns 713 and 724 connecting the external electrodes 12 and 13 having different polarities, respectively, wherein the first inner electrode 71 has a rectangular conductive pattern 711 and the conductive pattern 711. And a slot 712 formed to penetrate two mutually opposite corners on each of the plurality of conductive patterns 711. The second internal electrode 72 has a rectangular conductive pattern 721 and the conductive member. Two slots 723 and 722 are formed in two opposite corners of the pattern 721 in the center direction, and are formed in a direction orthogonal to the slot 712 of the first internal electrode 71.

Next, referring to FIG. 8, the multilayer ceramic capacitor according to the fifth embodiment of the present invention includes the first and second internal electrodes 81 and 82 adjacent to each other vertically and the first and second internal electrodes 81 and 82. A plurality of lead patterns 814 and 823 are connected to the external electrodes 12 and 13 having different polarities, respectively, wherein the first inner electrode 81 includes a rectangular conductive pattern 811 and the conductive pattern 811. The two inner electrodes 82 are formed in the center direction at two opposite edges, respectively, and are parallel to each other, and the second inner electrode 82 includes a rectangular conductive pattern 821 and the conductive pattern 821. It is formed to penetrate two mutually opposite corners of the top to divide the conductive pattern 711 into two and consists of a slot 712 formed in a direction orthogonal to the slots (812, 813).

7 and 8 are performed in the same manner as in the third embodiment shown in FIG.

As another variation, Fig. 9 shows the internal electrode structure of the multilayer ceramic capacitor according to the sixth embodiment of the present invention.

Referring to FIG. 9, the multilayer ceramic capacitor of the present invention includes first and second internal electrodes 91 and 92 formed up and down adjacent to the inside of the ceramic block 11, and the first and second internal electrodes 91. , 92 and a plurality of lead patterns 912 and 923 to connect the external electrodes 12 and 13 of different polarities, respectively, wherein the first inner electrode 91 is formed of a rectangular conductive pattern 911. The second internal electrode 92 is formed of a rectangular conductive pattern 921 and a slot 922 formed to penetrate two opposite corners on the conductive pattern 921 to divide the conductive pattern into two.

The second internal electrode 92 of FIG. 9 has the same shape as the second internal electrode 82 of FIG. 8, and exhibits the same electrical action. However, it is shown that the first internal electrode 91 may be formed of only a rectangular conductive pattern 911 in which no separate slot is formed.

Slots formed in the first and second internal electrodes illustrated in FIGS. 6 to 9 are respectively used to further subdivide the direction of the current flowing through the conductive pattern, and are formed parallel to the internal current direction.

Next, the multilayer ceramic capacitor according to the present invention may be formed in various forms such as an external electrode having an 8 terminal type, a 10 terminal type, and a 12 terminal type.

10 to 13 illustrate the arrangement of the extraction patterns for each type of external electrode in various embodiments of the multilayer ceramic capacitor according to the present invention.

First, FIG. 10 shows a configuration example of the extraction pattern according to the arrangement of the external electrodes in the first embodiment shown in FIG. 4, where (a) is an eight-terminal type, (b) and (c). In the case of 10 terminal type, (d) and (e) show a configuration example of the drawing pattern according to the change of arrangement of the external electrode in case of the 10 terminal type. 10 (a) to 10 (e), the first internal electrodes 41 and the second internal electrodes 42 are applied with opposite polarities, and the first and second internal electrodes 41 and 42 are applied to each other. The positions of the extraction patterns 413, 414, 423, and 424 are determined so that opposite polarities are applied to the first and second conductive patterns 411, 412, and 421, 422 respectively provided in the reference line).

Next, FIG. 11 shows a configuration example of the extraction pattern according to the arrangement of the external electrodes in the second embodiment shown in FIG. 5, and (a) shows the case where the external electrodes are 8-terminal type, (b) (e) shows an example of forming the withdrawal pattern of the internal electrode when the external electrode is 10 terminal type, and (f) and (g) are the 12 terminal type external electrode. In FIG. 11, the polarity of the first internal electrode 51 and the second internal electrode 52 are opposite to each other, and a pair of conductive patterns for implementing the first and second internal electrodes 51 and 52 ( The number and positions of the extraction patterns 513, 514, 523, 524 are determined so that the polarities of the 511, 512, 521, and 522 are the same.

In FIG. 11, in the case of (c) and (e), two lead patterns drawn out from the pair of conductive patterns 511, 512, 521, and 522 toward the end face are simultaneously connected to one external electrode located at the end face of the ceramic block. .

Next, FIG. 12 shows the arrangement form of the inner lead-out pattern according to the external electrode structure in the fifth embodiment of the present invention shown in FIG. 8, wherein (a) is a case where the external electrode is an eight-terminal type. b) and (c) indicate 10-terminal external electrodes, and (d) and (e) indicate 12-terminal shapes. In FIG. 12, the extraction patterns 814 and 823 are disposed so that the first internal electrodes 81 and the second internal electrodes 82 arranged up and down have different polarities.

FIG. 13 is a view showing the arrangement of the internal lead-out pattern according to the external electrode structure according to the sixth embodiment of the present invention shown in FIG. 9, wherein (a) is an eight-terminal external electrode, and (b), (c) shows a case where the external electrodes are 10-terminal, respectively, and (d) and (e) shows a case of 12-terminal. As in the previous example, in FIG. 13, the extraction patterns 912 and 923 are disposed such that the first internal electrodes 91 and the second internal electrodes 82 disposed up and down are connected to different polarities.

While the configuration and operation of the present invention have been described above with reference to various embodiments, the present invention is not limited to the above embodiments and can be applied in various ways within the scope of the claims of the present invention.

As described above, the multilayer ceramic capacitor according to the present invention can further reduce the parasitic inductance as compared with the prior art, and as a result, there is an excellent effect of realizing a capacitor suitable for decoupling of a high frequency circuit.

Claims (13)

A ceramic block formed by stacking a plurality of ceramic sheets; A plurality of external electrodes formed on outer surfaces of the ceramic block facing each other and set to + or − terminals, respectively; At least one first and second internal electrodes vertically adjacent to the inside of the ceramic block and flowing current in different directions; And And a plurality of lead patterns formed integrally with each of the first inner electrodes and connected to an outer electrode set as a + or − terminal. The method of claim 1, wherein the upper and lower adjacent first and second internal electrodes Multilayer ceramic capacitors, characterized in that connected to the external electrode set to a different polarity through the respective withdrawal pattern The method of claim 1, The multilayer ceramic capacitor of claim 1, wherein the first internal electrode and the second internal electrode flow in opposite directions. The method of claim 1, Multilayer ceramic capacitors, characterized in that the first internal electrode and the second internal electrode flows in a direction perpendicular to each other. The method of claim 3, wherein The first and second internal electrodes are respectively The multilayer ceramic capacitor is formed parallel to the same plane, and formed of a pair of conductive patterns having a U-shape by forming a slot of a predetermined length on the side of the rectangular pattern. The method of claim 4, wherein The first inner electrode is formed of a rectangular conductive pattern and two slots each formed in a center direction at two opposite edges of the conductive pattern, The second internal electrode is a multilayer ceramic capacitor comprising a rectangular conductive pattern and two slots each formed in a center direction at two opposite corners of the conductive pattern so as to be orthogonal to the slots of the first internal electrode. . The method of claim 4, wherein The first internal electrode is formed through a rectangular conductive pattern and two slots facing each other facing each other on the conductive pattern is formed of a slot for dividing the conductive pattern into two, The second internal electrodes are formed of a rectangular conductive pattern, and are formed in two centers at two opposite edges of the conductive pattern, respectively, and are formed of two ceramics orthogonal to the slots of the first internal electrodes. Capacitor. The method of claim 4, wherein The first internal electrode is formed of a rectangular conductive pattern, And the second internal electrode is formed to pass through a rectangular conductive pattern and two opposite corners on the conductive pattern, and is formed of a slot dividing the conductive pattern into two parts. The multilayer ceramic capacitor of claim 5, wherein the pair of conductive patterns face the same direction in a U-shaped slot position. The multilayer ceramic capacitor of claim 5, wherein the pair of conductive patterns are positioned in opposite directions to each other in a U-shaped slot position. The method of claim 5, The pair of conductive patterns is a multilayer ceramic capacitor, characterized in that the reverse current flows in the adjacent region. The multilayer ceramic capacitor of claim 9, wherein the pair of conductive patterns are connected to external electrodes having different polarities. The multilayer ceramic capacitor of claim 10, wherein the pair of conductive patterns are connected to external electrodes having the same polarity.

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