KR20060005022A - Printed circuit board and method of manufacturing the same - Google Patents

Abstract

The present invention relates to a printed circuit board and a method for manufacturing the same, and provides a printed circuit board and a method for manufacturing the same, in which internal circuits of upper and lower layers are connected through metal protrusions through a self-aligning circuit and a protrusion forming process using a barrier film pattern. . Here, in the alignment circuit and the protrusion forming process, the first barrier layer pattern is formed on the metal layer of the center substrate to shield the region where the internal circuit is to be formed, and then the first metal plating layers are formed on both sides of the center substrate. Selectively forming a second metal plating layer and a second barrier film for the metal projection on the metal plating layer, and performing a self-aligned etching process using the first barrier film pattern and the second barrier film as an etching mask to perform the first metal plating layer. And etching the metal layer to form the metal protrusion and the internal circuit, and then removing the first barrier layer pattern and the second barrier layer. Thereafter, the insulating layer and the copper foil are laminated, and then a self-aligning circuit and a projection forming step of using the substrate on which the insulating layer and the copper foil are laminated are continuously performed to provide a build-up multilayer printed circuit board.

As a result, the internal circuit and the copper protrusions can be formed at the same time, since the copper plating layer is not formed thick at one time, the plating deviation can be eliminated, and the amount of etching of the copper plating layer can be reduced. Can be formed and can be easily adjusted to target the thickness and width of the copper protrusions. In addition, it is possible to reduce the material cost when manufacturing a multi-layered central circuit board having a copper projection can reduce the cost.

Center Board, Internal Circuit, Copper Protrusion, Multilayer Printed Circuit Board, Barrier Film, Nickel Plating Layer, Copper Plating Layer, Self Alignment Etching Process

Description

Printed circuit board and method of manufacturing the same

1A to 1L are cross-sectional views illustrating a method of manufacturing a conventional build-up multilayer printed circuit board.

2 is a cross-sectional view illustrating a problem of a multilayer printed circuit board formed according to the manufacturing method of FIGS. 1A to 1L.

3A to 3F are cross-sectional views illustrating a method of manufacturing a build-up multilayer printed circuit board using a conventional copper protrusion.

4A to 4D are cross-sectional views illustrating a method of manufacturing a multilayer printed circuit board formed by pressing separately manufactured copper protrusions.

5A to 5I are cross-sectional views illustrating a method of manufacturing a build-up multilayer printed circuit board according to an exemplary embodiment of the present invention.

6 to 9 are cross-sectional views for describing other exemplary embodiments of the present invention.

<Explanation of symbols for the main parts of the drawings>

1, 30, 52, 100, 600, 700, 800, 900: center board

2, 13, 18: conductive layers 3, 16, 100b: through holes

4, 195: copper foil 5: filler

6, 14, 200: RCC 7, 56, 190: Insulation resin

8, 15: via hole 11, 12: metal plating

17 plating layer 20 PSR

32, 54, 170, 615, 715, 810, 910: internal circuit

34: electroless chemical copper 42, 46: copper plate

36, 120, 160, 620, 720, 820, 920: nickel plated layer

38, 130, 150, 610b, 710b, 730, 830, 930: copper plating layer

40, 48, 58, 180, 630, 740, 840, 940: copper protrusion

44 nickel plate 50, 110, 140 photosensitive film pattern

100a: insulation layer 100c, 610a, 710a: metal layer

The present invention relates to a printed circuit board and a method for manufacturing the same, and more particularly, to a method for manufacturing a build-up multilayer printed circuit board using copper protrusions formed by electroplating.

Printed circuit boards are the most basic components of many electronic products currently manufactured, and are widely used in mobile phones, washing machines, TVs, system boards such as routers, servers, satellites, and automobiles. In addition, recently, high-density multilayer printed circuit boards for miniaturization include mobile phones, PCS, IMT 2000, notebooks, palmtops, camcorders, ball grid arrays (CGA), chip scale packaging (CSP), and multi chip modules (MCM). It is applied to many package substrates for the same semiconductor. Hereinafter, the conventional manufacturing method of the above-mentioned printed circuit board is demonstrated with reference to drawings.

1A to 1L are cross-sectional views illustrating a method of manufacturing a conventional build-up multilayer printed circuit board.

1A and 1B, a center substrate 1 having copper foil coated on both surfaces thereof is used. In order to connect the conductor layer, the upper and lower surfaces of the central substrate 1 drill a through hole 3 with a drill and plate the through hole 3 to form a copper foil 4 inside the hole. Thereby, the copper foil of an upper surface and a lower surface is connected. Thereafter, the inside of the through hole 3 is filled with the filler 5 of the insulator component. Thereafter, the copper foils located on the upper and lower surfaces are patterned to form the first conductor layer 2.

Referring to FIG. 1C, a first Resin Coated Copper Foil (RCC) 6 having copper foil coated on one surface thereof is pressed and laminated on the upper and lower surfaces of the center substrate. The RCC refers to an adhesive insulating resin 7 coated on one surface of the copper foil.

Referring to FIG. 1D, the copper foil of the portion for forming the via holes on the surfaces of the first RCCs 6 and 7 is etched to expose the insulating resin (see region A in FIG. 1D).

Referring to FIG. 1E, the insulating resin 7 exposed by the laser drill is removed to form a first via hole 8 exposing a part of the first conductive layer 2.

1F and 1G, the second conductive layer 13 is formed by performing electroless plating and metal plating 11 along the step on the entire structure and then performing a predetermined patterning process. As a result, the metal plating 12 is also formed in the inner region of the first via hole 8 so that the first conductive layer 2 and the second conductive layer 13 are electrically connected to each other.

Referring to FIG. 1H, the second via hole 14 is formed by repeating the process described with reference to FIGS. 1C to 1G. That is, the second RCC 14 is compressed and laminated on the first RCCs 6 and 7 formed on the upper and lower surfaces thereof. As a result, the first via hole 8 is buried. A predetermined etching step is performed to remove the copper film on the second RCC 14 to expose the insulating resin. The insulating resin exposed by the laser drill is removed to form a second via hole 15 exposing a part of the second conductive layer 13.

Referring to FIG. 1I, a drill drills through holes 16 for interlayer connection and mounting of components. That is, the through hole 16 is formed by removing the upper second RCC 14, the upper first RCC 6, the central substrate 1, the lower first RCC 6, and the lower second RCC 14. .

Referring to FIGS. 1J and 1K, the electroless plating and metal plating are performed on the entire structure to form a plating layer 17 inside the via hole and the through hole, and a predetermined patterning process is performed to form the third conductive layer 18. Is formed, and an inner conductive layer is formed in the through hole 16. Thereby, the 2nd conductive layer 13 and the 3rd conductive layer 18 are electrically connected, and are electrically connected by the through-hole 16. As shown in FIG.

Referring to FIG. 1L, a PSR (solder mask) 20 is formed on an insulating resin between the third conductive layers 18.

Through the above-described method, a multilayer printed circuit board could be manufactured. However, as the size of electronic products has become smaller, lighter, and thinner, the diameter of via holes in printed circuit boards is gradually decreasing. Therefore, when the fine via holes are plated by using a general electroless and electroplating method, since the aspect ratio of the via holes is high, it is difficult to plate the inner surface of the via holes.

2 is a cross-sectional view illustrating a problem of a multilayer printed circuit board formed according to the manufacturing method of FIGS. 1A to 1L.

Referring to FIG. 2, in the manufacturing process of the build-up multilayer printed circuit board using the center board 1 having the copper foil, the electroless plating layer 11a and the electroplating layer 11b are formed on the existing copper foil 6 again. Therefore, the thickness of the metal conductor layer as a whole becomes thick. When the thickness of the metal conductor layer becomes thick, it is impossible to manufacture a fine circuit pattern in an etching process for manufacturing a circuit pattern. This is because the etchant used in the etching process has a constant etch factor, so that the metal conductor layer cannot be etched more than a certain aspect ratio.

In addition, the plating layer plated on the sidewall of the via hole is relatively very thin as compared to the lower and upper regions of the via hole. As a result, a predetermined crack is generated in the plating layer formed on the sidewall (particularly, the interface between the lower portion of the via hole and the sidewall region) to generate a weakly electrically disconnected region (see region B in FIG. 2).

In addition, the conventional multi-layer printed circuit board by the above-described method has a problem that there is no productivity because the processing speed is very slow because more than hundreds of thousands of via holes per m 2 must be drilled. To solve this problem, the capital investment cost should be increased.

In addition, as described above, after forming the first via hole, a second via hole should be formed in the upper region where the via hole is not formed (see FIG. 1H). That is, in order to electrically connect the multilayer conductive layers, the first via hole and the second via hole must be alternately formed. As a result, since a predetermined circuit element cannot be mounted in a region where a via hole is formed, there are many limitations in manufacturing a predetermined circuit on a multilayer printed circuit board. That is, problems such as area loss occur.

In order to solve the above-mentioned problems, an AGP process is formed in which copper protrusions are formed to electrically connect the upper and lower layers.

3A to 3F are cross-sectional views illustrating a method of manufacturing a build-up multilayer printed circuit board using a conventional copper protrusion.

Referring to FIGS. 3A and 3B, the internal circuit 32 is formed by etching the copper foil of the center substrate 30 on which copper foil is coated on both surfaces.

Referring to FIGS. 3C and 3D, the electroless chemical copper 34 is formed on both surfaces of the central substrate 30 on which the internal circuit 32 is formed, and electroplating using nickel is performed on both surfaces of the central substrate 30. The nickel plating layer 36 is formed in this.

Referring to FIG. 3E, the copper plating layer 36 is formed on both surfaces of the center substrate 30 by electroplating using copper. At this time, the copper plating layer 36 is formed to a thickness of 80 to 100㎛.

Referring to FIG. 3F, after the copper plating layer 38 in a region other than the predetermined region above the internal circuit 32 is etched, the copper protrusion 40 is formed in the center region 30 of the internal circuit 32. The nickel plating layer 36 and the electroless plating layer are removed. The multilayered printed circuit board may be manufactured by performing a lamination process on both surfaces of the central substrate on which the copper protrusions are formed on the internal circuit described above. At this time, the electrical connection of the circuits formed between each layer is made through a copper protrusion.

Since the via hole is not formed through the above-described protrusion, the problem caused by the via hole can be solved. However, in order to form a copper protrusion, since a copper plating layer having a thickness of about 80 μm or more is formed, there is a problem in that a plating error corresponding to about 10 to 20% of the thickness of the entire copper plating layer occurs. In addition, since the copper plating layers of all regions except for the copper protrusions are removed, the loss of the copper plating layers increases, resulting in an increase in manufacturing cost. In addition, there has been a problem that an expensive electroless chemical plating process should be performed.

In addition, in order to solve the problems caused by the formation of via holes, a copper plate having copper protrusions may be manufactured separately from the outside, and then pressed on the upper and lower surfaces of the center board on which the internal circuits are formed, thereby manufacturing a build-up multilayer printed circuit board.

4A to 4E are cross-sectional views illustrating a method of manufacturing a multilayer printed circuit board formed by pressing separately manufactured copper protrusions.

Referring to FIG. 4A, a predetermined conductive plate in which the first copper plate 42, the nickel plate 44, and the second copper plate 46 are sequentially stacked is provided. The first copper plate 42 is a conductive copper plate to be an external circuit through a subsequent patterning process, and the second copper plate 46 is a conductive copper plate on which copper protrusions are to be formed. Therefore, the first copper plate 42 is formed thin, but the second copper plate 46 is formed to a thickness of about 100 μm. In addition, the nickel plate 44 is a film serving as a barrier for protecting each plate during patterning between the first copper plate 42 and the second copper plate 46.

Referring to FIG. 4B, the second copper plate 46 is patterned to form a copper protrusion 48. The patterning forms the photoresist pattern 50 on the second copper plate 46 through a lithography process. An etching process using the photosensitive film pattern 50 as an etching mask is performed to remove the second copper plate 46 to form a copper protrusion 48. The predetermined strip process is performed to prepare a conductive plate having copper protrusions.

Referring to FIG. 4C, a center substrate 52 having an internal circuit 54 is provided. That is, the internal circuit 54 is formed by etching the copper foil of the center substrate 52 on which copper foil is coated on both surfaces.

Referring to FIG. 4D, the conductive plate on which the copper protrusions 48 are formed is pressed onto the center substrate 52 having the internal circuits 54 formed on both surfaces thereof. At this time, the copper protrusion 58 of the conductive plate and the internal circuit 54 of the center substrate 52 are electrically connected. Further, the insulating plate 56 is filled between the conductive plate and the center circuit board 52. Thereafter, the first copper plate 42 of the conductive plate can be patterned to produce an external circuit.

As described above, the conductive plate on which the copper protrusions are formed may be pressed to produce a printed circuit board having a desired number of layers. However, in the crimping of the conductive plate and the center board, there is a problem that the entire circuit board laminated in a multilayer becomes defective when a small alignment error occurs. In addition, since the predetermined three-layer predetermined plate must be used, the material is limited, and the manufacturing cost increases.

Therefore, in order to solve the above problems, the present invention can simultaneously form internal circuit patterns and copper protrusions on both sides of the multi-layered central substrate through a self-aligning circuit and bump forming process. The build-up multilayer printed circuit board which can prevent the plating error occurring when the copper plating layer is formed, prevent the enormous loss of the copper plating layer in advance, and prevent the alignment error between the lower circuit pattern and the upper copper bump. Its purpose is to provide a method for producing the same.

A central substrate according to the present invention, at least one internal circuit formed on the central substrate, at least one barrier film formed on the internal circuit and at least one metal protrusion formed on the barrier film, the internal circuit Provided is a printed circuit board on which a metal protrusion is formed.

The present invention also provides a method of manufacturing a printed circuit board in which internal circuits of upper and lower layers are connected through metal protrusions through a self-aligning circuit and a protrusion forming process that can simultaneously form an internal circuit and a metal protrusion using a barrier film pattern.

The barrier layer pattern, the internal circuit, and the metal protrusion may be formed in at least one layer.

The self-aligning circuit and the protrusion forming process may include forming a first barrier layer pattern on a metal layer of the central substrate, the first barrier layer pattern protecting a region where an internal circuit is to be formed, and both side surfaces of the central substrate on which the first barrier layer pattern is formed. Forming a first metal plating layer on the substrate, selectively forming a second barrier film on the first metal plating layer, and performing a self-aligned etching process using the first barrier film pattern and the second barrier film as an etching mask. By etching the first metal plating layer and the metal layer to form the metal protrusions and the internal circuit.

After the forming of the first metal plating layer, the method may further include selectively forming the second metal plating layer for the metal protrusions on the first metal plating layer, and further, forming the metal protrusions and the internal circuit. The method may further include the step of removing the first barrier layer pattern and the second barrier layer, as well as after the forming of the metal protrusion and the internal circuit, the internal circuit and the metal protrusion formed thereon. The method may further include forming an insulating layer and a conductor layer above and below the center substrate.

The barrier layer pattern may be formed of a material having different etching characteristics from the internal circuit and the copper protrusion. In addition, when the first and second metal plating layers are formed, materials having different electrical characteristics may be used.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention in more detail. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the embodiments are intended to complete the disclosure of the present invention, and to those skilled in the art to fully understand the scope of the invention. It is provided to inform you. Like numbers refer to like elements in the figures.

The self-aligning circuit and the protrusion forming step of the present invention form a first barrier film having the same pattern as the target circuit pattern on the copper foil, and the same pattern as the target protrusion on the plating layer formed with a predetermined thickness on the first barrier film. After the formation of the second barrier film, the process refers to a process of simultaneously forming a circuit pattern and a projection through an etching process using the first and second barrier films as an etching mask. In this case, the first and second barrier films use materials different in etching characteristics from the circuit pattern and the protrusions. Here, the first barrier film may use a conductive material having different etching characteristics, and the second barrier film may use a conductive material or non-conductive material having different etching characteristics.

Hereinafter, an example of the manufacturing method of the printed circuit board of the present invention using the above-described self-aligning circuit and the protrusion forming step will be described in detail with reference to the drawings.

5A to 5I are cross-sectional views illustrating a method of manufacturing a build-up multilayer printed circuit board according to an exemplary embodiment of the present invention.

Referring to FIG. 5A, a central substrate 100 having a metal layer 100c formed on upper and lower surfaces thereof is manufactured. As the center substrate 100, a double-sided copper clad laminate having copper coated on both surfaces of the insulating layer 100a is used. In addition, a double-sided or multi-layered substrate may be used as the central substrate 100. A predetermined through hole may be formed in the double-sided copper clad laminate, and a predetermined plating layer may be formed on the inner wall of the through hole to connect the upper and lower metal layers. Subsequently, the through hole may be filled with a predetermined filler 100b to manufacture the center substrate 100 to which the upper and lower metal layers are connected. It is preferable to use copper as said metal layer 100c. In addition, as the filler, it is preferable to use an insulating material such as ink and resin.

Referring to FIG. 5B, the first nickel plating layer pattern 120 is formed in a region where an internal circuit is to be formed.

To this end, first, a photoresist film is coated on upper and lower surfaces of the center substrate 100, and then a photolithography process using a predetermined mask is performed to form the first photoresist mask pattern 110. Photolithographic etching refers to an exposure and development process using a mask. In the first photoresist mask pattern 110 formed by the above-described method, an area in which an internal circuit is to be formed is opened, and the remaining regions are formed in a pattern shielded by the photoresist film. A nickel plating process using the first photoresist mask pattern 110 as a plating resist is performed to form the first nickel plating layer 120 in an area exposed by the first photoresist mask pattern 110. Nickel plating can be formed using various surface treatment methods such as electroplating and electroless plating. As such, the first nickel plating layer pattern 120 may be effectively formed only on a target region without forming a nickel plating layer on the entire center substrate 100 using the photoresist mask pattern, and the first nickel plating layer pattern 120. ) Can be used as a barrier film to simultaneously form a copper protrusion and an internal circuit pattern in a subsequent step. For this reason, in the present invention, any conductive material having an etching difference (etching characteristic difference) not only with nickel but also with the lower copper foil may be used. For example, a metal paste may be printed.

Thereafter, the first photoresist mask pattern 110 is removed through a predetermined strip process.

Referring to FIG. 5C, a first copper plating layer 130 is formed on upper and lower surfaces of the central substrate 100 on which the lower first nickel plating layer pattern 120 is formed. The first copper plating layer 130 may be formed through various plating processes for surface treatment. In the present embodiment, the first copper plating layer 130 may be formed through electroplating. In addition, the first copper plating layer 130 is formed to a height of about 10 to 90% of the total height of the copper protrusion to be formed through a subsequent process. As a result, the loss of the copper plating layer and the difficulty of etching may be solved by forming the entire copper protrusion through one plating and etching. As a result, cost can be reduced and plating variation can be eliminated.

Referring to FIG. 5D, a second copper plating layer 150 and a second nickel plating layer 160 for copper protrusions are selectively formed on the first copper plating layer 130.

In order to selectively form the second copper plating layer 150 and the second nickel plating layer 160, first, a photosensitive film is coated on the first copper plating layer 130. A photolithography process using a predetermined photoresist mask is performed to form a second photoresist mask pattern 140. The second photoresist mask pattern 140 exposes the first copper plating layer 130 of the region where the copper protrusion is to be formed and shields the region where the copper protrusion is not formed. In addition, the region exposed by the second photosensitive film mask pattern 140 has the same shape and the same width as the target copper protrusion.

The second copper plating layer 150 is formed by performing a plating process using the second photoresist mask pattern 140 as a plating resist. The second copper plating layer 150 is preferably formed through an electroplating process.

At this time, the first and second copper plating layers 130 and 150 form the copper protrusions of the present invention through a subsequent process. When the height of the copper protrusions is determined, and as described above, when the first copper plating layer 130 is formed to about 10 to 90% of the height, the second copper plating layer 150 is formed to a height of 90 to 10%, A copper bump of the target height is formed. In addition, the plating height of the first and second plating layers may vary in accordance with process conditions such as the height of the photoresist pattern and the plating deviation. In this embodiment, the first copper plating layer 130 is formed to have a height of 50 to 80% of the total copper protrusion height, and the second copper plating layer 150 is formed to have a height of 20 to 50% of the total copper protrusion height. desirable. In the present invention, at least two or more copper plating layers may be formed to form a target copper protrusion. This will be described later. In addition, the target copper protrusion can be formed through one plating without forming the second copper plating layer.

As described above, the second copper plating layer 150 is formed on the first copper plating layer 130 of the copper protrusion region exposed by the second photoresist mask pattern 140, and then a nickel plating process is performed to perform second copper plating. The second nickel plating layer 160 is formed on the plating layer 150. In the present invention, not only the nickel plating layer but also a conductive material having different etching characteristics from the copper film below may be used.

As such, after forming the second copper plating layer 150 and the second nickel plating layer 160 on the first copper plating layer 130 in the region where the copper protrusion is to be formed, the second photoresist mask pattern ( 140).

Referring to FIGS. 5E and 5F, a first etching process using the first and second nickel plating layers 120 and 160 as an etching mask is performed to form a copper protrusion 180 and an internal circuit 170. The exposed first and second nickel plating layers 120 and 160 are removed through a second etching process.

The first etching process uses an etchant having a different etching rate (different etching rate) for the first and second copper plating layers 130 and 150 than the first and second nickel plating layers 120 and 160. Conduct. In the present exemplary embodiment, etching is performed using copper chloride as an etchant of the first etching process, but the first and second nickel plating layers 120 and 160 are used as etching masks, that is, barrier layers. That is, the first copper plating layer 130 except for the region where the copper protrusions are to be formed is removed, and the metal layer 100c is removed except for the lower region of the second nickel plating layer 160 (that is, the internal circuit region). As a result, the copper protrusions 180 formed of the first and second copper plating layers 130 and 150 are formed, and the internal circuit 170 is formed. As described above, the present invention can simultaneously form the copper protrusion and the internal circuit using the pre-formed barrier film.

Thereafter, a second etching process is performed to remove a portion of the first nickel plating layer 120 remaining on the copper protrusion 180 and the second nickel plating layer 160 exposed on the internal circuit 170. The second etching process uses an etchant having different etching characteristics for the first and second nickel plating layers 120 and 160 than the first and second copper plating layers 130 and 150, but in this embodiment, iron chloride is used. desirable. Of course, the next step can be performed without performing the second etching step.

In the present invention, a predetermined washing step may be performed together for each step of the above-described steps. In addition, at this time, the passive element (R, L, C) of the desired characteristics can be manufactured by injecting a metal having different electrical characteristics into each copper plating layer.

Referring to FIG. 5G, the RCC 200 may be stacked above and below the center substrate 100 on which the internal circuit 170 and the copper protrusion 180 are formed.

The RCC 200 refers to an adhesive insulating resin 190 coated on one surface of the copper foil 195. The RCC 200 is stacked on the upper and lower surfaces of the central substrate 100 through a predetermined crimping process, and the upper copper foil 195 and the copper protrusion 180 on the surface of the RCC 200 are electrically and physically connected.

Subsequently, the process described above with reference to FIGS. 5B and 5F may be repeatedly applied to form a multilayer internal circuit 250 and a copper protrusion 240 connecting them.

That is, as shown in FIGS. 5H and 5I, a third nickel plating layer pattern 210 is formed on the copper foil of the RCC 200, and then a third copper plating layer 220 is formed thereon. A fourth copper plating layer pattern 230 is formed on the third copper plating layer 220, and a fourth nickel plating layer pattern (not shown) is formed thereon. Thereafter, an etching process is performed to etch the third and fourth copper plating layers 220 and 230 except for the lower portions of the third and fourth nickel plating layers 210, and to etch the copper foil 195 on the RCC 200. The copper protrusion 180 and the upper internal circuit 250 are formed. Thereafter, the remaining third and fourth nickel plating layers 210 are removed. As a result, the internal circuit 170 and the upper internal circuit 250 are connected by the copper protrusion 180, and the upper copper protrusion 240 is formed thereon. In addition, the upper copper protrusion 240 is connected to a circuit thereon when further stacking an RCC layer (not shown).

As described above, the present invention can simultaneously form a copper protrusion and an internal circuit by using a nickel plating layer as an etching mask, and perform selective copper plating using a first copper plating and a mask on the entire structure to form a copper protrusion when forming a copper protrusion. The etching amount can be reduced.

In addition, by applying the self-aligning circuit and the copper protrusion forming process of the present invention, it is possible to manufacture a variety of shapes of the copper protrusions (height, width, the number of laminated films, etc.). For example, it is possible to form a copper protrusion in which a plurality of copper plating layers are laminated, or to form a copper protrusion having a stepped step, and the width thereof can be formed thinner than in the prior art. . In addition, a predetermined PSR may be formed on the build-up multilayer printed circuit board completed through the above-described process.

6 to 9 are cross-sectional views for describing other exemplary embodiments of the present invention.

Referring to FIG. 6, the present invention forms a metal layer 610a of the central substrate 600 and a separate metal plating layer 610b thereon, and then forms a self-aligning circuit and a copper protrusion forming process thereon. In this case, the copper protrusion 630 made of a single copper plating layer and the internal circuit 615 made of two metal layers may be formed.

That is, the metal plating layer 610b is formed on the metal layer 610a of the center substrate 600 through a plating process. The first nickel plating layer pattern 620 is formed in the region where the internal circuit is to be formed on the metal plating layer 610b. As described above with reference to FIG. 5, the first nickel plating layer pattern 620 forms a nickel plating layer using a photosensitive film pattern. Subsequently, a copper plating layer is formed on the entire structure, and a second nickel plating layer pattern (not shown) is formed in a region where a copper protrusion is to be formed thereon. The second nickel plating layer pattern may also be formed in the same manner as the first nickel plating layer pattern 620. Thereafter, self-aligned etching using the first and second nickel plating layers 620 as an etching mask is performed to etch the copper plating layer, the metal layer 610a and the metal plating layer 610b, and then the exposed first and second nickel plating layers. 620 is removed to form a copper protrusion 630 and an internal circuit 615. In this case, the copper plating layer may be selectively formed only in a region where the copper protrusion is to be formed using the photosensitive film as described with reference to FIG. 5 to form the copper protrusion 630. That is, after forming the copper plating layer pattern and the second nickel plating layer pattern thereon, the metal layer 610a and the metal plating layer 610b are etched through a self-aligned etching process to form a plurality of metal layers under the copper protrusion 630. Internal circuits 615 may be formed.

In addition to this, a positive photoresist may be used instead of the second nickel plating layer. As a result, a process for plating the second nickel plating layer and a process for removing the second nickel plating layer may be omitted. That is, after forming a copper plating layer as described above, a photosensitive film pattern using a positive photoresist is formed thereon. Due to the positive photoresist characteristic, the region exposed to light remains, and the photoresist pattern using the same is formed in the same pattern as the second nickel plating layer described above (copper protrusion region shielding). Next, a self-aligned etching process using the photosensitive film pattern and the first nickel plating layer 620 as an etching mask may be performed to form the copper protrusion 630 and the internal circuit 615. Thereafter, the photoresist pattern is removed through a predetermined strip process. As described above, the photoresist pattern using the positive photoresist may simplify the manufacturing process of the build-up multilayer printed circuit board and reduce the manufacturing cost.

Referring to FIG. 7, an inner circuit 715 made of a multilayer metal layer and a copper protrusion 740 made of a multilayer copper plating layer may be formed thereon.

Here, the internal circuit 715 and the copper protrusion 740 are simultaneously formed through a self-aligning process, but each metal layer and the copper plating layer constituting the same may be formed and etched in various ways. For example, the metal plating layer 710b is formed on both surfaces of the central substrate 700 on which the metal layer 710a is formed, and the first nickel plating layer pattern 720 is formed thereon. First and second copper plating layers 730a and 730b are formed on the entire structure, and a third copper plating layer 730c using a photosensitive film pattern is formed thereon. Thereafter, a second nickel plating layer pattern (not shown) is formed on the third copper plating layer 730c. Thereafter, the first to third copper plating layers 730a to 730c are etched through a self-aligned etching process using the first and second nickel plating layers 720 as etching masks to form the copper protrusions 740, and the metal plating layer 710b. ) And the metal layer 710a are etched to form the internal circuit 715. Thereafter, the remaining nickel plating layer is removed. Of course, the present invention is not limited thereto, and the first to third copper plating layers 730a to 730c may be formed of one plating layer. To this end, a thick photoresist pattern is formed on the first nickel plating layer pattern 720. The photosensitive film pattern is formed to open the first nickel plating layer pattern 720 in the region where the copper protrusion is formed. A copper plating layer may be selectively formed on the open first nickel plating layer 720. As a result, the copper protrusions 740 may be formed. Also. After forming the second nickel plating layer on the copper plating layer, the photosensitive film pattern may be removed, and an internal circuit may be formed by performing a self alignment etching process. In addition, after the first copper plating layer 730a is plated on the center substrate 700 on which the first nickel plating layer 720 is formed, the second copper plating layer 730a may be selectively formed on the region where the copper protrusion 740 is to be formed using the photosensitive film pattern. Third copper plating layers 730b and 730c may be formed. Of course, not only this but various order and method of process can be applied.

Referring to FIG. 8, a copper protrusion 840 having a stepped step and an internal circuit 810 may be simultaneously formed. This can also be formed by self-alignment using the nickel plating layer described in FIG. 5 described above.

That is, the first nickel plating layer pattern 820a is formed on the central substrate 800 on which the metal layer is formed. The first copper plating layer 830a is formed on the upper portion thereof, and the second nickel plating layer pattern 820b is formed on the upper portion thereof. A second copper plating layer 830b is formed on the second nickel plating layer pattern 820b using a photosensitive film pattern, and a third nickel plating layer pattern (not shown) is formed thereon. The third nickel plating layer pattern is smaller than the size of the second nickel plating layer pattern 820b. Thereafter, an etching process using the first to third nickel plating layer patterns 820a and 820b as an etching mask is performed to form the copper protrusion 840 and the internal circuit 810 having a predetermined step.

Referring to FIG. 9, the width of the copper protrusion 940 for connecting the inner circuit 910 of the upper and lower layers may be very narrow.

That is, the first nickel plating layer pattern 920a is formed on the central substrate 900 on which the metal layer is formed. The first copper plating layer 930a is formed on the first nickel plating layer pattern 920a, and the second nickel plating layer pattern 920b is formed on the first nickel plating layer pattern 920a. A second copper plating layer 930b is formed on the second nickel plating layer pattern 920b using a photosensitive film, and a third nickel plating layer pattern 920c is formed thereon. The third copper plating layer 930c is formed on the third nickel plating layer pattern 920c, and the fourth nickel plating pattern (not shown) is formed on the third copper plating layer 930. An etching process using the plating pattern 920 as an etching mask may be performed to simultaneously form a copper protrusion 940 having a very thin width and an internal circuit 910 under the copper protrusion 940. In this case, a multilayer copper plating layer may be formed, which preferably forms at least two or more plating layers according to the height of the copper protrusions. In addition, when the first copper plating layer 930a and the second copper plating layer 930b are formed, a conductive layer having different electrical characteristics may be formed in at least one plating layer to manufacture a passive device having desired characteristics.

The photoresist pattern may be formed by applying a liquid photoresist at least once and then using a photolithography process using a mask. The photoresist may be pressed onto the top and bottom surfaces of the center substrate by roller pressing. It may be. In addition, in the case of stacking a multi-layered central substrate, an oxide layer may be formed on the upper and lower portions of the central substrate on which the internal circuit and the copper protrusion are formed to increase the adhesion. In addition, the prepreg and the copper foil serving as the insulating layer on the upper lower surface of the center substrate on which the oxide layer is formed as described above, or the copper foil to be the internal circuit and the upper circuit by applying a constant temperature and pressure to the RCC under vacuum. Can be connected. When a predetermined temperature and pressure are applied in a vacuum state, it penetrates through the insulating component of the prepreg and the RCC, and physical contact is possible between the copper foil and the copper protrusion, and the interlayers can be electrically connected. Another substrate can be further formed by using the substrate as a center substrate again. In the copper plating layer of the present invention, a predetermined impurity may further participate in addition to copper, and a predetermined metal material may be used to change the electrical properties of the plating layer.

Therefore, as described above, the present invention may not perform an etching process for forming a separate internal circuit. In addition, since the copper plating layer is not formed thick at one time, plating variation can be eliminated, and a separate plating layer having a target thickness is selectively formed on the upper portion of the copper plating layer by using a photosensitive film, and then the copper plating layer previously formed is etched to copper. By forming protrusions, the amount of etching of the copper plating layer may be reduced. That is, the plating layer of the desired thickness can be formed in a required part. Thereby, the material cost of the multi-layered central circuit board having the copper protrusions can be reduced, and the cost can be reduced. In addition, it can be easily adjusted to target the circuit thickness or the thickness and width of the copper projection corresponding to the circuit. In addition, one etching process may be performed to simultaneously form a copper protrusion and an internal circuit at a time.

As described above, the present invention can form an internal circuit and a copper protrusion at the same time through a self-aligning circuit and a projection forming step, thereby manufacturing a build-up multilayer printed circuit board for completing the interlayer connection.                     

In addition, the copper protrusion and the internal circuit may be simultaneously formed by performing one etching process without performing an etching process for forming a separate internal circuit.

In addition, after forming the first copper plating layer of a thin thickness, and selectively forming a second copper plating layer in the region where the copper protrusions are to be formed thereon to remove the first copper plating layer in the region except the copper protrusion region to remove the copper protrusions By forming, the copper plating layer is not formed thick at one time, thereby eliminating the plating variation, and reducing the amount of etching of the copper plating layer.

In addition, a plating layer having a desired thickness can be formed on a required portion, and material costs can be reduced when fabricating a multi-layered central circuit board having copper protrusions, thereby reducing costs.

In addition, it can be easily adjusted to target the thickness and width of the copper protrusion corresponding to the internal circuit.

Claims (9)

Center substrate; At least one internal circuit formed on the central substrate; At least one barrier film formed on the internal circuit; And At least one metal protrusion formed on the barrier film, The printed circuit board is formed with the internal circuit and the metal projection at the same time. A method of manufacturing a printed circuit board in which internal circuits of the upper and lower layers are connected through metal protrusions through a self-aligning circuit and a protrusion forming process capable of simultaneously forming an internal circuit and a metal protrusion using a barrier film pattern. The method of claim 2, The barrier layer pattern, the internal circuit and the metal protrusions are formed in at least one layer. The method of claim 2, wherein the self-alignment circuit and the projection forming step, Forming a first barrier layer pattern on a metal layer of the central substrate to protect a region where an internal circuit is to be formed; Forming first metal plating layers on both sides of the central substrate on which the first barrier layer pattern is formed; Selectively forming a second barrier film on the first metal plating layer; And Performing a self-aligned etching process using the first barrier layer pattern and the second barrier layer as an etching mask to etch the first metal plating layer and the metal layer to form the metal protrusions and the internal circuits. How to make. The method of claim 4, wherein after forming the first metal plating layer, And selectively forming the second metal plating layer for the metal protrusion on the first metal plating layer. The method of claim 4, wherein after forming the metal protrusions and the internal circuit, The method of claim 1, further comprising removing the first barrier layer pattern and the second barrier layer. The method of claim 4, wherein after forming the metal protrusions and the internal circuit, And forming an insulating layer and a conductor layer above and below the center substrate on which the internal circuit and the metal protrusion are formed. The method of claim 2, The barrier layer pattern is a manufacturing method of a printed circuit board using a material different from the etching characteristics of the internal circuit and the copper projections. The method according to claim 4 or 5, Method of manufacturing a printed circuit board using a material having a different electrical characteristics when forming the first and second metal plating layer.

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